Abstract: The disclosure relates to a microphone assembly including a multibit analog-to-digital converter configured to generate N-bit samples representative of a microphone signal. The microphone assembly also includes a first digital-to-digital converter configured to generate a corresponding M-bit digital signal based on N-bit digital samples, wherein N and M are positive integers and N>M. The microphone assembly may include a data interface configured to repeatedly receive samples of the M-bit digital signal and write bits of the M-bit digital signal to a data frame.

Abstract: A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.

Abstract: A sensor includes an analog front end having a circuit element responsive to a clock signal and a clock generating circuit configured to generate the clock signal having blanking time periods during which the clock signal is held at a constant level, wherein the circuit element is not operational during the blanking time periods. The blanking time periods correspond to time periods during which transitions of a common mode input voltage to the sensor are expected to occur.

Abstract: A system includes a management device and nodes that execute plural jobs in parallel. When a total electric-power consumption of the nodes reaches a threshold, the management device extracts a first job of the largest electric-power consumption from among the plural jobs, based on information about an electric-power consumption of each node and information about the plural jobs that are executed in parallel by the nodes. The management device reduces the electric-power consumption of a first node that executes the first job when a remaining execution time of the first job, which indicates a period of time from a current time until a scheduled end time of the first job, is longer than or equal to a predetermined time, and reduces the electric-power consumption of a second node that does not execute the first job, when the remaining execution time of the first job is shorter than the predetermined time.

Abstract: An electronic device and method are provided. The electronic device includes a first connector including first conductive pins arranged according to a first protocol, a second connector including second conductive pins arranged according to a second protocol and different in number, and a control circuit operatively coupled to the first and second connector. The control circuit detects coupling to an external device through the first connector by at least one of the first conductive pins, receives profile information including at least one of: a power supply device operatively coupled to the second connector and identification information for an external device, and sets a charging path within the electronic device between the first connector and the second connector using at least one of the first conductive pins and the at least one of the second conductive pins coupled to the power supply device.

Abstract: An information processing apparatus includes first and second power feed control portions and a storage processing portion. The first power feed control portion stops power feed to a nonvolatile first storage portion when reading or writing data from/to the first storage portion is completed. In a case where power feed to the first storage portion is stopped, the storage processing portion stores specific data among data stored in the first storage portion into a second storage portion. When an access request for accessing data in the first storage portion has been received: when access-target data specified in the access request is not stored in the second storage portion, the second power feed control portion resumes power feed to the first storage portion; and when the access-target data is stored in the second storage portion, does not resume the power feed to the first storage portion.

Abstract: A system and method generates contextual information for a source model. An identification of one or more first model elements of interest within the source model may be received. One or more constraints on inputs of selected model elements also may be received. A scope of analysis regarding outputs of the first model elements may be specified. The contextual information may be derived automatically for the one or more first model elements. The contextual information may include one or more model elements, signals, or states that are contained with the scope of analysis while execution of the source model is limited by the one or more constraints. The derived contextual information may be provided to an output device.

Abstract: The disclosure is related to a method, an apparatus and a computer-readable medium for controlling a terminal. The method includes: obtaining a cover closing instruction where the cover closing instruction indicates that an upper cover and a lower cover of the terminal are closed; obtaining, in response to the cover closing instruction, a program running on the terminal; and determining an operation to be performed by the terminal based on the program running on the terminal, where the operation to be performed by the terminal includes any one of: shutdown, sleep, maintaining normal operation, or screen off.

Abstract: A plurality of processing entities of a processor complex is maintained, wherein each processing entity has a local cache and the processor complex has a shared cache and a shared memory. One of the plurality of processing entities is allocated for execution of a critical task. In response to the allocating of one of the plurality of processing entities for the execution of the critical task, other processing entities of the plurality of processing entities are folded. The critical task utilizes the local cache of the other processing entities that are folded, the shared memory, and the shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task.

Abstract: A storage device and a refresh method thereof are provided. The storage device includes at least a first processing core configured to operate by receiving a first power from a host, a second processing core separate from the first processing core, at least a first three-dimensional (3D) flash memory, a power module and a retention management module supplied with a second power from the power module when the first power is not supplied from the host. The retention management module is configured to refresh a part of the first 3D flash memory using the second processing core. The retention management module is configured to be woken up at intervals of a first period to refresh the part of the first 3D flash memory.

Abstract: A method for managing two baseboard management controllers comprises connecting to a first baseboard management controller, sending an instruction to the first baseboard management controller, determining whether the instruction comprises a bridge parameter, when the instruction comprises the bridge parameter, sending the instruction to a second baseboard management controller through a bus, generating a response signal by the second baseboard management controller, and receiving the response signal by the first baseboard management controller and sending the response signal to an administration interface; otherwise, executing a corresponding operation according to the instruction by the first baseboard management controller and sending an operation result to the administration interface.

Abstract: A KTV player in communication with at least one song server is configured to upload a song list of a song database to the song server, obtain a song playback list from the song server, obtain corresponding music scores and pitch curves from the song server according to the song playback list, obtain corresponding songs according to the song playback list, display the songs in sequence on a display, and display the corresponding music scores and pitch curves on the display synchronously with the songs. The song playback list is sent by a mobile terminal in communication with the song server.

Abstract: Embodiments are directed to a method of optimizing power consumption in an electrical device. The method includes receiving, by a processor, instructions to enter a wait state, and identifying, by the processor, a parameter associated with the instructions to enter a wait state. The method continues with initiating, by the processor, instructions to enter a low-power mode based on the parameter, initiating, by the processor, instructions to exit a low-power mode based on the parameter, and providing, via a user interface, a user with notice of a current state of the processor. The parameter includes runtime information, instructional information, and scheduled operations.

Abstract: According to various embodiments, a wearable device may be provided. The wearable device may include: a display panel having integrally formed a first display portion and a second display portion; and a driver circuit configured to control the first display portion with a first frequency and to control the second display portion with a second frequency.

Abstract: An image processing method includes steps of receiving an image sequence; when at least one object appears in the image sequence, analyzing a moving trajectory of each object; extracting at least one characteristic point from each moving trajectory; classifying the at least one characteristic point of each moving trajectory within a predetermined time period into at least one cluster; and storing at least one characteristic parameter of each cluster.

Abstract: A rechargeable power module (RPM) may include a rechargeable energy storage device such as a battery or capacitor, a charging circuit, a direct-current (DC) to DC converter, a low drop-out (LDO) voltage regulator and a controller. The charging circuit provides the rechargeable energy storage device with a charging current based on power requirements of device under test and the state of charge, or storage, of the energy storage device.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.

Abstract: A method of operating a touchless user interface on an electronic device is disclosed. The electronic device is configured to determine information regarding the position and/or movement of an input object. The method has the steps of: deciding that an engagement gesture has been performed; deciding that a related input gesture has been performed; and carrying out an operation on the device on the basis of the input gesture only if the engagement gesture has been recognized and if the input gesture is one of a subset of possible input gestures determined by the engagement gesture.

Abstract: A display device includes a plurality of latch circuits which latch gradation data that is used to drive a plurality of data lines, a plurality of D/A converters which convert gradation data that is latched to the plurality of latch circuits to a plurality of analog signals, a plurality of amplifiers which generate a plurality of gradation signals by respectively amplifying the plurality of analog signals output from the plurality of D/A converters, and an analysis circuit that analyzes gradation data that is latched to the plurality of latch circuits and reduces direct current that flows in at least one amplifier or at least one D/A converter according to an analysis result.

Abstract: A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor module coupled to an input/output (I/O) module via a connector. The processor module to communicate with the I/O module via the connector to store and retrieve data. The processor module is a separate hardware unit from the I/O module.

Abstract: An integrated circuit may be provided with cryptocurrency mining capabilities. The integrated circuit may include control circuitry and a number of processing cores that complete a Secure Hash Algorithm 256 (SHA-256) function in parallel. Logic circuitry may be shared between multiple processing cores. Each processing core may perform sequential rounds of cryptographic hashing operations based on a hash input and message word inputs. The control circuitry may control the processing cores to complete the SHA-256 function over different search spaces. The shared logic circuitry may perform a subset of the sequential rounds for multiple processing cores. If desired, the shared logic circuitry may generate message word inputs for some of the sequential rounds across multiple processing cores. By sharing logic circuitry across cores, chip area consumption and power efficiency may be improved relative to scenarios where the cores are formed using only dedicated logic.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

Abstract: A computer system detects that a mobile device of a user is in a location that exceeds a threshold distance from a second device of the user. Based on at least the detecting, the computer system switches the mobile device to stealth mode, wherein switching the mobile device to stealth mode includes determining an image that visually matches a surface directly below the mobile device, and displaying the image on at least one display of the mobile device. The computer system determines that the second device of the user is located within the threshold distance of the mobile device. Based on the determining, the computer system initiates one or more actions to alert the user as to the location of the mobile device.

Abstract: Methods and systems for supplying more power than a power limit to a powered device (PD) if the PD is capable of receiving power more than the power limit, and receiving power more than the power limit from a power sourcing equipment (PSE) if the PSE is capable of supplying power more than the power limit. The PD and the PSE operates in a power over Ethernet (PoE) environment. The system comprises a power receiving section and a power supply section. The power receiving section comprises a first power-receiving circuit and a second power-receiving circuit, where the first power-receiving circuit is used when receiving power up to the power limit, and the second power-receiving circuit is used when receiving power more than the power limit.

Abstract: The authentication of a client to multiple server resources with a single sign-on procedure using multiple factors is disclosed. One contemplated embodiment is a method in which a login session is initiated with the authentication system of a primary one of the multiple server resources. A first set of login credentials is transmitted thereto, and validated. A token is stored on the client indicating that the initial authentication was successful, which is then used to transition to a secondary one of the multiple resources. A second set of login credentials is also transmitted, and access to the secondary one of the multiple resources is granted on the basis of a validated token and second set of login credentials.

Abstract: Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.

Abstract: A display apparatus including a display configured to display an image; a connecting section configured to connect with an external apparatus that includes at least one operating section and a charging section to be charged with power to be supplied to the operating section; a power supply configured to supply power to the external apparatus connected to the connecting section; and a controller configured to receive information about power used by at least one operating section of the external apparatus connected to the connecting section, determine a level of power supplied to the external apparatus according to the received power information and usage power of the display, and control the power supply to supply power having the determined level to the external apparatus.

Abstract: This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.

Abstract: A microcontroller that can be configured to selectively operate in a synchronous mode or an asynchronous mode, and a method of selectively switching the operating mode is described. The microcontroller can include a processor and a system controller. The processor can be configured to operate synchronously in a synchronous operating mode and asynchronously in an asynchronous operating mode. The processor can also be configured to generate a processor idle status signal indicative of the processor operating in a reduced power mode, and generate a programming signal. The system controller can be configured to generate an asynchronous mode signal based on the programming signal and the processor idle status signal, and provide the asynchronous mode signal to the processor to control the processor to selectively operate in the synchronous operating mode and in the asynchronous operating mode.

Abstract: Cloud services require the outward appearance of unlimited resources with flexible availability for varying demand. However, while on-demand allocation and deallocation of resources may seem efficient, there are significant cases where simply allocating and deallocating resources just in response to demand results in inefficiencies. As discussed herein, cloud services can be made more efficient by deallocating resources based on delays incurred between when resources are requested to be deallocated and reallocated and when they actually are deallocated and allocated, and for how long the resource would be returned to the cloud before needing to be reallocated. Deallocating resources more efficiently not only gives a direct performance improvement, but also indirect, since deallocated resources may not be available again when demand increases.

Abstract: A mechanism is provided for opportunistic handling of freed data in data de-duplication. Responsive to receiving a request to store a file in a storage device, the file is mapped to a set of virtual blocks. For each virtual block in the set of virtual blocks: a hash value is computed, a determination is made as to whether the computed hash value appears within a previously-used information table as associated with an existing data block, and, responsive to the computed hash value appearing within a previously-used information table as associated with an existing data block, a data block entry and hash value associated with the existing data block is moved to a de-duplication information table. The virtual block is then stored as a reference to the existing data block.

Abstract: A communication device includes a plurality of controllers, a plurality of buses that transmit transmission information, and a gateway to which the plurality of buses are collectively connected. Each of the plurality of controllers has a pattern table that defines, for each piece of the transmission information, a transmission bus pattern, and controls the input and output of the transmission information according to the pattern table. Each of the plurality of controllers is connected to at least two buses, and outputs, to the gateway via all of the connected buses, check information for a confirmation of connections to the connected buses. The gateway determines an interrupted bus from which no check information is input, and outputs, to each of the plurality of controllers, a route switch instruction instructing use of a pattern table that does not include the interrupted bus(es).

Abstract: In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.

Abstract: This disclosure generally provides an input device modulates a reference voltage used to provide power to a plurality of power supplies and acquires, while modulating the reference voltage, first resulting signals from a plurality of sensor electrodes simultaneously at a central receiver. In input device also acquires second resulting signals from the sensor electrodes at a plurality of local receivers and mitigates an effect a grounding condition has on the second resulting signal using the first resulting signals.

Abstract: The invention provides for mobile radio communications device (10) for operation within a mobile radio communications network and arranged to employ one of a plurality of possible power saving modes, and arranged to send non-access stratum or access stratum signalling (14) to the network including an indication of at least one of the said plurality of possible power saving modes, and responsive to which indication the network (12) is arranged to return confirmation (16) of the power saving mode to be employed by the mobile radio communications device (10), the mobile radio communications device (10) further being arranged to receive the said confirmation (16) and to initiate operation of the confirmed power-saving mode (26; 38; 44).

Abstract: Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.

Abstract: A method, system and computer program product are provided for refreshing a software component without interruption. The method includes detecting when a current instance of the software component is inactive and activating a refresh process of the software component in parallel to the current instance, including starting a new instance of the software component. The method further includes monitoring a state of the current instance and, when the current instance ceases to be inactive, canceling the refresh process. The method includes determining that the refresh process is complete and switching from the current instance to the new instance of the software component.

Abstract: An adaptive block cache management method and a DBMS applying the same are provided. A DB system according to an exemplary embodiment of the present disclosure includes: a cache configured to temporarily store DB data; a disk configured to permanently store the DB data; and a processor configured to determine whether to operate the cache according to a state of the DB system. Accordingly, a high-speed cache is adaptively managed according to a current state of a DBMS, such that a DB processing speed can be improved.

Abstract: Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

Abstract: An embodiment: (a) receives a request for a measurement of a hypervisor from at least one computing node that is external to the at least one machine; (b) executes a previously measured measuring agent to measure the hypervisor, after the hypervisor is measured and booted, to generate a measurement while: (b)(i) the at least one machine is in virtual machine extension (VMX) root operation, and (b)(ii) the measuring agent is in a protected mode; (c) attest to the measurement, based on at least one encryption credential, to generate an attested measurement output; and (d) communicate the attested measurement output to the at least one computing node. The hypervisor does not include the at least one encryption credential while the measuring agent is measuring the booted hypervisor. Other embodiments are described herein.

Abstract: Power supply of ECUs connected to a communication network is optimally controlled so that power consumption is reduced. A transceiver/receiver converts a message of a differential signal received via a CAN bus into a digital signal. A select circuit determines whether the converted message is in a CAN format or a UART format. If it is in the UART format, the select circuit outputs a message to the UART circuit. A UART circuit determines whether the message matches a UART format. If matched, an ID determination circuit determines whether the input message is specifying a CAN ID of its own ECU. If it is the CAN ID of the ECU, the ID determination circuit outputs an enable signal to turn on a regulator and supply power to an MCU and an actuator.

Abstract: A multiple-chip voltage feedback technique allows multiple strings of Light Emitting Diodes (LED's) and current sinks to be efficiently powered by a DC-to-DC voltage converter. A plurality of controllers connected in a daisy chain series monitor voltages between the connected LED's and the current sinks, progressively determine the lowest voltage, and then feed the lowest voltage back to the voltage converter. The DC-to-DC voltage converter monitors this lowest voltage and adjusts its output in order to ensure that the LED strings have adequate voltage with which to function, even as the LED's have different forward voltages and the strings are asynchronously enabled and disabled.

Abstract: A method of communicating with multiple other devices by a low energy device, the method including broadcasting advertisements from the low energy device to connect, the advertisements being broadcasted at a slow rate, receiving an event at the low energy device, responsive to receiving the event, broadcasting advertisements at a high rate for a selected period of time, and connecting and disconnecting with the multiple other devices to exchange information related to the event during the selected period of time.

Abstract: A storage control apparatus obtains first-code attached data, each having target data to be written and first code information, which includes an error detection code based on the target data and information about a first write destination, attached to the target data. The storage control apparatus then obtains the target data by excluding the first code information from the first-code attached data eliminates duplication of the target data, generates second code information which includes an error detection code for the target data remaining and information about a second write destination, and writes second-code attached data including the second code information into a memory device.

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.

Abstract: An approach is provided for providing secure signing and utilization of distributed computations. A distributed computation authentication platform causes, at least in part, a signing of one or more computation closures of at least one functional flow. The distributed computation authentication platform also processes and/or facilitates a processing of the one or more signed computation closures to cause, at least in part, a transfer of the one or more signed computation closures among one or more levels, one or more nodes, or a combination thereof, wherein an execution of the one or more signed computation closures at the one or more levels, the one or more nodes, or a combination thereof is based, at least in part, on an authentication of the signed one or more computation closure.

Abstract: The disclosed technology provides for off-loading dirty data from a volatile cache memory to multiple non-volatile memory devices responsive to detection of a power failure. The arrangement of the dirty data is describable by a cache image, which is reconstructed within the volatile memory from the non-volatile memory devices responsive to detection of power restoration following the power failure.

Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.