By Shutdown Of Only Part Of System Patents (Class 713/324)
  • Patent number: 9541987
    Abstract: Methods and apparatus relating to generic host-based controller latency are described. In one embodiment, latency information, corresponding to one or more devices, is detected from a host controller that controls access to the one or more devices. Detection of the latency information is performed in response to one or more transactions that are initiated by the host controller. Other embodiments are also claimed and disclosed.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventor: Barnes Cooper
  • Patent number: 9542347
    Abstract: A microcontroller for a peripheral hub includes a plurality of host bus interface microdrivers and a corresponding plurality of host transports. A first manager client, associated with a supported peripheral device, processes messages from a first host. A host manager module routes asynchronous communications, including but not limited to HID input reports, from a client to a host via one of a plurality of supported transports via a targeted transport indicated in the communication. The host manager modules routes synchronous communications from a host to a client via a targeted transport selected from a plurality of transports.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventor: James Trethewey
  • Patent number: 9519345
    Abstract: In one example, a method includes receiving, by a computing device, an indication of a detected force applied to the computing device. The method further comprises determining, by the computing device, that the detected force matches a corresponding input that the computing device associates with a corresponding function that is executable by the computing device. The method further comprises generating, by the computing device and in response to determining that the detected force matches the corresponding input and, a non-visual output based on the corresponding function.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 13, 2016
    Assignee: Google Inc.
    Inventors: Ullas Gargi, Richard Carl Gossweiler, III
  • Patent number: 9513853
    Abstract: A data processing apparatus that has first to fourth power modes in which power consumption becomes larger in this order, and is capable of changing into a mode selected and set by a user. A receiving unit receives the instruction for bringing the data processing apparatus into the third power mode or the fourth power mode. A first transition unit brings, when the apparatus is working in the second power mode, the apparatus into the first power mode in response to the receiving unit receiving the transition instruction. A determination unit determines which mode the apparatus is to be brought into between the third power mode and the fourth power mode in response to the first transition unit bringing the apparatus into the first power mode. A second transition unit brings the apparatus into a power mode determined by the determination unit.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 6, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Tamotsu Takatani
  • Patent number: 9490799
    Abstract: An electronic device includes a transmission interface, a switch unit and a control unit. The transmission interface includes a signal reference contact and a signal transmission contact. The switch unit is coupled between the signal reference contact and a grounded layer. The control unit is coupled to the switch unit. When the control unit controls the switch unit to connect the signal reference contact and the grounded layer, the signal transmission contact is used to transmit a first signal. When the control unit controls the switch unit to disconnect the signal reference contact from the grounded layer, the signal reference contact is used to transmit a second signal.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: November 8, 2016
    Assignee: Synology Incorporated
    Inventors: Yen-Li Hsieh, Ming-Hung Tsai, Hung-Ming Tsai
  • Patent number: 9485724
    Abstract: A method for spatiotemporal control of electrical energy consumption of a telecommunications network dependent on conditions in a power grid that is responsible for supplying the telecommunications network in space and time, includes detection of an overload on a power grid due to too high power supply by exchanging of information between the power grid monitoring unit and the telecommunications control unit, and an increase in power consumption by the telecommunications network in the spatial area, through configuration of the telecommunications network components in this spatial area by the power grid monitoring unit for the period of too high power supply.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: November 1, 2016
    Assignee: DEUTSCHE TELEKOM AG
    Inventors: Christoph Lange, Heiko Lehmann
  • Patent number: 9466386
    Abstract: A method of programming a storage device comprises determining whether at least one open page exists in a memory block of a nonvolatile memory device, and as a consequence of determining that at least one open page exists in the memory block, closing the at least one open page through a dummy pattern program operation, and thereafter performing a continuous writing operation on the memory block.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: October 11, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Wook Park, Jung-Soo Kim, Jaeyong Jeong, Kitae Park, Youngsun Song
  • Patent number: 9467300
    Abstract: A network device and a method for the network device to set operation of a port are provided. The network device is connected to a set of power sourcing equipment (PSE) through a port, and the PSE powers the network device through the port. The network device includes an analysis module and a port control module. The analysis module judges whether the port of the network device is connected to the PSE. The port control module provides a port function switch instruction according to a judgment result of the analysis module, so as to enable or disable the port.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 11, 2016
    Assignee: EDGECORE NETWORKS CORPORATION
    Inventors: Kuo-Lun Chen, Wei-Ting Wang
  • Patent number: 9460483
    Abstract: Methods and apparatus are disclosed to manage power consumption at a graphics engine. An example method to manage power usage of a graphics engine via an application level interface includes obtaining a policy directive for the graphics engine via the application level interface, the policy directive identifying a threshold corresponding to power consumed by the graphics engine operating in a first graphics state. The example method also includes determining a power consumed by the graphics engine during operation. The example method also includes comparing the power consumed to the threshold of the policy directive, and when the threshold is met, setting the graphics engine in a second graphics state to cause the graphics engine to comply with the policy directive.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Kanivenahalli Govindaraju, Vincent J. Zimmer
  • Patent number: 9454214
    Abstract: In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Robert B. Bahnsen, Kanivenahalli Govindaraju, Robert C. Swanson, Mallik Bulusu
  • Patent number: 9454199
    Abstract: Servers, storage medium and methods associated with control of power management services of remote servers of a remote computing service are disclosed herein. In embodiments, a storage medium may have instructions to enable a local server to query a remote computing service having one or more remote servers. The instructions may enable the local server to receive a record from the remote computing service in response to the query. The record may include information related to power management services available from the one or more remote servers. The instructions may enable the local server to transmit power management commands, based on the information, to the remote computing service to at least partially control power consumption by the one or more remote servers. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Enrique G. Castro-Leon, John Kennedy
  • Patent number: 9438043
    Abstract: A system has a power source connected to power access points and at least one environmental control system. A threshold compare device is effective to compare the proportional load on the environmental control systems to a preset threshold. If the threshold is exceeded, unused power access points are disabled. This prevents such access points from placing additional loads on the environmental control systems. Conversely, when the proportional load on the environmental control systems drops below a preset threshold, power can be restored to the disabled power access points. A master control unit can monitor the load on the environmental control systems and either or both the environmental conditions in environment zones or the power loading of the power access points and determine whether to disable unused power outlets.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: September 6, 2016
    Assignee: Astronics Advanced Electronic Systems Corp.
    Inventors: Jeffrey Jouper, John S. Lamb
  • Patent number: 9429973
    Abstract: A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module and/or the integrated circuit. A third circuit module may, for example, determine power control information based at least in part on the monitored performance characteristic(s). The power control information may be communicated to power supply circuitry to control various characteristics of the electrical power. Various aspects of the present invention may also comprise an integrated circuit comprising a first module that monitors at least one performance characteristic of a first electrical device.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: August 30, 2016
    Assignee: Broadcom Corporation
    Inventors: Neil Y. Kim, Pieter Vorenkamp
  • Patent number: 9430152
    Abstract: Techniques for operating a storage front-end system are disclosed. The techniques include identifying a synchronous group of data storage devices across two or more enclosures, each of which comprise a plurality of data storage devices. Data across the data storage devices is accessible by a storage front-end system as an aggregate memory space. The techniques further include sending an activation request to the enclosures to synchronously activate the data storage devices in the synchronous group and performing a data maintenance task in the aggregate memory space of the data storage devices.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: August 30, 2016
    Assignee: NetApp, Inc.
    Inventor: David Slik
  • Patent number: 9423744
    Abstract: An image forming apparatus controls entry to a power save mode based on an operation state of an external interface device when an operation state of a removable user interface unit satisfies a condition for entering the power save mode.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Soo-young Kang
  • Patent number: 9423857
    Abstract: The present invention relates to a job processing apparatus including an instruction unit configured to provide an instruction to shift a power supply to an OFF state, a setting unit configured to variably set a suspended time for shifting from a suspended state to the OFF state based on a threshold of the number of rewritable times calculated by a calculation unit and a number of writing times, and a control unit configured to shift the power supply to the OFF state after the suspended time set by the setting unit has lapsed.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: August 23, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichi Konosu
  • Patent number: 9423863
    Abstract: A server system and a control method thereof are provided. The server system includes a first computing module, a power distribution board (PDB) module, a first storage apparatus, and a second storage apparatus. The PDB module is connected to the first computing module and is configured to distribute the power of the server system. The first storage apparatus and the second storage apparatus are connected to the PDB module. After finishing a boot operation, the first computing module determines whether a second computing module connected to the PDB module is present, such that the first computing module controls the PDB module to select and distribute the first storage apparatus and the second storage apparatus to the first computing module and the second computing module. Therefore, the server system can achieve different data access applications in the server system by only using a general-purpose PDB module.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: August 23, 2016
    Assignee: Wistron Corporation
    Inventor: Cheng-Kuang Hsieh
  • Patent number: 9417934
    Abstract: A system for managing operation of a “whiteboard” supported by one or more devices. A whiteboard may comprise a shared storage area allocated amongst the memories of one or more devices enabled for wireless communication. The whiteboard may be accessed by various programs, or “nodes,” resident on the devices. In at least one scenario, some nodes may provide information to a whiteboard section of one device for use by nodes that may exist on other devices. This information may be accessible via wireless communication The present invention may evaluate the requirements of the various active nodes in view of the status of the plurality of devices in order to both optimize whiteboard operation while conserving device resources.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: August 16, 2016
    Assignee: Core Wireless Licensing S.a.r.l.
    Inventors: Arto Palin, Juha-Matti Tuupola, Olli Tyrkkö
  • Patent number: 9405344
    Abstract: An integrated circuit includes a circuit including a plurality of functional blocks, a sensor associated with one of the plurality of functional blocks for sensing a state of activity thereof, and a sleep switch receiving an output from the sensor and placing the associated functional block in a sleep state in response to the sensed state of activity.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: August 2, 2016
    Assignee: MARVELL ISRAEL (M.I.S.L.) LTD.
    Inventor: Eitan Rosen
  • Patent number: 9395786
    Abstract: A method for cross-layer power management in a multi-layer system includes determining whether there is a service level violation for an application running on a hardware platform. Power consumption of the hardware platform is controlled in response to the service level violation.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: July 19, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vanish Talwar, Jeffrey S. Autor, Sanjay Kumar, Parthasarathy Ranganathan
  • Patent number: 9373957
    Abstract: Systems and methods for power balancing in power distribution networks are disclosed herein. According to an aspect, a method may be implemented at a power manager in a power distribution network including multiple computing devices. The method may include receiving vital product data associated with the computing devices. The method may also include predicting, based on the vital product data, occurrences of unbalanced power in the power distribution system upon distribution of power to the computing devices. Further, the method may include controlling application of power to the computing devices, prior to distributing power in the power distribution system, based on the predicted occurrences such that power distribution to the power distribution system is substantially balanced.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: June 21, 2016
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Shareef Alshinnawi, Gary D. Cudak, Edward S. Suffern, John M. Weber
  • Patent number: 9369036
    Abstract: A circuit includes a switching regulator that produces a first voltage supply output and that includes an operational supply input. The operational supply input may provide power for running the logic in the switching regulator. The circuit also includes a linear regulator that produces a second voltage supply output. A control circuit accepts the first voltage supply output and the second voltage supply output and includes a power output connected to the operational supply input. The control circuit is configured to pass the second voltage supply output to the power output until the first voltage supply output is established. After the first voltage supply is established, the control circuit instead passes the first voltage supply output to the power output through the control circuit. The first voltage supply output may also then provide power to the circuitry that would otherwise have been powered by the linear regulator.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: June 14, 2016
    Inventors: Eric Martin Hayes, Mark David Rutherford
  • Patent number: 9360986
    Abstract: Arrangements for managing displays of ultra-mobile devices (UMD's). Automatically or manually, a small-mode interface on a UMD screen, wherein one application window is visible, is switched to a large-mode interface.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: June 7, 2016
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: James J. Thrasher, Justin T. Dubs, Steven R. Perrin, James S. Rutledge, Michael T. Vanover, Jennifer G. Zawacki
  • Patent number: 9357483
    Abstract: A method and a device for energy saving control in the home base station environment are provided to solve the problem of energy saving control in the home base station environment. In the present invention, a source base station sends an energy saving control request to a target home base station, wherein the energy saving control request comprises the information of the target base station, the information of the source base station, and the type of the energy saving control request. After receiving the energy saving control request, the target home base station performs an energy saving control processing operation, and sends a result of the energy saving control processing to the source base station through an energy saving control response. If the energy saving control processing fails, the energy saving control response further comprises a reason for the failure and/or a wait time.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: May 31, 2016
    Assignee: ZTE CORPORATION
    Inventors: Yin Gao, Lifeng Han, Longtao Ren
  • Patent number: 9350915
    Abstract: Power saving techniques are provided for processing circuitry on image sensors. Processing circuitry may include one or more processing blocks. The processing blocks may receive pixel data in the form of lines separated by blanking time. To reduce power consumption, each processing block may have a clock that is enabled when processing data and disabled during blanking time. The processing blocks may have respective clocks that are enabled and disabled at different times. Timing control circuitry may provide a clock enable signal to a first processing block. Each processing block may receive a clock enable signal and output a time-shifted clock enable signal for a subsequent processing block.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 24, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Vickie Wu
  • Patent number: 9348382
    Abstract: In an embodiment, set forth by way of example and not limitation a USB power converter for an electronic device includes a USB bus including VBUS power line, a D? data line and a D+ data line, a variable voltage converter, a processor clock, a USB transceiver coupled to the D? data line and the D+ data line, and a processor coupled to processor clock and to the USB transceiver. Preferably, the variable voltage converter has an alternating current (AC) input, a direct current (DC) output coupled to the VBUS power line, and a voltage control input responsive to a voltage control signal to provide a plurality of voltage levels at the DC output. The process is, in this example embodiment, operative to develop the control signal based upon communication from an electronic device connected to the USB bus.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: May 24, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kenneth J. Helfrich, Sang H. Kim, Fabrizio Fraternali
  • Patent number: 9317102
    Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: April 19, 2016
    Assignee: Apple Inc.
    Inventors: Muditha Kanchana, Gurjeet S. Saund, Harshavardhan Kaushikkar, Erik P. Machnicki, Seye Ewedemi
  • Patent number: 9317139
    Abstract: According to an aspect, an electronic device includes a first face, a second face, a display unit arranged on the first surface, a notification unit arranged on the second surface, an attitude detecting unit, and a control unit. The attitude detecting unit detects whether attitude of the electronic device is a first attitude, in which the first surface faces upward in the vertical direction, or a second attitude, in which the first surface faces downward in the vertical direction. When the attitude detecting unit detects the second attitude, the control unit prevents displaying on the display unit and enables the notification unit to give a notification.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 19, 2016
    Assignee: KYOCERA CORPORATION
    Inventors: Haruyoshi Oshinome, Sanae Nishio
  • Patent number: 9317104
    Abstract: A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node includes a network port, a network chip and a control unit. The network port is connected to the network switch via a cable. The network chip detects the cable to obtain a connection state with the external network at the server node after the network switch is started, and accordingly outputs a connection state signal. The control unit turns on or shuts down the server node according to the connection state signal and an on/off state of the server node.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: April 19, 2016
    Assignee: Quanta Computer Inc.
    Inventors: Le-Sheng Chou, Sz-Chin Shih
  • Patent number: 9317096
    Abstract: Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 19, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: William L. Bircher, Madhu Saravana Sibi Govindan, Brian E. Waldecker
  • Patent number: 9317103
    Abstract: A method and system for controlling power is provided. The system is configured to selectively control a plurality of power control domains. The system may be configured to process audio data in at least one of the domains. The system may be configured to output audio data, while one or more of the power control domains is suspended.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 19, 2016
    Assignee: Broadcom Corporation
    Inventor: Gordon Hollingworth
  • Patent number: 9310874
    Abstract: There is disclosed an electronic device comprising a receiver, a display, an application processor and a sensor hub. The receiver is configured to receive notifications from a remote device. The display is configured to provide information including notifications. The application processor and the sensor hub are in communication with the display. The application processor is configured to provide instructions for displaying full screen information at the display during a non-sleep mode of the electronic device. The full screen information includes a first notification associated with information received by the electronic device during the non-sleep mode. The sensor hub is configured to provide instructions for displaying partial screen information at the display during a sleep mode of the electronic device. The partial screen information includes a second notification associated with information received by the electronic device during the sleep mode.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 12, 2016
    Assignee: Google Technology Holdings LLC
    Inventors: Michael E Gunn, Nathan M Connell, Christian L Flowers, Andrew K Wells, Long Ling
  • Patent number: 9310783
    Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: April 12, 2016
    Assignee: Apple Inc.
    Inventors: Erik P Machnicki, Gurjeet S Saund, Munetoshi Fukami, Shane J Keil
  • Patent number: 9304577
    Abstract: An apparatus comprising a memory and a controller. The memory processes a plurality of read/write operations. The controller (i) operates in a first power domain to control power savings operations, and (ii) processes the read/write operations in a second power domain. The first power domain is isolated from the second domain.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: April 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Edward Yan
  • Patent number: 9292339
    Abstract: A multi-core processor system includes a core configured to determine whether a task to be synchronized with a given task is present; identify among cores making up the multi-core processor and upon determining that a task to be synchronized with the given task is present, a core to which no non-synchronous task that is not synchronized with another task has been assigned, and identify among cores making up the multi-core processor and upon determining that a task to be synchronized with the given task is not present, a core to which no synchronous task to be synchronized with another task has been assigned; and send to the identified core, an instruction to start the given task.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: March 22, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Tetsuya Saka
  • Patent number: 9268290
    Abstract: An apparatus configured to operate in a first power state and in a second power state that consumes less power than the first power state. In a case where a predetermined condition is satisfied, when a power-supply-off drive for switching a switch to an off side using a drive unit is executed and if it is detected that a power supply to the apparatus is not cut after executing of the power-supply-off drive, a control unit shifts a power state of the apparatus from the first power state to the second power state.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: February 23, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroshi Yamamizu
  • Patent number: 9262478
    Abstract: A system and a method for initializing a streaming application are disclosed. The method may include initializing a streaming application for execution on one or more compute nodes which are adapted to execute one or more stream operators. The method may, during a compiling of code, identify whether a processing condition exists at a first stream operator of a plurality of stream operators. The method may add a grouping condition to a second stream operator of the plurality of stream operators if the processing condition exists. The method may provide for the second stream operator to group tuples for sending to the first stream operator.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Branson, Bradford L. Cobb, John M. Santosuosso
  • Patent number: 9256376
    Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: February 9, 2016
    Assignee: Rambus Inc.
    Inventors: Ely Tsern, Thomas Vogelsang, Craig Hampel, Scott C. Best
  • Patent number: 9257123
    Abstract: In a semiconductor device, a vocoder processing unit requests, after executing a first vocoder process being one of an encoding process and a decoding process and before executing a following second vocoder process being other one of the encoding process and the decoding process, a cache memory to prefetch first program data to be used for the second vocoder process from an external memory.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 9, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Jiro Hara, Yutaka Uchimura
  • Patent number: 9250678
    Abstract: An information processing apparatus includes a nonvolatile memory, a volatile memory, and a process control section. A startup program to be required when starting up the information processing apparatus has previously been stored in the nonvolatile memory. When a command to start up the apparatus is received, it is determined whether or not the startup program is present in the volatile memory. When the startup program is absent, the startup program is loaded from the nonvolatile memory into the volatile memory. Thereafter, when a command to turn off the power of the information processing apparatus is received, supply of power to other components of the information processing apparatus than the volatile memory is stopped while maintaining supply of power to the volatile memory, thereby to shutdown the power of the information processing apparatus.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: February 2, 2016
    Assignee: Nintendo Co., Ltd.
    Inventors: Hiroshi Sasaki, Yutaka Murakami
  • Patent number: 9251553
    Abstract: A pipelined video pre-processor includes a plurality of configurable image-processing modules. The modules may be configured using direct processor control, DMA access, or both. A block-control list, accessible via DMA, facilitates configuration of the modules in a manner similar to direct processor control. Parameters in the modules may be updated on a frame-by-frame basis.
    Type: Grant
    Filed: October 14, 2012
    Date of Patent: February 2, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Satishchandra G. Rao, Boris Lerner, Robert Bushey, Michael Meyer-Pundsack, Benno Kusstatscher, Sreejith Kazhayil, Gokul Muthusamy, Gopal Karanam, Praveen Sanjeev
  • Patent number: 9253722
    Abstract: Systems and techniques for reduced host sleep interruption are described herein. A first packet received via a receive chain may be placed into a buffer. The first packet may be of a first preliminary type. The first packet may be processed from the buffer without communication with the host machine. The first packet may also be of a first secondary type. Processing the first packet may include an operation chosen from the group of dropping the packet and responding to the packet. A second packet received via the receive chain may be placed into the buffer. The second packet may be of a first preliminary type and a second secondary type. The second packet may be communicated from the buffer to the machine. A third packet received via the receive chain may be communicated to the machine. The third packet may be of a second preliminary type.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Sameh Gobriel, Christian Maciocco, Kristoffer D Fleming, Tsung-Yuan C. Tai
  • Patent number: 9251006
    Abstract: A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: February 2, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dhamim Packer Ali, Tom C. Wang, Sha Liu, Sreenivasulu Reddy Chalamcharla
  • Patent number: 9246488
    Abstract: A boundary scan circuit containing a freeze circuit and a transparency circuit that provides a capability to selectively place portions of a system logic in a sleep mode and thereby conserving power. There are two transparency circuit configurations, one that connects to an input pad cell and one that connects to an output pad cell. The circuitry in the transparency circuit is controlled in such a manner as to establish at the output of transparency circuit a known logic state to control leakage current resulting from the circuitry of the various pad cell configurations, which further conserves power during sleep mode.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: January 26, 2016
    Assignee: Global Unichip Corporation
    Inventor: Min-Hsiu Tsai
  • Patent number: 9229667
    Abstract: The present invention is concerning an image forming apparatus that has a first power-saving mode in which a power of loads in the apparatus is caused to transition to a sleep state and a second power-saving mode in which supply of power to the loads in the apparatus is stopped, the apparatus comprising: a low power consumption control unit that keeps the power in the second power-saving mode, wherein, in response to an event to cancel the second power-saving mode, the control unit restarts the supply of power to the loads other than the load of an image forming unit while keeping the supply of power to the loads of the image forming unit stopped.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: January 5, 2016
    Assignee: RICOH COMPANY, LIMITED
    Inventor: Akira Takiguchi
  • Patent number: 9223390
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Patent number: 9223389
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Patent number: 9223503
    Abstract: Methods and apparatus related to generating random numbers utilizing the entropic nature of NAND flash memory medium are described. In one embodiment, a data pattern is written to a portion of a non-volatile memory device and is subsequently read multiple times. Based on the read operations, at least one bit is marked for random number generation based at least partially on comparison of a number of flips by the at least one bit and a threshold value. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Knut S. Grimsrud, Darren D. Lasko, Nathaniel G. Burke
  • Patent number: 9218034
    Abstract: Apparatuses and methods for user-directed motion gesture control are disclosed. According to aspects of the present disclosure, direct user inputs can be used to predictably manipulate power control behavior. In some embodiments, a wearable mobile device may be configured to accept user commands, and be configured to sense multitude of use, use environment, and use contexts. The wearable mobile device may include a memory configured to store a set of reference power control motion gesture sequences, one or more sensors configured to sense a motion gesture sequence, and a controller configured to provide interactive power control of the device using the motion gesture sequence and the set of reference power control motion gesture sequences.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 22, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Khosro Mohammad Rabii
  • Patent number: 9213391
    Abstract: By integrating multiple electronic devices, it is possible to increase the functionality of the devices individually. For example it is possible to improve media playback functionality, create media playlists “on-the-go” and to use a first device power supply to charge the power supply of the second device. By integrating the devices, it is possible to address some of the shortcomings of devices that are decreasing in size with increasing power requirements, while still maintaining the advantages that these devices offer.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: December 15, 2015
    Assignee: Apple Inc.
    Inventor: Aram Lindahl