Abstract: In some aspects, a calibration method includes performing a write/read test for each one of multiple combinations of write/read delay settings, wherein each one of the multiple combinations of write/read delay settings includes one of a plurality of write delay settings of a first delay device and one of a plurality of read delay settings of a second delay device. The method also includes obtaining test results for the write/read tests, determining a pass region based on the test results, determining a center of the pass region, and selecting one of the multiple combinations of write/read settings based on the center of the pass region.

Abstract: An apparatus includes a calculation processing unit configured to perform a calculation in the electronic device, a device manager configured to controls a speed of the calculation processing unit and output load factor information, one or more user-level application programs with a respective load factor limit, configured to request for load factor limit information of the calculation processing unit and calculation of a load with a load factor limit, and a service quality manager configured to receive the load factor limit information and the load with the load factor limit from the user-level application programs with the load factor limit, receive load factor information of the calculation processing unit from the device manager, generate a calculation parameter so that a load factor of the calculation processing unit is within the load factor limit information, and output the load with the load factor limit and the generated calculation parameter.

Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.

Abstract: A technique includes clocking a processor; and in response to the processor providing a signal indicating that the processor is transitioning between a first power state that is associated with a first power consumption and a second power state that is associated with a second power consumption different than the first power consumption, changing a frequency of the clocking.

Abstract: Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.

Abstract: A power control method of an electronic device is provided. The electronic device transmits power change information containing a power control value of an application to another electronic device, and receives and stores power control information about the application transmitted from the another electronic device. If a power level of the electronic device is lower than a predetermined power change level when the application is executed, the electronic device executes the application with power control data of the application in the power control information stored in the electronic device.

Abstract: A device for supplying an electronic circuit with a clock signal having a dock frequency includes a frequency actuator that generates the clock signal in accordance with a frequency setting according to a regulation mechanism. A control module selectively applies to the frequency actuator a first frequency setting or a second frequency setting that is higher than the first setting. An adaptation module modifies the regulation mechanism in accordance with the applied setting.

Abstract: A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain. The first clock frequency alteration generates an associated first alteration in a power consumption from the first synchronous frequency processing domain. The method further includes determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment. The second clock frequency alteration is determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.

Abstract: Hybrid threading in a processor is described. An integrated circuit that implements hybrid threading includes a power control unit (PCU), a first functional hardware unit coupled to the PCU, and a second functional hardware unit coupled to the PCU. The first functional hardware unit and the second functional hardware unit are heterogeneous functional hardware units. The PCU is configured to monitor at least one power attribute of the first and second functional hardware units. The PCU is further configured to calculate an aggregate power value based on the monitored at least one power attribute. Upon determining that the aggregate power value is below a power threshold, the PCU is also configured to calculate a first frequency for the first functional hardware unit and a second frequency for the second functional hardware unit that results in an updated aggregate power value that is closer to the power threshold.

Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.

Abstract: A memory controller includes a clock scaler, a bus component and a level monitor. The clock scaler is configured to receive a first clock signal and configured to generate a second clock signal based on the first clock signal, first and second frequency control signals. A frequency of the second clock signal may increase based on the first frequency control signal and decrease based on the second frequency control signal. The bus component may operate based on the second clock signal and generate a level signal corresponding to a current operating state of the bus component. The level monitor may generate the first and second frequency control signals based on the level signal, a first threshold value, a second threshold value, a first reference time, and a second reference time.

Abstract: A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies.

Abstract: A circuit for use in a switched mode power supply comprising includes an integrated circuit, a transformer, a capacitor, a low voltage circuit and a current limiting resistor. The IC jitters the switching frequency of the switch based on a bias voltage of the integrated circuit. The IC also includes a current source configured to supply current for operation of the switching regulator when insufficient current is available from the bias input pin. The transformer includes primary, secondary and auxiliary windings. The primary winding receives a rectified line voltage and is coupled to the switch. The capacitor is coupled between the bias input pin and ground. The low voltage circuit is coupled to the auxiliary winding, and provides current to the bias input pin. The current limiting resistor limits current produced by the low voltage circuit to less than that required for operation of the IC.

Abstract: A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract: Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. The clock signals may be selected automatically or programmatically. Clock generation circuitry may generate a clock signal that is initially used as the primary clock. The clock generation circuitry may be dynamically reconfigured without interrupting operation of the synchronous digital system, by first selecting another of the available clock signals for use as the primary clock.

Abstract: An apparatus includes multiple media processing modules and a control unit. The media processing modules are configured to exchange digital media signals over a shared bus. The control unit is configured to determine a desired connectivity scheme among the media processing modules, to adaptively define, based on the desired connectivity scheme, connections that transfer the media signals among the media processing modules over the shared bus, and to instruct the media processing modules to establish the connections, by communicating with the media processing modules over a control interface that is independent of the shared bus.

Abstract: An information processing apparatus includes a processor that is capable of switching a performance level to one of a plurality of performance levels with different power consumption, and a storage unit that stores a program for controlling the performance level of the processor. The processor executing the program detects the periodicity of load variation of the information processing apparatus, and changes, according to the periodicity of the load variation, a determination interval for determining whether to switch the performance level of the processor.

Abstract: Technologies are generally provided for a system to enhance security and prevent side channel attacks of targeted functions. Side channel attacks assume that the targeted functions operate at same speed each time, and observe timing data of the targeted functions to glean secure information. According to some examples, an enhanced security system may alter a processing speed of one or more subunits of a processor executing the targeted function(s) to transparently change an instantaneous performance of the processor in an unpredictable manner. The performance time of the targeted function(s) may thereby be randomized. A virtual machine manager (VMM) may identify a security risk for a targeted function, and trigger one or more subunits of the processor to operate at a reduced frequency. After completion of the targeted function, the subunits may be returned to a default performance speed.

Abstract: A bit line and word line tracking circuit is provided that accounts for the power-supply-voltage-dependent delays in a memory having a logic power domain powered by a logic power supply voltage and a memory power domain powered by a memory power supply voltage.

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract: A clock generation system for an integrated circuit (IC) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the IC chip to start and stop internal clocks dynamically on demand to reduce power consumption.

Abstract: Described herein are an apparatus, method, and system for adaptive compensation for reverse temperature dependence in a processor. The apparatus comprises: a first sensor to determine operating temperature of a processor; a second sensor to determine behavior of the processor; and a control unit to determine a frequency of a clock signal for the processor and a power supply level for the processor according to the determined operating temperature and behavior of the processor, wherein the control unit to increase the power supply level from an existing power supply level, and/or reduce frequency of the clock signal from an existing frequency of the clock signal when the operating temperature is in a region of reverse temperature dependence (RTD).

Abstract: An ASMP computing device is provided, which comprises one or more computing components, which themselves comprise a plurality of processing units and one or more memory devices that are communicatively coupled to the one or more computing components, Stored on the memory devices are first and second processing frequency data. The first processing frequency data comprise a synchronization frequency, which comprises a frequency for application to all online processing units when a measured highest load of any online processing unit is greater than a first ramp-up processor load threshold and an operating frequency of the online processing unit is lower than the synchronization frequency. The second processing frequency data comprises a ramp-up frequency, the ramp-up frequency comprising a frequency for application to any online processing unit when a measured processing load of any online processing unit is greater than a second ramp-up processing load threshold.

Abstract: The present invention discloses a method for reducing chip power consumption. The method includes: monitoring real-time load statuses of an input interface, an output interface, and an internal bus of a chip, and collecting load monitoring information; adjusting a working frequency of the chip according to the load monitoring information; and performing rate limiting for an information transmission rate of each channel of the chip according to the current working frequency of the chip. The method and apparatus for reducing chip power consumption according to the present invention solve a problem in the prior art that in a process of chip frequency modulation and power consumption reduction, it is difficult to implement constant rate limiting for a chip channel, thereby providing a feasible solution for reducing chip power consumption while maintaining constant rate limiting for the chip channel.

Abstract: A wireless communication system and method that includes configurable Carrier Aggregation (CA) and/or Multiple-input Multiple-output (MIMO) operational modes. In CA, multiple carriers (i.e., channel bundling) are aggregated and jointly used for transmission to/from a single terminal. Downlink inter-band carrier aggregation increases the downlink data rates by routing two signals, received in different frequency bands, simultaneously to two active receivers in the RF transceiver. MIMO utilizes two additional receivers as diversity paths and the frequency generation can be shared between main and diversity path for each carriers.

Abstract: Certain embodiments of the present disclosure relate to methods for improving a service flow of a mobile device based upon a different level of its available battery power. If the battery power availability is below a predefined threshold, then one or more power-saving techniques can be triggered that increase an air time of the mobile device and provide savings of power consumption at different rates using a different level of clock rate.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: An integrated circuit is provided that includes a plurality of modules comprising at least one clock-gated module and a controller unit, which is arranged to enable and disable provision of a clock signal to the at least one clock-gated module. The at least one clock-gated module includes one or more electronic circuits arranged to be in a first state of an electrical stress condition during a first portion of a period of time and in a second state of less electrical stress than in the first state during a second portion of the period of time. The at least one clock-gated module is further arranged to switch the one or more electronic circuits between the first state and the second state such that a change of a characteristic of at least one of the one or more electronic circuits caused by the electrical stress condition is at least partially reduced.

Abstract: The embodiment of the application provides an apparatus and a method for dynamically adjusting a frequency of central processing unit CPU. The apparatus is used for a computer system which executes a CPU bound application and a memory bound application, and comprises: a ratio acquiring unit for acquiring the ratio of memory access instruction as executing an application task set; a frequency calculating unit connected with the ratio acquiring unit for calculating an adjusted new frequency of CPU in inverse proportional to the ratio of memory access instruction acquired by the ratio acquiring unit; and a frequency adjusting unit connected with the frequency calculating unit for adjusting the frequency of CPU to the new frequency of CPU. With the apparatus and method for adjusting the frequency of CPU according to the embodiment of the invention, the frequency of CPU can be decreased in consideration of the ratio of memory access instruction so as to reduce the power consumption of the computer system.

Abstract: A mechanism is provided for detecting malicious activity in a functional unit of a data processing system. A set of activity values associated with a set of functional units and a set of thermal levels associated with the set of functional units are monitored. For a current activity value associated with the functional unit in the set of functional units, a determination is made as to whether a thermal level associated with the functional unit differs from a verified thermal level beyond a predetermined threshold. Responsive to the thermal level associated with the functional unit differing from the verified thermal level beyond the predetermined threshold, sending an indication of suspected abnormal activity associated with the given functional unit.

Abstract: This disclosure discusses systems, methods, and apparatus for dynamically scaling a clock frequency of an I/O interface to a non-volatile storage device. The scaling can be based on monitoring an idle time on the I/O interface, a priority of one or more applications having read/write requests queued for dispatch to the I/O interface, a load of the queued read/write requests on the I/O interface or a combination of priority and load. Such variables can be compared to thresholds in a frequency governor.

Abstract: Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.

Abstract: A hardware parameter configuring method operating under in an Extensible Firmware Interface-based basic input/output system mode includes reading a currently-existing hardware profile including multiple hardware parameters; reading a preloading hardware profile including multiple hardware parameters; comparing the currently-existing hardware parameters with their corresponding preloading hardware parameters to generate a comparison result; displaying the comparison result through a graphical interface; and loading the preloading hardware parameters to the hardware units to replace the currently-existing hardware parameters when receiving confirmation signal.

Abstract: A system and method are disclosed for private cloud computing and for the development and deployment of cloud applications in the private cloud. The private cloud computing system and method of the present invention include as components at least a cloud controller, a cloud stack, Service Registry, and a cloud application builder.

Abstract: Systems and methods for automatically controlling an electronic device based on whether or not a headset is in a listening position are described. The existing wired stereo headset conductors may be used to provide power to a sensor and hardware subsystem within the headset. In some aspects, a sensor-enabled headset or headphones can sense whether each earbud of the headset is placed in the user's ears and communicate that information to an electronic device.

Abstract: There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.

Abstract: The present disclosure relates to carrying synchronization through Ethernet, Optical Transport Network (OTN), and other asynchronous protocols. In one exemplary embodiment, timing markers or symbols are used in packets to enable a downstream device to recover timing based upon a time differential between markers or symbols. Advantageously, enabling Ethernet, OTN, etc. to carry synchronous information will de-risk switching from SONET/SDH to Ethernet and/or OTN for service providers. The present disclosure also includes frame decomposition scheme of the Ethernet stream. Ethernet packets are broken into fixed bandwidth and excess bandwidth. The fixed bandwidth is subdivided into fixed (negotiated) flits, with each flit corresponding to a specific user or combination of users like a private tunnel. This offers service providers a method to provide deterministic and more secure bandwidth over Ethernet to multiple clients.

Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Abstract: Method and systems for a network device are provided. The method includes receiving configuration data having a primitive sequence comprising a first primitive and a second primitive at a first clock rate at a port of the network device; writing the configuration data into a smoothing module of the port at the first clock rate; reading the configuration data out of the smoothing module at a second clock rate; allowing a primitive to be inserted or deleted in the smoothing module to prevent smoothing module underflows or overflow; regenerating the primitive sequence at the second clock rate; and transmitting the regenerated primitive sequence to the destination port.

Abstract: A frequency calibration method applied to a Universal Serial Bus (USB) device includes: coupling the USB device to a USB host, wherein the USB device at least comprises a programmable oscillator; utilizing the USB device to extract a low frequency periodic signal from the USB host; and calibrating the programmable oscillator of the USB device according to the low frequency periodic signal, to make the programmable oscillator generate an oscillating signal having a predetermined frequency.

Abstract: Timing circuits including supervisor chip(s), capacitors, and latches. The supervisor chip(s) and capacitors cooperate to generate an electrical signal (window signal) having a high logic state when the window is open. The latches are used to determine whether an event of interest occurred while the window was open using the generated window signal and an electrical signal asserted upon occurrence of the event of interest.

Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.

Abstract: Systems and methods detect when a transition from a first power module to a second power module is taking place and generates a lockout pulse when the transition is detected. The lockout pulse initiates the blocking of a predetermined number of gate pulses from reaching the second power module. When the predetermined number of gate pulses are blocked, the systems and methods reset to allow complete gate pulses to reach the second module, and continues to detect when the next transition takes place.

Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.

Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

Abstract: Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. The control circuitry controls the CPU to poll the I/O range for input to the application. The control circuitry also monitors whether or not each poll results in input to the application and adjusts a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected. Methods and a central computer server of an automated exchange system are also provided.

Abstract: Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology, a master device is connected to a plurality of slaves communicating using a bi-frequency encoded bit stream. A host device communicates with the master device using a non-return-to-zero data encoding. Each slave receives data from the master and sends it to the next slave in the ring unaltered unless the master indicates a requirement for a particular data, and transmits placeholder bits with a value of 0 around the ring. A particular slave can “fill-in” the placeholder bits with the information to be sent back to the master by inverting the placeholder bit. Clock synchronization between a receiving device and a transmitting device is improved using a fractional rate multiplier to generate a data sampling clock from a system clock.

Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.