Abstract: The present invention discloses a USB3.0 clock frequency generation device without crystal oscillator, that is, the crystal oscillator used in the USB3.0 device (or apparatus) is removed and replaced with an oscillator circuit module in the present invention, in which a simple circuit module is added to the controller circuit of the USB3.0 device to provide accurate and proper timing signals needed. The oscillator circuit module includes an oscillator block, a frequency divider block, a delta-sigma modulator block, and a preset number block.

Abstract: An embedded multimedia card (eMMC) includes a clock channel receiving a clock from a host, a complementary clock channel receiving a complementary clock from the host, a command/response channel exchanging commands/responses with the host, a plurality of data channels exchanging data between the host and the eMMC, a return clock channel sending a return clock to the host synchronously with data, a complementary return clock channel sending a complementary return clock to the host, and a reference voltage channel that either receives a reference voltage from the host or communicates a reference voltage to the host.

Abstract: A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of packet from an input data stream to initialize a counter, a second detector for detecting a synchronization sequence, a token packet or a handshake packet in the data stream for the counter to carry out clock counting on the clock signal, and a trimming code controller for comparing the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock.

Abstract: An integrated circuit includes a generator. The generator, based on a summation signal, generates a clock signal having a frequency. Multiple devices generate respective requests. Each of the requests requests transfer of data on a bus. Each of the devices is configured to, based on the frequency of the clock signal, transfer the data for the corresponding request on the bus. A summer receives the requests and based on a number of the requests being in an asserted state during a first period of time, generates the summation signal. A first module, based on the summation signal, increases a second period of time that a first request is in an asserted state. The second period of time is increased to include or overlap the first period of time. The summer, as a result of the increase, generates the summation signal further based on the first request.

Abstract: A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a runtime dynamic calibration mechanism and procedure is also provided.

Abstract: A semiconductor device includes: a frequency setting information storage unit that stores sets of frequency information indicating setting of a frequency supplied by an oscillation unit and frequency identification information identifying the frequency information and outputs one of a plurality of pieces of the frequency information to the oscillation unit based on frequency identification information inputted thereinto; a speed setting information storage unit that stores speed identification information indicating a speed of the semiconductor device and frequency identification information corresponding to the speed identification information; a frequency identification information count unit that holds a value of the frequency identification information inputted into the frequency setting information storage unit; and a control unit that causes the frequency identification information count unit to increment or decrement the held value of the frequency identification information to approach a value of the

Abstract: A USB device with a clock calibration function and a method for calibrating reference clocks of a USB device are provided. A USB 2.0 initial calibration is performed on the USB device in order to control an embedded oscillator (EMOSC) of the USB device to output a first reference clock compliance USB 2.0 specification and USB 3.0 specification during the initialization phase. After that, a USB 3.0 on-line calibration is performed on the USB device in order to control the EMOSC of the USB device to calibrate a second reference clock during a super-speed mode of USB 3.0 specification.

Abstract: Example embodiments relate to a security device having two communication interfaces sharing at least one pin, each interface being capable of operating according to either of two predetermined communication protocols. The security device may further include a frequency detector to detect the frequency of a clock signal on the shared pin. Depending on the value of the detected frequency, and to which of a plurality of predetermined frequency ranges the detected frequency pertains, the security device may function according to one of the two predetermined communication protocols, operating at two different frequencies.

Abstract: A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control signal (CS) from a communication interface (CLK, CS, MOSI, MISO), wherein the communication interface (CLK, CS, MOSI, MISO) is designed to transfer information according to a communication protocol. The method further comprises a step of providing the frequency signal in the unit and comparing the frequency signal to a temporal sequence of signal levels of the cycle signal (CLK) received by the communication interface (CLK, CS, MOSI, MISO) in order to obtain a comparison result or controlling a counter by the control signal (CS) and the frequency signal in order to obtain a counter status.

Abstract: Information processing equipment that has one or plurality of partitions further includes: a detection unit configured to detect switching of a clock unit from a first clock unit for counting a time used by an operating system in the partition to a second clock unit; a first setting unit configured to set a time obtained from the first clock unit to a third clock unit for counting a time used in the partition when switching of the clock unit is not detected, and to set a time obtained from the third clock unit to the second clock unit when switching of the clock unit is detected; and a second setting unit configured to set a time that is set to the first clock unit by the operating system to the third clock unit when time setting to the first clock unit performed by the operating system is detected.

Abstract: A dual rail memory operable at a first voltage and a second voltage includes an input circuit, an output circuit and a clock generator circuit coupled with the input circuit. The input circuit is operable to receive at least a first input signal referenced to the first voltage and to generate a second input signal referenced to the second voltage. The output circuit is operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage. The clock generator circuit is operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal.

Abstract: An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined period of time, a hardware comparator to compare a number of write accesses counted by the hardware counter with at least one predetermined threshold value, the hardware comparator further to generate a control signal, the control signal being dependent on a result of a comparison of a number of write accesses counted by the hardware counter with at least one predetermined threshold value performed by the hardware comparator, and a clock frequency setting circuit to set a clock frequency of a processor depending on the control signal.

Abstract: The present invention relates to a method of building virtual clocks that guarantee strictly increasing and high precision timekeeping of programs executed on multiprocessor systems. Specifically, a multiprocessor system is defined as a computing system composed of multiple processing units, where a processing unit is formed of multiple processor cores which operate asynchronously with each other. In addition each processor core has a time counter and operates with one of multiple operating frequencies and can change the operating frequency dynamically. The method builds a high-precision Strictly Increasing Virtual Clock (SIVC) on top of a computer system's time counter which is used as the reference time counter to which a control layer is implemented for capturing the system events that can advance or delay the elapsed time count of system clocks. In this way, SIVC can provide to the computer system a time counter which produces strictly increasing and high-precision values.

Abstract: Integrated circuit devices that operate in different modes. In a low data rate mode, data is transferred between the integrated circuit devices at a low data rate, or no data is transferred at all. In a high data rate mode, data is transferred between integrated circuit devices at a high data rate. A transition mode facilitates the transition from the low data rate mode to the high data rate mode. During the transition mode data is transferred between the integrated circuit devices at an intermediate data rate greater than the low data rate but lower than the high data rate. Also during the transition mode, parameters affecting the transmission of data between the integrated circuit devices are calibrated at the high data rate.

Abstract: A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.

Abstract: Methods and apparatus relating to dynamic intelligent allocation and utilization of package maximum operating current budget are described. In one embodiment, at least one computational element may be caused to operate at an increased frequency in response to a determination that an opportunity exists to reduce a maximum dynamic capacitance associated with the processor. The determination may be based on an idle status of one or more subsystems of the processor. Other embodiments are also disclosed and claimed.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.

Abstract: To provide a clock signal generating device that changes the frequency of a predetermined clock signal in a short time and prevents or mitigates instability in the operation of the supply destinations of the clock signal when the frequency of the clock signal is changing. The clock signal generating device is provided with a second control unit that, when the target frequency changes, successively changes the voltage impressed on the clock signal generating unit with a preset change value and a preset interval in a preset time in place of the first control unit, causing the frequency of the clock signal newly generated by the clock signal generating unit to approach the target frequency.

Abstract: A microcontroller for use in a control device for an internal combustion engine includes: an analysis access via which internal data in the microcontroller can be accessed from outside the microcontroller; a clock generator which generates clock timing for data communication of the microcontroller with other units. The microcontroller is configured to change over from a first clock to a second clock when there is an access to the microcontroller via the analysis access.

Abstract: A clock frequency of a clock signal is calculated, with the clock signal being received by an IC card from a terminal or an internal clock within the IC card. A first time-stamp is received from the terminal, and a first value of the timer is set. The timer of the IC card is started when the first time-stamp is received. A second time-stamp is received, and a second value of the timer is read when the second time-stamp is received. The frequency is calculated by comparing a difference between the second and the first timer values, and a difference between the second and the first time stamps.

Abstract: Methods and apparatuses for minimizing co-channel interference in communications systems are disclosed. A method in accordance with the present invention comprises shifting a characteristic of the first signal with respect to a like characteristic of the second signal to mitigate co-channel interference, and transmitting the first signal and the second signal over different channels of the communication system.

Abstract: Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.

Abstract: A method and apparatus are provided for docking data processing modules, which require differing average clock frequencies, and for transferring data between the modules. This comprises a means for providing a common dock signal to modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the docking frequency required by each module. Clock pulses are applied to modules between which data is to be transferred at times consistent with the data transfer.

Abstract: In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a single clock frequency and a clock signal quadrature output frequency and a clock signal in-phase output with the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency being a fraction of the frequency of the single clock frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output, the final output of the plurality of dividers being synchronized to the reference frequency.

Abstract: A circuit for delaying an input signal includes first and second delay units. The input signal is switched to the first delay unit which is configured to delay the input signal by k cycles of a first clock signal so as to generate a value xt—k and transfer the input signal to the second delay unit. The second delay unit includes a converter and a second shift register. The converter is connected to the second shift register by n leads. The value xt—k and a value xt—k?1 are present at the converter, where xt—k?1 is the input signal delayed by k?1 cycles of the first clock signal, The converter is configured such that the value xt—k?1 is present on leads 1 to m and the value xt—k is present on leads m+1 to n. The second shift register is configured to successively output values present on leads 1 to n.

Abstract: Scalable, common reference-clocking architecture and method for blade and rack servers. A common reference clock source is configured to provide synchronized clock input signals to a plurality of blades in a blade server or servers in a rack server. The reference clock signals are then used for clock operations related to serial interconnect links between blades and/or servers, such as QuickPath Interconnect (QPI) links or PCIe links. The serial interconnect links may be routed via electrical or optical cables between blades or servers. The common reference clock input and inter-blade or inter-server interconnect scheme is scalable, such that the plurality of blades or servers can be linked together in communication. Moreover, when QPI links are used, coherent memory transactions across blades or servers are provided, enabling fine grained parallelism to be used for parallel processing applications.

Abstract: A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.

Abstract: A control apparatus controls a signal processing unit. The signal processing unit is mounted within a case and includes a waveform shaping unit which performs a waveform shaping process on an inputted signal. The control apparatus includes: an obtaining device which obtains (i) mounting information indicating a mounting state of the signal processing unit, (ii) temperature information indicating a temperature of the signal processing unit, and (iii) processing unit characteristic information indicating characteristics unique to the signal processing unit; and an adjusting device which adjusts waveform shaping characteristics of the waveform shaping unit, on the basis of the mounting information, the temperature information and the processing unit characteristic information.

Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.

Abstract: A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.

Abstract: Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a first clock having a first clock frequency (f1) with a first clock frequency tolerance (?f1), and a second timing engine that samples bits received by the receiver with a second clock having a second clock frequency (f2) with a second clock frequency tolerance (?f2). The second clock frequency is less than the first clock frequency. The network receiver may also include a third timing engine that samples bits received by the receiver with a third clock having a third clock frequency (f3) with a third clock frequency tolerance (?f3). The third clock frequency may be greater than the first clock frequency.

Abstract: In accordance with some embodiments, a method for high frequency clock distribution in a VLSI system includes splitting an original master clock signal into one or more pairs of lower-frequency sub-clocks for a destination in the VLSI system, distributing each lower-frequency sub-clock of the one or more pairs of lower-frequency sub-clocks to a corresponding channel coupled to the destination, and reconstructing a reference master clock signal at the destination from the one or more pairs of lower-frequency sub-clocks, wherein the reconstructed reference master clock signal replicates the original master clock signal.

Abstract: An apparatus for clock calibration on a remote device includes a first oscillator, a second oscillator, and a clock calibration module. The first oscillator generates a first clock signal during an active communication mode to facilitate communications between the remote and host devices. The first oscillator is inactive during a sniff mode. The second oscillator generates a second clock signal during both the active communication and sniff modes. The clock calibration module generates an estimated count for the first clock signal approximately at a transition from the sniff mode to the active communication mode. The estimated count is based on a clock ratio of a baseline count of the first clock signal relative to a baseline count of the second clock signal. The clock calibration module also calculates a difference between the estimated count and an actual count from the host device to determine whether to update the clock ratio.

Abstract: A processing device includes: a clock generating circuit that outputs a clock; an instruction executing circuit that is capable of a state change between an instruction executing state where an instruction is executed and an instruction stop state where an instruction is stopped; a first circuit that inhibits the supply of the clock to an internal circuit when a first clock inhibition signal is input; a second circuit that inhibits the supply of the clock to an internal circuit when a second clock inhibition signal is input; and a control circuit, and the control circuit outputs the second clock inhibition signal to the second circuit after outputting the first clock inhibition signal to the first circuit, when the instruction executing circuit changes from the instruction executing state to the instruction stop state.

Abstract: A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus.

Abstract: Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In one exemplary embodiment a clock recovery apparatus for a plurality of data channels may include a plurality of channel blocks, where each channel block may include a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a global signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal. The apparatus may also include a global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal.

Abstract: A method for reducing electromagnetic emissions in an electronic device having a multiple micro-controllers includes identifying the number of micro-controllers installed in the electronic device. An operating frequency range of the electronic device is determined based on the operating frequency range of each micro-controller. A frequency spacing for each micro-controller within the operating frequency range of the electronic device is then calculated, and an operating frequency is assigned to each micro-controller. The operating frequency of each micro-controller is separated from the operating frequency of each other micro-controller by at least the frequency spacing. Then, the operating frequency of each micro-controller is set at the assigned operating frequency.

Abstract: Embodiments of the disclosure generally set forth techniques for handling communication between processor cores. Some example multi-core processors include a first set of processor cores in a first region of the multi-core processor configured to dynamically receive a first supply voltage and a first clock signal, a second set of processor cores in a second region of the multi-core processor configured to dynamically receive a second supply voltage and a second clock signal, and an interface block coupled to the first set of processor cores and the second set of processor cores, wherein the interface block is configured to facilitate communications between the first set of processor cores and the second set of processor cores.

Abstract: A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

Abstract: In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the core clock signal based on the determined operating frequency. Other embodiments are described and claimed.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: One embodiment is a clocking system for a computing environment. The system comprises a first set of processes executing in a first computing environment; a first local clock mechanism associated with the first set of processes; and a first communications channel for connecting the first local clock mechanism with the first set of processes. The first local clock mechanism stores clock rates of the first set of processes, wherein each clock rate is specified by function and source and destination combination, the first local clock mechanism further coordinating the clock speeds of the first set of processes as necessary.

Abstract: Objects of the invention are to provide a clock generation circuit and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.

Abstract: A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a synchronization/desynchronization controller configured to synchronize or desynchronize the clock of the processor with respect to the clock of the submodule, depending on the result of the monitoring. Specifically, the processor clock is synchronized to the submodule clock when the frequency of access to the submodule by the processor is high, and the processor clock is desynchronized with respect to the submodule clock when the access frequency is low.

Abstract: A method is provided for synchronizing time in an unsynchronized vehicle controller area network system. A master control unit receives a global time from a time synchronization source. The master control unit estimates a respective time delay in transmitting messages by electronic control units on each controller area network bus. The time delay is a difference between a time when a message is generated by a respective electronic control unit for transmission on a respective controller area network bus and a time when the message is transmitted on the respective controller area network bus. The global time is adjusted for each respective controller area network bus based on the estimated time delays associated with each respective controller area network bus. Global time messages from the master control unit are transmitted to each electronic control unit that include the adjusted global times for an associated controller area network bus.

Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.