Abstract: A method for operating a device (such as a printer) having a first interface (such as USB interface) connectable to a first computer and a second interface (such as an Ethernet interface) connectable to a second computer. A phase lock loop (PLL) circuit is obtained which is driven by a clock source, which is adapted for switching between operating at the first and second clock frequencies, and which is operatively connected to the first and second interfaces to provide a clock signal to the first and second interfaces. The PLL circuit is operated at the first clock frequency when the first interface is active and is operated at the second clock frequency when the second interface is active. A device includes the first and second interfaces, the PLL circuit, and the clock source.

Abstract: A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.

Abstract: A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.

Abstract: Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells each having a multiplexer and a counter.

Abstract: A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an operation clock and includes a first DLL circuit for generating a first internal clock from an external clock in a first frequency band, a second DLL circuit for generating a second internal clock from an external clock in a second frequency band different from the first frequency band, and a selector for selecting any of the first internal clock generated by the first DLL circuit and the second internal clock generated by the second DLL circuit, and outputting the selected clock as the operation clock of the memory module.

Abstract: A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal when the lengthy operation is activated. The clock control circuit receives the clock signal and outputs a gated clock signal only when the first device is not producing the control signal. The processor unit runs off of the gated clock signal. The first device may be a memory, and the lengthy operation may be correction of a soft error in memory. According to a second aspect, the first device requires a longer clock cycle rather than more clock cycles. The clock can be gated to effectively double the period when the lengthy operation is activated.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.

Abstract: A programmable synchronizer system for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock signal and the bus clock domain is operable with a bus clock signal, the core and bus clock signals having a ratio of N core clock cycles to M bus clock cycles, where N/M?1. A first synchronizer is provided for synchronizing data transfer from a core clock domain logic block to a bus clock domain logic block. A second synchronizer is operable to synchronize data transfer from the bus clock domain logic block to the core clock domain logic block. Control means are included for controlling the first and second synchronizers, the control means operating responsive at least in part to configuration means that is configurable based on skew tolerance and latency parameters.

Abstract: The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.

Abstract: A system and method for coordinating synchronizer controllers disposed in different clock domains, e.g., a core clock domain and a bus clock domain, wherein a clock synchronizer arrangement is employed for effectuating data transfer across a clock boundary therebetween. A bus clock synchronizer controller operable in the bus clock domain includes circuitry for generating a set of inter-controller clock relationship control signals, which are provided to a core clock synchronizer controller. Responsive to the inter-controller clock relationship control signals, circuitry in the core clock synchronizer controller is operable to synchronize the core clock signal's cycle and sequence information relative to the bus clock signal.

Abstract: An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.

Abstract: A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one or more divide modes, wherein the divide modes provide a clock frequency that is a fraction of the normal clock frequency by a divisor value that is specified in a user-accessible divider register. Lower divisor values (e.g., 2, 4, 8, etc.) are preferably used for performance tuning, while large divisor values (e.g., 1024, 2048, and 4096) are preferably used for power saving.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Abstract: In one form of the invention, a method for generating a local clock signal responsive to signals on a Universal Serial Bus (“USB”) includes generating a frequency-bearing clock signal by a free running oscillator on an integrated circuitry chip of a device coupled to the USB. The oscillator runs at a frequency that is substantially stable but initially known with substantial inaccuracy. A single ended bit-serial signal is extracted from received signals sent by a USB host or hub and timing signals are responsively asserted. A bit pattern is detected in the single ended bit-serial signal and intervals are measured during which the timing signals are asserted. The period P of the local clock signal is adjusted responsive to one of the measured intervals. In one variant, the initial inaccuracy is at least partly because the oscillator consists solely of circuitry on the chip.

Abstract: A circuit and method for the input of a start signal, a controller being transferred from a first state into a second state as a function of the start signal, the energy consumption of the controller in the second state being greater than in the first state, the circuit having a clocked energy source which emits a timed energy signal, and the start signal is formed as a function of the energy signal.

Abstract: A clock distribution and control system (10) includes one counter (30) in a clock generation domain and another counter (40) in a phase-delayed clock domain. The phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.

Abstract: A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is halted. The standby mode is exited by input of an interrupt. The microcontroller also has a control circuit that, by storing the next few program instructions internally before placing the memory in standby, or by delaying the interrupt signal, provides extra time for memory operation to stabilize on exit from the standby mode. Malfunctions on recovery from standby are thereby prevented, and the microcontroller can conserve power by placing the memory in a deep standby mode with a comparatively long recovery time.

Abstract: The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.

Abstract: An oscillation circuit generates a reference clock signal for a clock signal supplied to each section of a data transfer control device. In a clock output control circuit, a clock command is decoded by a clock command decoder and oscillation of the oscillation circuit is controlled. The data transfer control device including a clock control circuit transfers data as a host or a peripheral in a state being set to either a self-powered first device or a second device which can operate by using a power supply on a bus. The oscillation operation of the oscillation circuit is suspended in an idle state of the second device.

Abstract: One embodiment of the present invention provides a system that provides skew compensation for communications across a source-synchronous self-timed network. During each clock period, the system allows multiple synchronous transmitters to each transmit one data element and to assert one acknowledgement on a transmit clock line into the self-timed network. In doing so, the multiple synchronous transmitters do not wait for requests from the self-timed network before transmitting a subsequent data element. Similarly, during each clock period, the system allows multiple synchronous receivers to accept one data element from and to assert one request on a receive clock line coupled into the self-timed network. In doing so, the multiple synchronous receivers do not wait for acknowledgments from the self-timed network before receiving a subsequent data element. The self-timed network is configured to tolerate bounded skew between the multiple synchronous transmitters and multiple synchronous receivers.

Abstract: To provide a semiconductor circuit device including a synchronous frequency divider which counts input clock signals and outputs a counted value, a selector circuit which receives signals of bits of the counted value output from the synchronous frequency divider and outputs a carry look-ahead signal of predetermined bits as an operation-processing effective-state signal in accordance with a selector signal, and an integrated circuit portion which uses a clock signal input to the synchronous frequency divider as a source clock and whose operating frequency is switched in accordance with the operation-processing effective-state signal.

Abstract: A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message.

Abstract: In a clock generating circuit, clocks generated therein are distributed by a clock distribution control circuit for every circuit block. In a clock output control circuit, a clock command is decoded by a clock command decoder and output of the clocks is controlled for every circuit block. A data transfer control device having a clock control circuit functions as a first device or a second device to transfer data as a host or a peripheral. When the data transfer control device function as a second device and in an idle state, it controls clock output to a state controller which controls switching between a host function and a peripheral function.

Abstract: In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number of chips requiring power, minimum refresh rates reduce the power needed to maintain information, and a threshold for determining when to power down a battery powered device are used to maximize battery life.

Abstract: A processor, comprising a monitor for, depending on the respective embodiment, measuring the relative amount of idle time, activity time, or idle time and activity time within the processor, results of the measuring being used by the processor for controlling a clock speed of the processor. Yet other embodiments disclose, depending upon the respective embodiment, a processor, comprising a monitor for measuring the relative amount of idle time, activity time or idle time and activity time within the processor, results of the measuring being used by the processor to control power dissipation associated with the processor.

Abstract: A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one processor cycle and with one power mode instruction employing clock transition logic within the processor to initiate a switch to the clock source configuration specified by a literal, such as a 3-bit literal. Operand may be written the register of clock transition logic to define an exit state for a sleep mode.

Abstract: A control device and a method for controlling and/or regulating the operational sequences in a motor vehicle, and a method for starting such a control device, which provide a program in a storage medium of the control device that is able to be executed independently of the frequency of the CPU, which allows the pulse frequency of the CPU to be checked and employs measures for reprogramming the program to be initiated. During starting or operation of the control device, the frequency of the CPU is checked first or the frequency of the CPU is compared to the frequency expected in the program. If necessary, measures for reprogramming the program are subsequently initiated.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU signals and generates CPU performance data based on the critical CPU signals. An adaptive CPU throttler (THR) module uses the CPU performance data, along with a CPU percent idle value fed back from the operating system, to generate a CPU throttle control signal during predefined run-time segments of the CPU run time. The CPU throttle control signal links back to the CPU and adaptively adjusts CPU throttling and, therefore, power usage of the CPU during each of the run-time segments.

Abstract: To provide a microcontroller having a function for stopping supply of a clock signal to a slave block and a function for properly stopping the access to a slave block to which supply of a clock signal is stopped. A microcontroller of the present invention has a master block 101 for controlling the whole microcontroller, slave blocks 102 and 103 to be controlled by the master block 101, clock-signal control means 106 and 107 for controlling supply/stop of a clock signal in response to a clock control signal output from the master block 101, and a default slave block 104 for outputting a response signal RESP instead of a slave block to which supply of a clock signal is stopped.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.

Abstract: The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one embodiment, the bus master is provided in the form of an integrated circuit comprising clock control logic that is configured to disable a clock signal that is otherwise delivered to functional circuitry contained within the integrated circuit during a period of time between the request for mastership of a bus and the grant of that request.

Abstract: This data processor can satisfy both requests of a fast transition from a low power consumption state to an operating state and low power consumption, and a data processor has a program running state, a standby mode, a light standby mode, and a sleep mode. In the sleep mode, the supply of a synchronizing clock signal to a central processing unit (CPU) is stopped and the synchronizing clock signal is supplied to other circuit modules. In the standby mode, the frequency multiplication and frequency operation of a clock pulse generator are suspended and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the frequency multiplication and frequency division operation of the clock pulse generator are enabled and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped.

Abstract: A watchdog timer circuit modified to operate during periods of microcomputer shut-down or sleeping, as for energy conservation purposes, controlled by an independent external rectangular-wave signal for inhibiting watchdog timer reset signal generation for the microcomputer during such shut-down periods and until a wake-up signal is generated at the end of such microcomputer sleeping, whereupon the watchdog circuit will generate a reset signal in the absence of proper microcomputer operation.

Abstract: A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

Abstract: A data processing system includes a general-purpose data processing unit (PU) including an instruction issuing unit that fetches and decodes an instruction in a program and issues the instruction and an execution unit that executes general-purpose processing according to a general-purpose instruction in the program; a special-purpose data processing unit (VU), including a data path unit for special-purpose data processing, that executes special-purpose data processing according to a special-purpose instruction in the program; and a first clock supply unit for stopping, based on a wait signal that is issued by the VU and shows that the PU is waiting for processing of the VU, a first clock signal for a part of the PU.

Abstract: A computer system having a logic device capable of accepting various chipset controllers and interfacing them with a personal computer processor, the logic device capable of placing the processor into a deep sleep state so that the processor can perform power state transitions. The power state transitions place the processor into a battery optimizing mode or a performance optimizing mode. The logic device allows chipset controllers that may or may not have the capability to perform power state transitions to interface with the processor. The logic device either passes power transition signals through to the processor from the chipset controller or performs the power state transitions. Various chipset and chipset controllers may therefore interface with a processor and are able to switch between battery optimized and performance optimized modes.

Abstract: A method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency. A first clock signal is generated with a first frequency which is then used to generate a second clock signal with a second frequency. The second frequency is generated by dropping selected pulses of the first clock signal. Particular patterns of bits are stored in a storage element. Bits are then selected and conveyed from the storage element at a frequency determined by the first clock signal. The conveyed bits are used to construct the second clock signal. By selecting the particular pattern of bits selected and conveyed, the frequency of the second clock signal may be determined. Further, by changing the patterns of bits within the registers at selected times, the frequency of the second clock signal may be made to change in a relatively linear manner.

Abstract: A microcomputer comprises an intermittent operation control section for intermittently operating a CPU. Moreover, the microcomputer comprises a timer block, a level detecting circuit or a timer interlocking control section as the circuits for assisting operation of the CPU. The CPU realizes a timer function with the timer block. The CPU can start the process in response to a level of an external signal with the level detecting circuit. The CPU can start operation with the timer interlocking control section after an external apparatus is driven. With the structure explained above, power consumption of the microcomputer is reduced.

Abstract: A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating responsive to a local clock signal. A system clock is coupled to the circuit blocks for providing a system clock signal that functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a shutdown circuit that selectively prevents the system clock signal from functioning as the local clock signal in those circuit blocks that receive the shutdown signal, but the shutdown circuit only operates after both the signal to shutdown is received from the power control manager and after the circuit block has, in fact, shutdown.

Abstract: A signal processing apparatus includes a digital signal processor (DSP) including an internal memory part storing a program to carry out, an external memory part storing all programs to carry out in the DSP, a clock signal generating part for generating and outputting a clock signal to the DSP, and a clock signal control part for controlling to output said clock signal to the DSP. More particularly, the clock signal control part forwards the programs outputted from the external memory part to the internal memory after the clock signal generating part stops outputting the clock signal to the DSP.

Abstract: A method of producing a time delay is provided. The method is performed with an information processor having a first timer and a second timer. The information processor is capable of maintaining a sleep mode. The method involves using the second timer to measure the timeout for the first timer. The method also includes repetitively causing the information processor to enter the sleep mode so as to be awakened by the first timer reaching timeout to substantially produce a time delay while the second timer is disabled.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a first clock receiver, one or more clock traces coupled to the clock generator, and clock generator coupled to the one or more clock traces. The clock generator gates clock signals to the first clock receiver in response to detecting that the clock traces have been disconnected from electrical ground.

Abstract: A method and apparatus are disclosed for conditionally enabling/disabling PCI power management in a computer-based system employing a central resource and an operating system. Non-CLKRUN# compatible PCI devices in the system are identified and whether or not the non-CLKRUN# compatible PCI devices are enabled is determined. The CLKRUN# support capability of the central resource, if available, is enabled or disabled based on, at least in part, the established status of the non-CLKRUN# compatible PCI devices. If enabled, PCI power management is provided by the CLKRUN# support capability according to the PCI CLKRUN# protocol for all CLKRUN# compatible PCI devices present in the computer-based system.

Abstract: An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.

Abstract: This specification discloses a method and device for playing multimedia files in a semi-power on state of a computer. A program is provided in the BIOS so that POST (Power On Self Test) is not performed after the power is turned on. The program directly initializes multimedia chips or chipsets. A micro controller is provided as the interface for the CPU to control to execute the commands given by its user. Finally, the processed result is presented by a player. Through the simple method, the user can make the computer play multimedia files directly, achieving the goal of a computer with the home electronics functions.

Abstract: A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal.