Abstract: A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU signals and generates CPU performance data based on the critical CPU signals. An adaptive CPU throttler (THR) module uses the CPU performance data, along with a CPU percent idle value fed back from the operating system, to generate a CPU throttle control signal during predefined run-time segments of the CPU run time. The CPU throttle control signal links back to the CPU and adaptively adjusts CPU throttling and, therefore, power usage of the CPU during each of the run-time segments.

Abstract: A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.

Abstract: A clock diagnostics module, such as a state machine, integrated into an integrated clock controller monitors clock signals associated with the integrated clock controller and reports the status of the clock signals through a management bus, such as an SMBus. For instance, a counter integrated into the integrated clock controller counts clock signal cycles that occur in a management bus cycle and compares the clock signal with an expected value to determine the accuracy of the clock. A power on reset allows the management bus to read the clock diagnostics module in the event of clock controller failure.

Abstract: A technique for providing service processor (SP) access to registers, e.g., control and status registers (CSRs), located within hardware modules of a computer system, ensures access to the CSRs within a predetermine time period. The computer system includes a host module (HM) and a plurality of client modules (CMs). The CMs each include one or more associated registers, and each of the CMs is separately addressable. At least one of the CMs operates at a different clock frequency than the remaining CMs and includes a clock synchronizer, which provides a clock signal to facilitate reading of or writing to the associated registers of the CM by the HM.

Abstract: There are provided a system on chip (SoC) with a low power mode and a method of driving the SoC, the SoC including: a power part supplying a main clock signal and controlling analog and digital power supply at a normal mode and supplying a sub clock signal and turning analog power off at a low power mode; a radio frequency (RF) part generating the main clock signal at the normal mode and stopping operation at the low power mode, under the control of the power part; and a control part operating according to the main clock signal at the normal mode and operating according to the sub clock signal, under to the control of the power part.

Abstract: In an electronic device having a plurality of processing elements PEs that operate in synch with a clock signal, each of the plurality of PEs generates its own operating clock signal in accordance with a clock enable signal that is input together with data from an outside or from a PE of a preceding stage, processes the input data in response to this operating clock signal, outputs this processed data to a PE of a succeeding stage and outputs the clock enable signal to the PE of the succeeding stage, and halts generation of its own operating clock signal when output of the processed data is completed following completion of processing of the data.

Abstract: The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by the transmitter equipment A is used by the receiver equipment B to sample the transmitted data. An alternation is effected at the receiver equipment B between a phase of operation during which the clock signal HA accompanying the data is replaced by a local clock signal HLS of the same frequency and a phase of operation during which the local clock signal is periodically re-synchronized with the accompanying clock signal. Means to implement the method are also disclosed.

Abstract: A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection. For each of the plurality of memories, a first variable delay unit delays, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function and a second variable delay unit delays, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time.

Abstract: A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third output driver to a third signal path. Rising and falling edge transitions of the timing information indicate times at which subsequent symbols of the write data are valid on the signal path. The timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach the destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path.

Abstract: In a method, system and apparatus for measuring an idle value of a Central Processing Unit (CPU) in an embedded system, the CPU increments a hardware counter in accordance with clock signals. The CPU also increments an idle counter during a predetermined period of time in accordance with the clock signals while an idle task is running. The CPU calculates the idle value as a ratio of total increments of the idle counter to total increments of the hardware counter after the predetermined period of time has expired.

Abstract: A computer system includes a device which operates depending on a clock frequency; a battery unit which comprises a plurality of battery cells and supplies power to the device; a temperature sensor which senses temperature of the battery cells; and a controller which decreases the clock frequency if the sensed temperature is beyond a first preset critical point.

Abstract: Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A plurality of interfaces, referred to as switches, together with the agents of the cells, connects the cells together. A clock source provides a clock to a switch, which replicates the clock and provides the replicated clocks to its ports. Each port of the switch, receiving a replicated clock, encodes this replicated clock and sends it over a link to each agent of a cell. Each agent of the cells, receiving an encoded clock, decodes this encoded clock, resulting in a decoded, or an extracted, clock. The agent then replicates the extracted clock and provides the replicates of the extracted clock to a plurality of CPUs of the cell. As a result, CPUs in all cells of the system receive clocks that all are synchronized to the clock provided by the clock source.

Abstract: The image sensing device interface unit attached to an image sensing device has dedicated means to detect a complete missing line and to perform clock gating of circuits for power management self-optimization. For each image frame, the time interval between start of line 1 and start of line 2 is computed and stored in a first register. The time interval between any other pair of two consecutive lines is also computed and stored in a second register. The stored values are compared, and if the value in the second register is greater than in the first register, a complete missing line has been detected and the gated clock used in said circuits is switched off for power saving. The interface unit can adapt to any type of sensor and does not require the help of any processor to perform the power saving function.

Abstract: Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.

Abstract: A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.

Abstract: An IC Card may include electronic components to receive a power supply and a main clock signal by a reader device. The power supply may be provided to a subset of the electronic components during a main clock stop status wherein the main clock signal is suspended for avoiding a maximum power consumption threshold. The IC Card may also include a low precision clock included in the subset of electronic components for measuring time in the main clock stop status.

Abstract: Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be transferred are shifted in the first clock domain. The shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain. A stream of sampled bits may be output in the second clock domain. Additional embodiments are described and claimed.

Abstract: A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.

Abstract: The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by the transmitter equipment A is used by the receiver equipment B to sample the transmitted data. An alternation is effected at the receiver equipment B between a phase of operation during which the clock signal HA accompanying the data is replaced by a local clock signal HLS of the same frequency and a phase of operation during which the local clock signal is periodically re-synchronized with the accompanying clock signal. Means to implement the method are also disclosed.

Abstract: An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell buffer used for compensating for distortion of clock signals inputted to the macrocell. The macrocell buffer is disabled if the clock signals are not being used by the corresponding macrocell, thereby preventing unnecessary toggling and power consumption.

Abstract: The present invention relates to an electronic device comprising a first CPU, a second CPU, a first delay stage and a second delay stage for delaying data propagating on a bus, a CPU compare unit, and wherein the first delay stage is coupled to an output of the first CPU and a first input of the CPU compare unit, an input of the first CPU is coupled to a system input bus, the second delay stage is coupled to the system input bus and to an input of the second CPU, an output of the second CPU (CPU2) is coupled to the CPU compare unit, and wherein the first CPU and the second CPU are adapted to execute the same program code and the CPU compare unit is adapted to compare an output signal of the first delay stage, which is a delayed output signal of the first CPU, with an output signal of the second CPU.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.

Abstract: A method and apparatus for accessing a memory device. The method includes providing control signals for an access command to the memory device via an asynchronous interface and transmitting data for the access command to the memory device. The method also includes encoding, into the transmitted data, a clock signal. The encoded clock signal in the transmitted data is used by the memory device for receiving the data transmission.

Abstract: Embodiments of RFID tag circuits and methods are described, which include a chip having a clock circuit operable to generate a clock signal having different frequencies, and one or more components operable to work at the different frequencies. In addition to a regular frequency, at least one higher frequency is possible, which is enabled in situations where a reader is known to be close to the chip. The proximity ensures that the chip generates reliably more power, which enables its operation at the higher speed.

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a memory; (b) a processor adapted to issue a functional command to the memory; (c) a translation chip; (d) a first link adapted to couple the processor to the translation chip; and (e) a second link adapted to couple the translation chip to the memory; (2) calibrating the first link using the translation chip; and (3) while calibrating the first link, calibrating the second link using the translation chip. Numerous other aspects are provided.

Abstract: An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).

Abstract: A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Abstract: A delay time of a reference clock CLK is changed to generate a memory control clock CLKd, a data value output from a write data generating section is written in a memory based on the memory control clock CLKd, while successively changing the delay time of the memory control clock CLKd with respect to the reference clock CLK, the data value written in the memory is read, and the delay time suitable for access to the memory is selected from the delay time of the memory control clock CLKd with respect to the reference clock CLK based on a comparison result of the data values.

Abstract: A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.

Abstract: To enable measurement of a suspension position and a suspension period of the reference clock of a microcomputer to be inspected, based on the information stored into a clock information register section, by acquiring output data output from the microcomputer; preserving the acquired output data into a data bank section by use of the reference clock being output from the microcomputer together with the output data; discriminating the suspension of the reference clock by a clock operation discrimination section at sampling intervals of the output data; and writing and preserving the discrimination result into the clock information register section by a register control section.

Abstract: A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the daisy chain bus structure as well as signal transmission time to each one of a plurality of client devices connected to a host device by the daisy chain bus structure may be readily determined.

Abstract: A method and apparatus for transparently replacing a processor, that receives interrupts in a partitioned computing device, with a replacement processor, is disclosed. The method comprises directing the interrupts to an unchangeable identifier mapped to the processor's identifier and replacing the processor with the replacement processor. An intermediary, such as an I/O APIC, is used for storing the unchangeable identifier. The mapping may use logical mode delivery, physical mode delivery, or interrupt mapping.

Abstract: An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

Abstract: An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device (1) comprising a D flip-flop (F0) for receiving a pulse of a clock signal (CK) to introduce data thereinto and output said introduced data and a shift register (2), comprising the D flip-flops (F1 to F7) for introducing the data thereinto in accordance with the pulse to output the introduced data, for processing the outputted data from the D flip-flop (F0), wherein the circuit device (1) comprises a control circuit (3) for controlling whether the D flip-flops (F1 to F7) are supplied with the pulse of the clock signal (CK) on the basis of outputted data from the D flip-flop (F0) in accordance with the pulse of the clock signal (CK) and data to be introduced into the D flip-flop (F0) in accordance with the next pulse.

Abstract: A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.

Abstract: A method and device for playing compressed multimedia files in a semi-power on state of a computer is provided. A program is provided in the BIOS so that POST (Power On Self Test) is not performed after the power is turned on. The program directly initializes multimedia chips or chipsets. A micro controller is provided as the interface for the CPU to control to execute the commands given by its user. Finally, the processed result is presented by a player. Through the simple method, the user can make the computer play compressed multimedia files directly, achieving the goal of a computer with the home electronics functions.

Abstract: An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

Abstract: The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and masking an output signal of said clock multiplier during settling time of said clock multiplier.

Abstract: The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

Abstract: A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. A sync circuit portion, responsive to a valid edge signal indicative of coincident edges between the first and second clock signals, is operable to generate based upon the ratio a start sync signal substantially centered around the coincident edges. A first sync generator, responsive to the start sync signal, is operable to generate synchronization pulses in the first clock domain. A second sync generator, responsive to the start sync signal, is operable to generate synchronization pulses in the second clock domain.

Abstract: An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on an elapsed cycle number obtained by counting, control timing of various interfaces relating to the CPU is adjusted and an interruption generating interval in which interruption is generated regularly by the CPU so that adjustment of control timing of various interfaces and setting of a timer interruption interval during the OS operation in accordance with a frequency of the clock source without performing OS modification such as rebuilding and the like.

Abstract: The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.

Abstract: A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to be a second level and to output the clock as a composite clock for clock switching, for a specified period including one of a leading edge and a trailing edge of the clock as well as additional time before and after the edge, when the signal becomes active while the clock is at a first level; a switching demand signal generation circuit that receives the clock and the signal, and outputs a clock switching demand signal; a clock selection signal generation circuit that changes a level of a first clock selection signal when the signal becomes active; and a first selector that selects one of the clock and the clock, according to the level of the signal, and outputs the selected clock.

Abstract: A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.

Abstract: A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable register. A reset circuit supplies a signal to a reset input of the digital module for a normal mode if the bit indicates the power-up state and a reset mode if the bit indicates a power-down state. Return to normal mode is delayed a predetermined time after the said bit of indicates the power-up state to ensure clean power up. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the corresponding bit indicates the power-down state.

Abstract: A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock signal transmitted to the remote member. One input of the main variable delay line receives the reference clock signal.

Abstract: A clock filter for use in filtering an external clock signal to create an internal clock signal for use by an electronic device is provided. The clock filter receives the external clock signal and sets the internal clock signal high when the external clock signal is above a first threshold and sets the internal clock signal low when the external clock signal is below a second threshold. The clock filter holds the internal clock signal constant for a period of time after the clock transitions.

Abstract: A processor, comprising a monitor for, depending on the respective embodiment, measuring a relative amount of idle time, activity time, or idle time and activity time associated with the processor, results of the measuring being used by the processor for controlling a clock speed. Yet other embodiments disclose, depending upon the respective embodiment, a processor, comprising a monitor for measuring the relative amount of Input/Output (I/O), relative importance of Input/Output (I/O), and/or relative amount of time between Input/Output (I/O), associated with the processor, results of the measuring being used by the processor to control power dissipation associated with the processor.