Abstract: Embodiments of the present invention are directed to a method and system for draining or aborting IO requests of a failed system prior to restarting or recovering an application in virtual environments. The method includes detecting, within an electronic system, an application error condition of an application executing on a virtual machine and determining an application restart target. The method further includes sending an input/output (IO) request drain command to a virtual IO server operable to provide storage to the virtual machine and receiving a signal that the IO requests have been drained. The drain command is operable to drain IO requests issued from the application. The application can then be restarted or recovered.

Abstract: Techniques for continuous data protection are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for reducing data protection system outages comprising polling a data protection client device, receiving a response from the data protection client device, parsing the response to determine whether restarting a data protection process is required, and restarting a data protection process on the data protection client device, if restarting the data protection process is required.

Abstract: A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an input module, a watchdog control module, and a frequency increasing module. The input module inputs an initial frequency of a CPU to the frequency generator to adjust a real-time frequency of the CPU. The watchdog control module sends a counter signal to the watchdog timer in a preset time interval. The watchdog timer receives the counter signal. If the watchdog timer does not receive the counter signal within the preset time, the watchdog timer outputs a reset signal to restart the computer. The frequency increasing module adds a preset increment to the real-time frequency to obtain a newly adjusted frequency, and provides the newly adjusted frequency to the frequency generator to adjust the real-time frequency.

Abstract: A system for recovering a server blade, in a multiple server blade computer, that is lost during a flash update operation on a service processor in the server blade. Because of the flash update failure, the lost server blade is unaware of its location on a management pathway, which in an exemplary form may be a midplane or a bus, which connects the server blade and a management module in a server blade chassis. The lost server blade puts a signal on the management pathway indicating that the flash failed. The signal is put on a special channel reserved for such messages. The management module receives the signal, and then determines which of the multiple server blades are lost due to the flash update failure.

Abstract: A failover control method for a virtual computer system including a plurality of virtual computers including: monitoring a second virtual computer via a first line by a first virtual computer among the plurality of virtual computers; detecting a malfunction of the second virtual computer by the first virtual computer; receiving from the other virtual computers a notification including a monitoring result for the second virtual computer in the other virtual computers among the plurality of virtual computers by the first virtual computer; relating the monitoring result to the detected malfunction of the second virtual computer to correspond to each other; judging whether or not the correspondence between the monitoring result and the detected malfunction of the second virtual computer satisfies a predetermined condition; and giving the second computer a reset instruction via a second line, when the predetermined condition is satisfied.

Abstract: A system is provided for controlling a right to use a computational component, comprising (a) a backup computational component 102 associated with a primary computational component 150, wherein when the primary computational component is in an operational mode the backup computational component is in a standby mode; (b) an activation agent 154 operable to determine when the primary computational component is no longer in the operational mode; (c) a timer 126 associated with the backup computational component; and (d) a mode setting agent 124 operable to permit the backup computational component to change to the operational mode when the value of the license error timer is not zero and to not permit the backup computational component to change to the operational mode when the value of the license error timer is zero.

Abstract: An integrated circuit chip includes a scan-in pin, a scan clock pin, and a test controller. The scan-in pin and the scan clock pin receive a test program for the type of test mode and a soft-reset pattern. A state machine is configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The state machine identifies a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggers a soft reset which eliminates the need for an extra reset pin, when testing in scan mode.

Abstract: A multi-microprocessor system and a control method for the same are provided. The multi-microprocessor system includes a first microprocessor and a second microprocessor. The second microprocessor is coupled to the first microprocessor. The second microprocessor transmits a detecting signal to the first microprocessor and determines a state of the first microprocessor by monitoring the first microprocessor for a predetermined time period. In the event that the first microprocessor crashes, the first microprocessor is immediately rest or restarted by the second microprocessor in order to maximize stability of the multi-microprocessor system.

Abstract: The present invention provides a CEC communications device which eliminates a troublesome process to solve the CEC-related communication malfunction when the CEC communications device detects a CEC-related communication malfunction caused by a software malfunction and improves serviceability of the CEC communications by automatically resetting the CEC to execute a CEC communication recovery. In the CEC communications device, when a CEC communications line monitoring unit detects a CEC-related communication malfunction caused by a software malfunction, a CEC control unit determines a reset order of a CEC appliance found on a CEC network, and notifies the CEC resetting unit of a CEC resetting request. The CEC resetting unit resets the CEC of a CEC appliance found on the CEC network via an HDMI line (DDC in FIG. 1) other than the CEC to recover the CEC communications.

Abstract: A system for pre-execution environment (PXE) booting a storage processor from a peer storage processor allows for the ability to reboot and/or restart the storage processor without an externally connected PXE server. In response to a reboot request of the storage processor, the peer storage processor pushes an operating system boot image and/or other information to the storage processor for PXE booting the storage processor, and vice versa. The system may also operate with multiple coupled computers.

Abstract: Methods and apparatuses for process a crossconnect switchover in a network element are described. According to one embodiment, an exemplary method includes synchronizing state information regarding broadband subscriber sessions of one or more circuits of a network element between one or more hub devices of an active control card and a standby control card of the network element, and in response to a crossconnect switchover, starting up one or more sessions associated with the one or more hub devices of the standby control card using the synchronized information, such that the one or more sessions are started up as if they are restarted. Other methods and apparatuses are also described.

Abstract: An interrupt-responsive non-volatile memory respond to an interrupt by aborting execution by a memory controller of a memory routine in a non-volatile memory, sets, a flag and executes an interrupt service routine; and upon completion of the interrupt service routine, in response to the flag, recovers the execution of the aborted memory routine.

Abstract: A reproducing apparatus 100 that reproduces content recorded in a recording medium 101 avoids reentering the same fault state and becoming unrecoverable at the time of occurrence of an unrecoverable CPU error, such as misalignment. Fault information is stored in nonvolatile memory, or the like, and the thus-stored fault information is used to cause reproduction control processing to branch before execution of a processing routine to be invoked at the time of occurrence of an unrecoverable CPU error, such as misalignment, thereby preventing the reproducing apparatus from reentering the same fault state.

Abstract: Methods, program products, and systems for monitoring extrinsic processes are described. A monitoring process can monitor one or more target processes. The target processes can be extrinsic, e.g., not spawned by the monitoring process. The monitoring process reads a process registry to identify which processes among multiple processes to monitor. The monitoring process can send status requests to the identified target processes periodically to check whether the target processes are healthy. If a target process is terminated, the monitoring process determines whether the termination is normal (e.g., by a user), or abnormal (e.g., the target process crashed). The monitoring process can restart the abnormally terminated or hung target process.

Abstract: A storage control apparatus of the present invention reduces the frequency of disk drive failures. An error management part manages the number of times errors occur in respective disk drives. A disk drive in which the number of errors meets or exceeds a threshold value is selected as a disk drive to be restarted. A restart control part commences difference management prior to restarting the disk drive targeted for restart. A difference management part manages parity group-related update locations using a difference bitmap. After commencing difference management, the restart control part restarts the disk drive in which the error was detected. This makes it possible to resolve an error caused by a firmware hangup or the like.

Abstract: A vehicle control apparatus includes a first storage area in which malfunction record information that is information on the record of a malfunction in a vehicle, and identifying information used to identify a program are stored in a nonvolatile manner; and a second storage area in which the program is stored in a rewritable and nonvolatile manner. If the identifying information stored in the first storage area does not match the identifying information corresponding to the rewritten program stored in the second storage area when rewriting of the program stored in the second storage area is completed, the control portion erases the malfunction record information in the first storage area, and rewrites the identifying information stored in the first storage area to the identifying information corresponding to the rewritten program.

Abstract: A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.

Abstract: A client device includes a command processing device. The command processing device is configured to transmit an error signal while in an abnormal operation mode to prevent an error due to no response to a command received from an external source and process the command while in a normal operation mode. The error signal is indicative of the abnormal operation mode.

Abstract: An electronic device comprises a first processor, a computer readable memory medium and logic instructions stored in the computer readable medium which, when executed by the first processor, configure the first processor to implement a watchdog module which monitors an operating status of one or more critical processes executing on the first processor and implements a recovery process when the one or more of the critical processes executing on the first processor fails. The device further comprises a system controller unit coupled to the first processor by a communication bus, wherein system controller unit activates the watchdog module periodically and only when the first processor is in at least one predetermined power state. Other embodiments may be described.

Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.

Abstract: A multiprocessor computer system comprises a plurality of processors distributed across a plurality of node coupled by a processor interconnect network. One or more of the processors is operable to manage hung processor instructions by setting a graduation timeout counter after a first program instruction graduates, resetting the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires, and resetting the processor if the graduation timeout counter expires before the subsequent program instruction graduates.

Abstract: Fatal errors are uncorrectable errors in hardware, which cause entire applications to be restarted and at worst can cause machine reboots. A method of recovering from a fatal error in a system having a plurality of components, in which the system includes a processor for executing a plurality of processes, comprises detecting an error in the system, determining which of the components caused the error, isolating processes affected by the error and recovering from the error. Assistance in error recovery can be provided by designing processes using check pointing, in which a back up of data pages is taken at predetermined points in a process, so that minimal loss of transactions occurs in the case of a fatal error.

Abstract: The present invention provides failure recognition, notification, and prevention for learning and self-healing capabilities in a monitored system. A system to collect monitoring data is monitored. A failure of the system is detected; A failure point for the detected failure in a data space defined by the monitoring data is identified and at least one predefined action with the identified failure point is associated. This process is repeated for a plurality of system failures. When a state of the system is determined to be approaching an identified failure point, the at least one predefined action associated with that identified failure point is performed.

Abstract: An electronic system comprises a processor, a diagnostic port, and a switching circuit, including a switch connected between the diagnostic port and the processor, for enabling and disabling the diagnostic port and for restricting access to contents of the electronic system prior to enabling the diagnostic port. A method for operating the electronic system is also included.

Abstract: A processor and memory system includes memory, a table of exceptions, and a processor. The memory includes a plurality of memory blocks. The table of exceptions identifies at least one of the plurality of memory blocks that includes an expected error. The processor diagnoses a security fault based on data stored in at least one of the plurality of memory blocks and the table of exceptions.

Abstract: A network element (NE) includes an intelligent interface (II) with its own operating environment rendering it active during the NE boot process, and with separate intelligence allowing it to take actions on the NE prior to, during, and after the boot process. The combination of independent operation and increased intelligence provides enhanced management opportunities to enable the NE to be controlled throughout the boot process and after completion of the boot process. For example, files may be uploaded to the NE before or during the boot process to restart the NE from a new software image. The II allows this downloading process to occur in parallel on multiple NEs from a centralized storage resource. Diagnostic checks may be run on the NE, and files, and MIB information, and other data may be transmitted from the II to enable a network manager to more effectively manage the NE.

Abstract: An image processing apparatus includes a volatile storing unit, a nonvolatile storing unit, a processing control unit, a transfer unit and a power controlling unit. The processing control unit controls image processing and writes a result of the control as history information into the volatile storing unit. The transferring unit transfers the history information from the volatile storing unit to the nonvolatile storing unit. The power controlling unit transfers the history information to the transferring unit transfer when detecting an abnormality of the processing control unit based on a communication with the processing control unit, and stops a supply of a power after a passage of a certain time since the detection of the abnormality.

Abstract: Systems and methods (“utility”) for providing a computer system with a mechanism to record live data on a continuous basis which may be analyzed subsequent to a fault condition is provided. The utility uses the existing DRAM memory of a computer system as a retentive DRAM (RDRAM) device that may be used to store the data. To accomplish this, software and firmware is provided for continuously refreshing the DRAM memory across resets that are due to fault conditions. Further, non-maskable interrupts (NMI) are used to flag a variety of fault conditions to the computer system. To make the utility platform independent, a standardized power and configuration interface is used to implement a computer system reset that preserves the contents of the RDRAM.

Abstract: A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided.

Abstract: Devices and methods for microprocessor supervision in a special purpose computer system are provided. One illustrative embodiment includes a first watchdog timer internal to the microprocessor and a second watchdog timer external to the microprocessor. In some cases, the internal watchdog timer may be initiated prior to or during the operating system startup and the external watchdog timer may be initiated after the operating system is up and running. The internal watchdog timer may have a relatively longer timer duration than the external watchdog timer, but is not required in all embodiments. In some embodiments, the internal watchdog timer may monitor the microprocessor's startup sequence and the internal watchdog timer and/or external watchdog timer may monitor the microprocessor when the operating system is up and running. If the microprocessor faults at any time during startup or while the operating system is up and running, the internal and/or external watchdog timer may trigger a microprocessor reset.

Abstract: A self-service terminal comprises a pc core and at least one module, which can be powered down independently of the pc core, the terminal has a control application and an agent arranged to monitor the fault state of the at least one module and cause a fault signal to be sent from the self-service terminal when the fault state of the at least one module is characteristic of a problem with the at least one module. The agent is arranged to determine if the module has been powered down; whereupon the fault signal is buffered until the module is powered up and a determination as to the fault state of the module is again made. The fault signal is only sent if the fault state still indicates there to be a problem with the at least one module.

Abstract: An electronic computing device including at least one processing unit that implements a specific fault signal upon experiencing an associated fault, a control unit that generates a specific recovery signal upon receiving the fault signal from the at least one processing unit, and at least one input memory unit. The recovery signal initiates specific recovery processes in the at least one processing unit. The input memory buffers input data signals input to the at least one processing unit that experienced the fault during the recovery period.

Abstract: A programmable processor calculates a hash value of a memory region, then monitors program operation to detect a security monitoring system initialization. The hash value is added to extend a security measurement sequence if the security monitoring system initialization clears a security state. Processors that implement similar methods, and systems using such processors, are also described and claimed.

Abstract: An interface controller initializing method for an information processing device equipped with multiple interfaces of the same type comprises the steps of: detecting control of an interface executed by a first control unit; detecting an end of the control of the interface by the first control unit executed according to instructions regarding the control of the interfaces issued by a second control unit; detecting abnormality regarding the control of an interface by the first control unit; allowing a user to input an initialization instruction for initialization of the first control unit; and executing the initialization of the first control unit on condition that the abnormality regarding the control of an interface by the first control unit has been detected, the initialization instruction has been inputted, and the end of the control of at least one of the other interfaces by the first control unit has been detected.

Abstract: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.

Abstract: A method, apparatus and system for restarting an emulated mainframe IOP, such as a failed or hung emulated mainframe IOP within an emulated mainframe commodity computer. The method includes a rescue process that polls a home location for Restart Request information. In response to receiving Restart Request information, the rescue process is configured to shut down the existing emulated mainframe IOP, start a new emulated mainframe IOP, and reset the home location. The Restart Request information can be provided to the home location by the mainframe computer being emulated. Alternatively, the rescue mechanism can use an interface management card instructed to restart the commodity computer hosting the failed or hung IOP, e.g., from a maintenance service and/or a maintenance program residing in an active commodity computer coupled to the commodity computers hosting one of several emulated mainframe IOPs.

Abstract: A network element (NE) includes an intelligent interface (II) with its own operating environment rendering it active during the NE boot process, and with separate intelligence allowing it to take actions on the NE prior to, during, and after the boot process. The combination of independent operation and increased intelligence provides enhanced management opportunities to enable the NE to be controlled throughout the boot process and after completion of the boot process. For example, files may be uploaded to the NE before or during the boot process to restart the NE from a new software image. The II allows this downloading process to occur in parallel on multiple NEs from a centralized storage resource. Diagnostic checks may be run on the NE, and files, and MIB information, and other data may be transmitted from the II to enable a network manager to more effectively manage the NE.

Abstract: In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls one of the Operating Systems when the processor receives an interrupt from a device, and the Operating System controls the device. Furthermore, a detecting unit detects an interrupt to the processor, a judging unit judges whether the Operating System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt, and a resetting unit resets the processor when the judging unit judges that the Operating Systcm 9em has not called the privileged software from the storage unit.

Abstract: A microcontroller receives a supply voltage (VCC) from one or more batteries. Rather than automatically resetting the microcontroller if VCC drops below a VBO voltage, a latent VBO reset circuit does not reset the processor if VCC drops below a second voltage (VBO) as long as VCC does not fall so low that a power on reset (POR) circuit of the latent VBO reset circuit is tripped. The processor continues to operate as long as it can below VBO, thereby maximizing battery usage. When VCC rises to a third voltage (for example, due to battery replacement), then the latent VBO reset circuit automatically resets the processor to remove potential ill-effects of having operated below VBO. User data stored in volatile memory is not lost during battery replacement. A special VBO bit in a processor-readable status register indicates that the microcontroller operated below VBO.

Abstract: An apparatus has at least one processing unit to generate a request having a request privilege level. At least one resource exists in the apparatus to receive the request and determine if the request is allowable. The apparatus includes an error handler that determines the nature of an error and performs a reset based upon the privilege level of the request that cause the error.

Abstract: A method and apparatus for compensating for a delay in the propagation of a plurality of signals via different signal paths, i.e., a skew compensation method, are provided. The apparatus includes a processing circuit which performs a data processing operation on input data, and a reset adjustment circuit which maintains a reset state of the processing circuit for a time period when a reset signal that initializes the processing circuit is received.

Abstract: A test apparatus for testing a portable communication unit. The test apparatus comprises a test unit adapted to supply test input data to the portable communication unit and retrieve test output data at least from the portable communication unit in accordance with a test schedule. The test apparatus further comprises a wireless interface unit adapted to provide a communication link between the test apparatus and a server located remotely from the test apparatus. The test unit is adapted to retrieve, from the server, at least part of the test input data. Moreover, the test unit is adapted to forward, to the server, at least part of the test output data. A method of testing the portable communication unit is also disclosed.

Abstract: A gaming machine may include memory, a software program loaded into the memory and a trusted cache. The trusted cache may include a context data save engine, a context data recovery engine and a restart engine. The context data save engine may be configured to save the context and state of the gaming machine at least upon sensing a failure condition. The context data recovery engine may be configured to load the context and state from the context data save engine back into memory, and the restart engine may be configured to restart the gaming machine and restore execution of the software program, and may be further configured to carry out a multi-stage recovery process that may include a soft reboot, a hardware reset and a power-off and, after a predetermined delay, a power-on of the gaming machine, attempting to restart the software program between each stage of the process.

Abstract: The device and method includes outputting a subsistence signal repeatedly that indicates that an information processing device is normally operating when the information processing unit is normally operating, executing a memory dump processing, if necessary, when a fault occurs in the information processing unit, monitoring whether another subsistence signal is output within a first time period after the subsistence signal is output, and determining whether or not the memory dump processing is being executed, requesting a restart or a shutdown of the information processing device if the memory dump processing is not being executed, and requesting the restart or the shut down of the information processing device after a second time period passes if the memory dump processing is being executed.

Abstract: A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer.

Abstract: A set-top terminal and related methods is provided that, in one embodiment, comprises a memory with proactive reboot logic and a processor configured with the proactive reboot logic to detect an indication of a critical condition associated with the set-top terminal, determine based on a current status of resources in the set-top terminal if a current time provides an opportunity for a reboot of the set-top terminal in a manner that reduces user intrusiveness, and effect a rebooting of the set-top terminal if the current time provides the opportunity, otherwise postponing the reboot.

Abstract: A method for operating a processor in data processing system comprises: asserting a debug control signal to cause the processor to enter a debug operating mode; initializing a plurality of shared processor resources with debug configuration information, wherein the plurality of shared processor resources are shared between a normal operating mode and the debug operating mode; executing instructions with the processor while in the debug operating mode; re-initializing the processor in response to a reset event; and preventing the reset event from re-initializing a predetermined portion of the debug configuration information in the plurality of shared processor resources. This allows processor debugging through reset events without losing the debug information.

Abstract: A status notification register storing a state of a function executing section is arranged for each function executing section. The function executing section includes at least one circuit for performing a predetermined function. By determining one of two values set in the status notification register, a power failure occurring in a functional unit is identified and an initial setting process is performed to an identified location when power is restored.

Abstract: Methods and apparatus to facilitate fast restarts in processor systems are disclosed. An example processor restart method disclosed herein includes recording a log of pre-boot initialization actions, and replaying a portion of the log during subsequent processor restarts to shorten pre-boot initialization time. The example processor restart method disclosed herein may further include creating a log index table for easier referral to portions of the log, storing the log and the log index table in non-volatile memory, using the log index table to reorder the replaying of the log, and reordering the replay of the log to initialize the video graphics adapter earlier in a processor restart sequence.

Abstract: Method, system and computer program product embodiments for, in an input/output (I/O) link handling complex instruction chains, a messaging scheme incorporating a method of error recovery between an initiator processor and a receiver processor, are provided. An operation initiation message is been sent from the initiator processor to the receiver processor for the receiver processor to begin work on an operation. If determined to be necessary, a terminate operation message is sent from the initiator processor to the receiver processor. The initiator processor withholds sending additional messages for the operation until a terminate operation response message is received. Once the terminate operation message is received, outstanding messages in process are flushed from the receiver processor. The receiver processor withholds sending additional messages to the initiator processor as the outstanding messages are completed.