Abstract: A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.

Abstract: Methods, systems, and devices for predictive media management for read disturb are described. A read disturbance manager can monitor a bit error rate for a block of a memory die. The read disturbance manager can detect that a degradation of the bit error rate satisfies a degradation threshold specific to the memory die. In some cases, the read disturbance manager can perform a write operation to write data from the block of the memory die to a second block of the memory die based on detecting that the degradation of the bit error rate satisfies the degradation threshold.

Abstract: The present application provides a method and a system for calculating a stripe of a strip for a disk, a terminal and a storage medium. The method includes: calculating a pack offset of a parity block according to a given disk index; calculating an address of a strip where the parity block is located in the disk according to the pack offset; comparing an address of a to-be-checked strip with the address of the strip where the parity block is located in the disk to determine whether the parity block is on the to-be-checked strip; and calculating a stripe index of the to-be-checked strip by considering redundant elements caused by the parity block in response to determining that the parity block is on the to-be-checked strip; or calculating the stripe index of the to-be-checked strip directly in response to determining that the parity block is not on the to-be-checked strip.

Abstract: A Fail Bit (FB) repair method and device can be applied to repairing an FB in a chip. The method includes: a bank to be repaired including multiple target repair regions in a chip to be repaired is determined; first repair processing is performed on a first FB in each target repair region by using a redundant circuit; a second FB position determination step is executed to determine a bit position of a second FB, and second repair processing is performed on the second FB; unrepaired FBs in each target repair region is determined, and the second FB position determination step is recursively executed to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position.

Abstract: A self-repair memory circuit includes a cell array, a controller, a row repair decoder, and a column repair decoder. The cell array includes rows and columns of memory cells. The controller receives an input indicating row repair or column repair, and a repair address shared by the row repair and the column repair of the cell array. The row repair decoder maps the repair address of a defective row to a redundant row of the cell array when the input indicates the row repair. The column repair decoder maps the repair address of a defective column to another column of the cell array when the input indicates the column repair.

Abstract: A storage system includes a central storage controller and a solid-state storage device operatively coupled to the central storage controller, the solid-state storage device including a processing device, the processing device to determine whether a die of the solid-state storage device is likely to fail. In response to determining that the die of the solid-state storage device is likely to fail, the processing device is further to mark the die of the solid-state storage device as likely to fail and transmit, to the central storage controller, an indication that the die of the solid-state storage device has been marked as likely to fail.

Abstract: Methods, systems and apparatus, including computer programs encoded on computer storage medium, for predicting a likelihood of a future computer memory failure. In one aspect training data inputs are obtained, where each training data input includes correctable memory error data that describes correctable errors that occurred in a computer memory and data indicating whether the correctable errors produced a failure of the computer memory. For each training data input, image representations of the correctable memory error data included in the training data input are generated. The image representations are processed using a machine learning model to output an estimated likelihood of a future failure of the computer memory. A difference between the estimated likelihood of the future failure of the computer memory and the data indicating whether the correctable errors produced a failure of the computer memory is computed. Values of model parameters are updated using the computed difference.

Abstract: Methods, systems, and devices for memory device health evaluation at a host device are described. The health evaluation relates to a host device that is associated with a memory device that monitors and reports health information, such as one or more parameters associated with a status of the memory device. The memory device may transmit the health information to the host device, which may perform one or more operations and may transmit the health information to a device of another entity of a system (e.g., ecosystem) including the host device. The host device may include one or more circuits for transmitting and processing the health information, such as a system health engine, a safety engine, a communication component, or a combination thereof. Based on a determination by the host device or information received from an external device, the host device may transmit a command to the memory device.

Abstract: Embodiments for a system and method of selecting data protection policies for a new system, by collecting user, policy, and asset metadata for a plurality of other users storing data dictated by one or more protection policies. The collected metadata is anonymized with respect to personal identifying information, and is stored in an anonymized analytics database. The system receives specific user, policy and asset metadata for the new system from a specific user, and matches the received specific user metadata to the collected metadata to identify an optimum protection policy of the one or more protection policies based on the assets and protection requirements of the new system. The new system is then configured with the identified optimum protection policy as an initial configuration.

Abstract: While a compiler compiles source code to create an executable binary, code is added into the compiled source code that, when executed, identifies and stores in a metadata table base and bounds information associated with memory allocations. Additionally, additional code is added into the compiled source code that performs memory safety checks during execution. This updated compiled source code automatically determines a safety of memory access requests during execution by performing an out-of-bounds (OOB) check using the base and bounds information retrieved and stored in the metadata table. This enables the identification and avoidance of unsafe memory operations during the implementation of the executable by a GPU.

Abstract: Duplication of files in a storage device of a computing device can be avoided using some techniques described herein. In one example, a system can determine a checksum of a file in a software package. The system can then determine that the file is absent from a storage device by issuing a command for accessing the file based on the checksum. In response to determining that the file is absent from the storage device, the system can download a copy of the file from a remote computing device to the storage device over a network.

Abstract: A processor may receive data regarding a reference source code commit. The processor may identify, using an artificial intelligence model, a first group of source code commits including source code commits similar to the reference source code commit, where each source code commit in the first group is associated with a repository. The processor may determine, using the artificial intelligence model, a first risk associated with implementing a first source code commit from the first group of source code commits. The processor may determine an error budget associated with a first repository associated with the first source code commit. The processor may determine a first time for implementing the first source code commit.

Abstract: A memory module system level tester device provides contact between the motherboard and the memory modules by using a test tray, thereby minimizing a time required for attaching and detaching the memory modules and omitting an additional configuration for attaching and detaching the memory modules. Accordingly, space limitations can be minimized, and as a result, test units can be arranged in two or more stages in the vertical direction to configure a compact layout to thereby increase space efficiency.

Abstract: A memory device includes an auto error check scrub (ECS) control circuit configured to generate an auto ECS command for performing an ECS operation based on a refresh control signal. The memory device also includes a burst ECS control circuit configured to generate an internal burst ECS command for performing the ECS operation every set period based on a burst ECS command and an ECS end flag. The memory device further includes an ECS address generation circuit configured to generate an ECS address for the ECS operation by counting an input of the auto ECS command or the internal burst ECS command and to generate the ECS end flag based on a value of the ECS address.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive new debug information, determine that a debug buffer does not have any available free entries for the new debug information, compare the priority information to a lowest priority information of old debug information stored in the debug buffer, remove a most recent old debug information that has a lowest priority information from the debug buffer, and place the new debug information and corresponding priority information in the debug buffer.

Abstract: A method for managing memory leaks in a memory device includes grouping, by a garbage collection system, a plurality of similar memory allocations of the memory device into one or more Unique Fixed Identifiers (UFIs); identifying, by the garbage collection system, one of the one or more UFIs having a highest accumulated memory size and adding each of the plurality of memory allocations in the identified one of the one or more UFIs into a Potential Leak Candidate List (PLCL); identifying, by the garbage collection system, the memory leaks in the memory device by identifying unreferenced memory addresses associated with the plurality of memory allocations in the PLCL; and releasing, by the garbage collection system, the identified unreferenced memory addresses associated with the plurality of memory allocations corresponding to the memory leaks into the memory device.

Abstract: According to one general aspect, a non-transitory computer readable medium includes instructions that, when executed by at least one processor, cause a computing device to read a string of a log file for an application, where the log file comprises multiple strings of log data, compare the string to signatures stored in a memory to find a matching signature, where each of the signatures is encoded with a signature identifier (ID), determine a deviation between the string and the matching signature, encode the string with the signature identifier (ID) of the matching signature and the deviation, and transfer the string to a destination computing device using the signature identifier (ID) of the matching signature, the deviation, and a timestamp of the string.

Abstract: Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system.

Abstract: An electronic device for diagnosing a fault of a plurality of external devices is disclosed. The electronic device comprises a communication unit and a processor.

Abstract: A stuck-at fault mitigation method for resistive random access memory (ReRAM)-based deep learning accelerators, includes: confirming a distorted output value (Y0) due to a stuck-at fault (SAF) by using a correction data set in a pre-trained deep learning network, by means of ReRAM-based deep learning accelerator hardware; updating an average (?) and a standard deviation (?) of a batch normalization (BN) layer by using the distorted output value (Y0), by means of the ReRAM-based deep learning accelerator hardware; folding the batch normalization (BN) layer in which the average (?) and the standard deviation (?) are updated into a convolution layer or a fully-connected layer, by means of the ReRAM-based deep learning accelerator hardware; and deriving a normal output value (Y1) by using the deep learning network in which the batch normalization (BN) layer is folded, by means of the ReRAM-based deep learning accelerator hardware.

Abstract: A data storage device includes a memory device having a plurality of blocks and a controller coupled to the memory device. The controller is configured to determine that an uncorrectable error correction code (UECC) failure has occurred to a block of the plurality of blocks, enable a UECC anti-strike mechanism, and erase the block. The UECC anti-strike mechanism comprises converting a read failure associated with the block to an erase failure. The controller is further configured to retire the block upon determining that the erase is unsuccessful.

Abstract: Facilitating outlier object detection in tiered storage systems is provided herein. A system can comprise a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations can comprise determining respective parameters associated with objects of a group of objects of a tiered storage system. The respective parameters can comprise at least one of a size, an access percentage, or a cost. The operations also can comprise using the respective parameters associated with the objects of the group of objects as inputs and performing data clustering on the group of objects, resulting in at least one data cluster. Further, the operations can comprise selecting at least one object from the group of objects as at least one outlier object within the tiered storage system based on the at least one data cluster.

Abstract: In one embodiment, a system for managing a virtualization environment comprises a plurality of host machines, one or more virtual disks comprising a plurality of storage devices, a virtualized file server (VFS) comprising a plurality of file server virtual machines (FSVMs), wherein each of the FSVMs is running on one of the host machines and conducts I/O transactions with the one or more virtual disks, and a virtualized file server self-healing system configured to identify one or more corrupt units of stored data at one or more levels of a storage hierarchy associated with the storage devices, wherein the levels comprise one or more of file level, filesystem level, and storage level, and when data corruption is detected, cause each FSVM on which at least a portion of the unit of stored data is located to recover the unit of stored data.

Abstract: Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.

Abstract: A method includes monitoring temperature characteristics for a plurality of memory components of a memory sub-system and determining that a temperature characteristic corresponding to at least one of the memory components has reached a threshold temperature. The method further includes determining a data reliability parameter for the at least one of the memory components that has reached the threshold temperature, determining whether the determined data reliability parameter is below a threshold data reliability parameter value for the at least one of the memory components that has reached the threshold temperature, and, based on determining that the data reliability parameter for the at least one of the memory components that has reached the threshold temperature is below the threshold data reliability parameter value, refraining from performing a thermal throttling operation.

Abstract: A memory system is provided. The memory system includes at least one memory device, and a controller configured to control the at least one memory device, wherein the controller includes: an error correction circuit configured to correct an error in data read from the at least one memory device, a codeword error counter configured to obtain a syndrome of a current codeword error based on a codeword error occurring in the error correction circuit, and to obtain a weighted codeword error count value by comparing the obtained syndrome with a previous syndrome, and an alert device configured to generate a warning signal for preventing an uncorrectable error of the at least one memory device according to the weighted codeword error count value.

Abstract: A secret key value that is inaccessible to software is scrambled according to registers consisting of one-time programmable (OTP) bits. A first OTP register is used to change the scrambling of the secret key value whenever a lifecycle event occurs. A second OTP register is used to undo the change in the scrambling of the secret key. A third OTP register is used to affect a permanent change to the scrambling of the secret key. The scrambled values of the secret key (whether changed or unchanged) are used as seeds to produce keys for cryptographic operations by a device.

Abstract: A method, computer program product, and computer system are provided. An operating system (OS) receives a status at completion of a cryptographic adjunct process (AP) instruction directed to an AP message queue on a cryptographic AP. The status includes a return code, a reason code, a queue full indicator, a queue empty indicator, and the count of enqueued request messages on the AP message queue. The OS determines a number of lost request messages on the AP message queue, based on a count of enqueued request messages on the AP message queue received in the status. The OS re-enqueues the number of lost request messages to the AP message queue. The OS recovers the number of lost request messages on the AP message queue.

Abstract: An information processing apparatus includes a fan that cools a first processor, a dust-proof bezel that prevents dust from entering a casing, a memory, and a second processor coupled to the memory. The second processor is configured to measure a temperature of the first processor and an air volume of an air flow which passes through the dust-proof bezel, compare a registered air volume to the measured air volume when the temperature matches a registered temperature included in comparison information stored in the memory. The registered air volume being included in the comparison information in association with the matched temperature and the comparison information including a registered temperature of the first processor and a registered air volume of an air flow generated by the fan in association with each other. The second processor determines an abnormality in the dust-proof bezel based on a comparison result.

Abstract: A storage device is disclosed. A first storage media may store data. The first storage media may be of a first storage type and may be organized into at least two blocks. A second storage media may also store data. The second storage media may be of a second storage type different from the first type, and may also be organized into at least two blocks. A controller may manage reading data from and writing data to the first storage media and the second storage media. Metadata storage may store device-based log data for errors in the storage device. The drive-based log data may include a first log data for the first storage media and a second log data for the second storage media. An identification circuit may identify a suspect block in the at least two blocks in the first storage media and the second storage media, responsive to the device-based log data.

Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash memory card. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: determining whether a temperature of a motherboard has exceeded a threshold through a temperature sensor IC after receiving a host read or write command from a host side; requesting a flash memory card to enter a sleep state when the temperature of the motherboard has exceeded the threshold; and instructing the flash memory card to perform an operation corresponding to the host read or write command when the temperature of the motherboard hasn't exceeded the threshold. The bridge IC and the temperature sensor IC are disposed on the motherboard, the flash memory card is inserted into a card slot on the motherboard, and the bridge IC is coupled to the temperature sensor IC and the flash memory card through a circuit of the motherboard.

Abstract: Technologies for logging and visualizing trace capture data in a data storage subsystem (e.g., storage application layers and data storage devices of a compute device) are disclosed herein. One or more storage events in the data storage subsystem are captured for a specified time period. Statistics are determined from the captured storage events. A visualization of the storage events and statistics for the specified time period is generated.

Abstract: Example implementations relate to determining a device wear-rate. An example system for determining a device wear-rate can include a plurality of filter drivers to: monitor system requests for I/O associated with a device of the system and transmit information associated with the system requests to a filter manager. The system can also include the filter manager to catalog the information, a service to collate the information across a plurality of machine configurations and workloads, and a processor to determine a wear-rate of the device based on an analysis of the collated information.

Abstract: A device such as a network-attachable data transfer device may be configured to operate in a cluster to coordinate the storage of data. A first manifest may be generated inventorying a first set of data successfully transferred to the data transfer device from a data source. A second manifest may be generated inventorying a second set of data successfully transferred from the data transfer device to a data destination. The first manifest may be compared with the second manifest to determine a transfer status of one or more data objects. The transfer status may indicate one or more data objects successfully transferred to the data destination from the data source. The one or more objects may be processed according to the transfer status.

Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for resynchronizing data in a storage system. One of the methods includes determining that a particular primary disk of a capacity object of a storage system has failed, wherein the capacity comprises a plurality of segments, and wherein the each segment comprises: a plurality of primary columns each corresponding to a respective primary disk of the capacity object, and a plurality of parity columns each corresponding to a respective parity disk of the capacity object; and resynchronizing, for each segment of one or more segments of the capacity object, the primary column of the segment corresponding to the particular primary disk using i) the primary columns of the segment corresponding to each other primary disk of the capacity object, ii) one or more parity columns of the segment, and iii) the column summaries of the segment.

Abstract: A method comprising: receiving, by a first storage node, an instruction to designate a first device file as the first storage node's primary device file for accessing a storage device designating, by the first storage node, the first device file as the first storage node's primary device file for accessing the storage device, the first device file being designated as the first storage node's primary device file for accessing the storage device in response to the first instruction; receiving, at the first storage node, an I/O command that is associated with the storage device; making a first attempt to complete the I/O command by using the first device file, detecting, by the first storage node, an error that is generated in response to the first attempt; designating, by the first storage node, a second device file as the first storage node's primary device file for accessing the storage device.

Abstract: Embodiments of information handling systems (IHSs) and computer-implemented methods are provided herein for testing system memory (or another volatile memory component) of an IHS. In the disclosed embodiments, memory testing is performed automatically: (a) during the pre-boot phase each time a new page of memory is allocated for the first time after a system boot, and (b) during OS runtime each time a read command is received and/or an event is detected. By proactively testing each page of memory, as the page is allocated but before information is stored therein, the systems and methods disclosed herein prevent “bad” memory pages from being used.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for resynchronizing data in a storage system. One of the methods includes receiving, by a first storage subsystem, a plurality of write requests corresponding to respective meta data blocks, wherein the first storage subsystem comprises a meta object; storing, by the first storage subsystem and for each write request, in each disk of the meta object, a version of the corresponding meta data block; determining that a particular disk of the meta object has failed; determining whether one or more valid versions of the meta data block are stored in respective other disks of the meta object; and in response to determining that one or more valid versions of the meta data block are stored in respective other disks of the meta object, resynchronizing the meta data block in the particular disk.

Abstract: A method and system may reconstruct data in a smart storage array where upon detection of data inconsistency, an application of the system is notified and affected data strips are rebuilt. When an initiator detects stripe corruption, the initiator may report the strip corruption to storage. The storage may lock the strip for I/O operations. Initiators may determine recovery scenarios for rebuilding the data strips and send the scenarios to storage. At storage, initiator replies may be collected, and a rebuild option with the highest votes may be automatically determined for a reconstruction operation. Once the reconstruction operation is completed, the rebuilt stripe may be unlocked and data operations may recommence.

Abstract: A chip testing device and a chip testing system are provided. The chip testing system includes a chip testing device and a plurality of environment control apparatuses. A plurality of electrical connection sockets are disposed on one side of a circuit board, and a plurality of testing modules are disposed on another side of the circuit board. A first fixing member and a second fixing member fix the electrical connection sockets on one side of the circuit board, and no screwing members are required to be screwed between the electrical connection sockets and the circuit board. Each of the electrical connection sockets with a chip disposed thereon can be disposed in a high temperature environment or a low temperature environment for testing along with the chip testing device, so that each of the chips does not need to be detached repeatedly.

Abstract: Systems and methods to throttle a universal backup host are described. The system executes a job, at a backup host, to back up a file set from a source host including fetching metadata from the source host. The system identifies a first operation set from operation sets, the operation set including a first operation. The system communicates, in parallel, requests for metadata items, over a network, to the source host, receives responses, and processes the responses by utilizing threads from a thread pool. The system generates latencies, counts the number of requests, and stores the latencies and number of requests in samples. The system aggregates the samples responsive to a timeout. The system resizes the thread pool based on the aggregating. Finally, the system backs up the file set from the source host based on the metadata.

Abstract: A storage device includes a nonvolatile memory, a communication interface connectable to a host, and a controller. The controller is configured to carry out writing of data that is received through the communication interface at a physical location of the nonvolatile memory when a write command associated with the data is received through the communication interface, control the communication interface to return a first notification upon determining that the writing of data at the physical location of the nonvolatile memory has completed, and control the communication interface to return a second notification a predetermined period of time after the first notification has been returned.

Abstract: In a storage system with multiple storage arrays configured to replicate a storage object, storage management applications are configured to exchange communications via private data replication links by encoding the communications as XML files and writing the files to their local storage array under a shared operating system. Other storage management applications poll their local storage arrays, discover the files, and then decode and read the communications. The communications may include messages, requests, and responses. Topics of interest may be specified in messages. Specific storage arrays may be designated as targets of requests. Responses are sent by encoding the responses as XML files and writing the files to respective local storage arrays under a shared operating system.

Abstract: A chip testing system includes a central control device, a chip mounting apparatus, a plurality of environment control apparatus, a classification apparatus, and a transferring apparatus. The central control device is configured to control the chip mounting apparatus to dispose a plurality of chips onto a chip testing device. Each of the environment control apparatus includes a plurality of accommodating chambers that are independent from each other. Each of the accommodating chambers is provided with a temperature adjusting device. The central control device is configured to control the transferring apparatus to place the chip testing device into one of the accommodating chambers. When the chip testing device carrying the chips is arranged in the corresponding accommodating chamber, the central control device is configured to control an operation of the corresponding temperature adjusting device, so that the chips are in an environment of a predetermined temperature.

Abstract: An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.

Abstract: Techniques are provided for maintaining timestamp parity during a transition replay phase to a synchronous state. During a transition logging phase where metadata operations executed by a primary node are logged into a metadata log and regions modified by data operations executed by the primary node are tracked within a dirty region log, a close stream operation to close a stream associated with a basefile of the primary node is identified. A determination is made as to whether the dirty region log comprises an entry for the stream indicating that a write data operation previously modified the stream. In an example, in response to the dirty region log comprising the entry, an indicator is set to specify that the stream was deleted by the close stream operation. In another example, a modify timestamp of the basefile is logged into the metadata log for subsequent replication to the secondary node.

Abstract: Techniques are provided for processing user input/output (I/O) write requests in a fault-tolerant data storage system (e.g., a RAID storage system) by selecting between performing a degraded write operation or a write operation to spare capacity, when the fault-tolerant data storage system is operating in a degraded mode. A method includes receiving a user I/O write request comprising data to be written to a RAID array operating in a degraded mode, and determining whether spare capacity has been allocated for rebuilding missing data of an inaccessible storage device of the RAID array and whether a missing data block, which is associated with I/O write request, has been rebuilt to the spare capacity. A degraded write operation is performed without using the spare capacity, when the missing data block, which is associated with the data of the I/O write request, has not been rebuilt to the allocated spare capacity.

Abstract: Methods, systems, and devices related to zone swapping for wear leveling memory are described. A memory device can perform access operations by mapping respective logical zones associated with respective logical addresses (e.g., of an access command) to respective zones of the memory device. As the memory device receives access commands and accesses respective zones, some zones may undergo a disproportionate amount of access operations relative to other zones. Accordingly, the memory device may swap data stored in some disproportionately accessed zones. The memory device can update a correspondence of respective logical zones associated with the zones based on swapping the data so that later access operations access the desired data.

Abstract: A set of two or more block families associated with a first voltage bin are selected. Each block family includes two or more pages of a memory device that have been programmed within a corresponding time window. The set of two or more block families includes a first block family and a second block family. Values of a data state metric for each of the set of block families is determined. A first voltage for the first block family and a second voltage for the second block family is determined based on the values of the data state metric. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.