Abstract: A set of two or more block families associated with a first voltage bin are selected. Each block family includes two or more pages of a memory device that have been programmed within a corresponding time window. The set of two or more block families includes a first block family and a second block family. Values of a data state metric for each of the set of block families is determined. A first voltage for the first block family and a second voltage for the second block family is determined based on the values of the data state metric. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.

Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.

Abstract: A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at successive points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.

Abstract: A test system for a memory device includes: a chamber including at least one test socket column having a plurality of test sockets arranged in a first direction, wherein memory devices to be tested are in respective ones of the plurality of test sockets, a temperature adjusting apparatus configured to supply air into the chamber according to a temperature control signal to control a temperature of the chamber, a test device electrically connected to the test sockets and configured to test the memory devices, and a temperature controller configured to receive temperature information of the memory devices from temperature sensors of the memory devices and to output to the temperature adjusting apparatus the temperature control signal to compensate for a temperature difference between a detected temperature of the memory devices and a target temperature.

Abstract: An instruction to perform load testing is sent to a mobile device where an application running on the mobile device determines whether the mobile device is in a state where load testing is permitted. In response to receiving the instruction, the application running on the mobile device performs load testing on a web server if the mobile device is in the state where load testing is permitted. Performance information associated with the load testing is received from the application running on the mobile device and the performance information associated with the load testing is displayed.

Abstract: Mechanisms are provided for cabling a set of enclosures. Using a set of cables that comprises eight physical layers (PHYs), the set of enclosures are coupled together such that: for a first enclosure and each intermediate enclosure in the set of enclosures, at least four PHYs of the eight PHYs terminate within a Serial Attached Small Computer System Interface (SCSI) (SAS) expander of the first enclosure and a SAS expander of each intermediate enclosure white passing through a remaining four PHYs of the eight PHYs without connecting to the respective SAS expander; and, for a last enclosure in the set of enclosures, all of the eight PHYs terminate in the SAS expander of the last enclosure.

Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.

Abstract: A device for monitoring a digital control unit with regard to functional safety is proposed. The device comprises an interface configured to receive a control signal of the digital control unit for a circuit component. The control signal represents a digital value. Furthermore, the device comprises a timer circuit configured to output an associated timer value in each case for successive points in time. The device furthermore comprises a hash value generator, which is configurable, in response to a change in the digital value, to recalculate a hash value on the basis of the change in the digital value and the timer value at the point in time of the change in the digital value.

Abstract: A chip testing method for being implemented by a chip testing system includes: a chip mounting step implemented by using a chip mounting apparatus to respectively dispose a plurality of chips onto electrical connection sockets of a chip testing device; a moving-in step implemented by transferring the chip testing device carrying the chips into one of accommodating chambers of an environment control apparatus; a temperature adjusting step implemented by controlling a temperature adjusting device of the one of the accommodating chambers so that the chips are in an environment having a predetermined temperature; and a testing step implemented by providing electricity to the chip testing device, so that each testing module of the chip testing device performs a predetermined testing process on the chips on the corresponding electrical connection sockets connected thereto.

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.

Abstract: To control initialization of a nonvolatile memory device, before assembling a memory system including a first nonvolatile memory device and a second nonvolatile memory device, information data for initialization of the first nonvolatile memory device are stored in the first nonvolatile memory device. After assembling the memory system, the information data are moved from the first nonvolatile memory device to the second nonvolatile memory device. The first nonvolatile memory device is initialized based on the information data stored in the second nonvolatile memory device. An initialization time of the first nonvolatile memory device is reduced efficiently by moving the information data from the first nonvolatile memory device to the second nonvolatile memory device having the rapid speed of the reading operation and using the information data read from the second nonvolatile memory device.

Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.

Abstract: Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.

Abstract: A memory system may include: a memory device configured to perform one or more of data write, read and erase operations; and a controller configured to execute an error management command and control the operation of the memory device, wherein the error management command is configured to determine first data which is highly likely to cause a read fail, among data stored in the memory device, determine one or more second data which is used to generate predicted error parity, and generate the predicted error parity based on the determined first and second data, and wherein the memory device performs the write operation to store indexes of the first and second data and the predicted error parity, under control of the controller.

Abstract: A memory system includes a plurality of memory devices configuring a plurality of ways, and a memory controller communicating with the plurality of memory devices through a channel, wherein each of the plurality of memory devices includes a device queue, and wherein the device queue queues a plurality of controller commands inputted from the memory controller.

Abstract: A memory system includes a memory device including a plurality of memory blocks capable of storing data, and a controller configured to determine an attribute of data stored in a memory block during an operating period. A duration of the operating period is changeable based on a parameter regarding the plurality of memory blocks. The duration of the operating period is adjusted in order to increase the accuracy of a determination of a usage pattern regarding the memory device.

Abstract: Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is initiated using the simulation data. A first machine region is identified during the functional simulation as associated with at least a first fault of the plurality of faults. A functional simulation of the first machine region is performed, and a divergence point associated with the first fault is identified. A fault simulation for the first fault is performed using the functional simulation of the first machine region and the divergence point.

Abstract: An information handling system includes a memory controller with an error logger, and a DIMM coupled to the memory controller via a memory channel. The DIMM includes a non-volatile memory device mapped to include event blocks that store error information associated with memory events occurring the memory controller, the DIMM, and the memory channel. Each event block includes a flag field and a data field. The error logger receives an indication that a memory event has occurred, reads first flag information from a flag field of an event block, determines whether the event block is locked based upon the first flag information, and if the event block is not locked, then writes second flag information to the flag field and writes event information to a data field of the event block. The event information describes the memory event.

Abstract: A computer-implemented method for dropped write error detection is proposed. In the method, a read request for a stride stored in an array of storage drives is received. The stride includes segments of a data and a first parity associated with the data spreading across the storage drives in the array of the storage drives. In response to the read request being a predefined sequential read request and a state of the stride being a first state, a parity check is performed on the stride. The first state indicates that no parity check has been performed after the data is written into the array of storage drives. The state of the stride is changed to a second state, and the second state is different with the first state.

Abstract: A method of clustering call stacks from a memory dumps resulting from out-of-memory errors includes accessing a memory dump resulting from an out-of-memory error; identifying call stacks in the memory dump that are associated with the out-of-memory error; accessing call stacks from one or more other memory dumps that were determined to be associated with other out-of-memory errors; generating clusters of call stacks based on a similarity score; and providing a cluster for an analysis of the out-of-memory error.

Abstract: A data processing apparatus includes a processor; and a direct memory access (DMA) controller coupled to the processor, the DMA controller including a control circuit that controls a DMA transfer of data, an error detection circuit that performs an error detection on the data based on a character assigned in association with the data to output a result of the error detection to the control circuit, and a diagnosis circuit that disconnects between the control circuit and the error detection circuit to diagnose an operation of the error detection circuit and provide a diagnosis result to the processor.

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

Abstract: Techniques for remapping portions of a plurality of non-volatile memory (NVM) dice forming a memory domain. A processing device partitions each NVM die into subslice elements comprising respective physical portions of NVM having proximal disturb relationships. The NVM allocation has user subslice elements and spare subslice elements. For the NVM dice forming the memory domain, the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for the memory domain. Identified user subslice elements having the highest error rates, remap to spare subslice elements of the memory domain that were not identified as having the highest error rates to remove subslice element or elements having highest error rates. At least one user subslice element is remapped from a first die of the memory domain to a second die of the memory domain.

Abstract: A processing device in a memory system determines that a first metric of a first memory unit on a first plane of a memory device satisfies a first threshold criterion. The processing device further determines whether a second metric of a second memory unit on a second plane of the memory device satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is lower than the first threshold criterion. Responsive to the second metric satisfying the second threshold criterion, the processing device performs a multi-plane data integrity operation to determine a first reliability statistic for the first memory unit and a second reliability statistic for the second memory unit in parallel.

Abstract: Systems and methods for an integrated reliability, availability, and serviceability (RAS) state machine are provided. Handling of RAS events by the Basic Input Output System (BIOS) of an integrated circuit device can result in lost processing time on the processing cores of a multi-core processor resulting from numerous system management interrupts generated by the BIOS. To reduce lost processing time, a dedicated state machine can execute instructions to handle RAS events independently of the BIOS and minimize the number of system management interrupts.

Abstract: Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.

Abstract: A memory device includes a memory array having at least one memory bank, where the at least one memory bank includes a target memory array and a clone memory array. The clone memory array corresponds to the target memory array and is configured to store the same data as in the target memory array. When a command that is applied to the target memory array to perform an operation, the command is also applied to the clone memory array. An error detection method adapted to a memory device having at least one memory bank that comprises a target memory array and a clone memory array is also introduced.

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.

Abstract: Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has interfaces between the logic device and memory device that cannot be directly accessed at a package ball. Test programs are concurrently executed by the logic device and the memory device to reduce testing time. Each memory device includes a BIST (built-in self-test) module that is initialized and executes the memory test program while the one or more modules within the logic device are tested.

Abstract: A memory device includes a memory block comprises a plurality of bits, wherein at least a first bit of the plurality of bits presents an initial logic state each time it is powered on; a start-up circuit configured to power on and off the memory block N times, where N is an odd integer greater than 1, and wherein the at least first bit presents an initial state after each respective power cycle of the memory block; and an authentication circuit, coupled to the memory block, and comprising an election engine that is configured to elect an initial state that occurs (N+1)/2 or more times after N power cycles that are performed by the start-up circuit, as a majority initial logic state for the first bit.

Abstract: Error recovery operations are provided for a memory system. The memory system includes a memory device including a plurality of cells and a controller. The controller performs a read on a select cell among the plurality of cells. The controller adjusts a log-likelihood ratio (LLR) value on the select cell to generate an adjusted LLR value, based on first read data on the select cell and second read data on at least one neighbor cell adjacent to the select cell, when the read on the select cell fails.

Abstract: A method and apparatus for generating a message interrupt. In one embodiment, the method includes writing a predefined data pattern to a predetermined source location in a memory system. One or more first data blocks are also stored in the memory system at one or more first locations, respectively. After storing the one or more first data blocks at the one or more first source locations, creating a first data structure that comprises one or more first source addresses mapped to one or more first destination addresses, respectively, and a predetermined source address mapped to a predetermined destination address, wherein the one or more first source addresses correspond to the one or more first source locations, respectively, and wherein the predetermined source address corresponds to a predetermined source location. The first data structure can be used by a DMA controller to transfer data stored at the one or more first storage locations and to transfer the predetermined data.

Abstract: An alert configuration system facilitates accurate and reliable configuration of alerts for data protection policy in a data protection system, including eliminating or reducing manual configuration of data protection policy. The system identifies risks through trend analysis and behavioral statistics as applied to historical data, and automatically configures alerts for the identified risks so that alerts are generated upon detection of the identified risks. After detecting differences between tracked values for a data protection system and predicted values obtained through trend analysis and behavioral statistics as applied to the historical data, the alert configuration system automatically adjusts the configuration of alerts for data protection policy in accordance with the predicted values.

Abstract: Methods and systems for dynamic handling of call home data are provided. A system for providing dynamic handling of call home data includes an event detection module that detects one or more events in the operation of one or more components. The system may also include a data request module that requests call home instructions from an upload data manager in response to the detected one or more events. Also, the upload data manager provides call home instructions. The system may further include a call home transmission module that collects call home data based on the call home instructions and provides the collected data to an upload server.

Abstract: A separate family space is provisioned as a separate fault domain for each production device in a storage system. The space provisioned for each family has contiguous logical block addresses that do not overlap with the address space of any other family. Snaps and clones in a first family space are used for fault recovery without interrupting IOs to a second family space. If the first family space points to the same virtual block as other families as a result of deduplication then the virtual block is un-deduped. For example, another instance of the virtual block may be created and pointers updated such that only the first family space points to one of the virtual block instances.

Abstract: A secret key value that is inaccessible to software is scrambled according to registers consisting of one-time programmable (OTP) bits. A first OTP register is used to change the scrambling of the secret key value whenever a lifecycle event occurs. A second OTP register is used to undo the change in the scrambling of the secret key. A third OTP register is used to affect a permanent change to the scrambling of the secret key. The scrambled values of the secret key (whether changed or unchanged) are used as seeds to produce keys for cryptographic operations by a device.

Abstract: A memory system including: a memory apparatus including a buffer die, core dies disposed on the buffer die, channels and a through silicon via configured to transmit a signal between the buffer die and at least one of the core dies; a memory controller configured to output a command signal and an address signal to the memory apparatus, to output a data signal to the memory apparatus and to receive the data signal from the memory apparatus; and an interposer including channel paths for connecting the memory controller and the channels, wherein the memory apparatus further includes a path selector for changing a connection state between the channels and channel paths, and when an error is detected in a first connection state between the channels and the channel paths, the path selector changes the first connection state to a second connection state.

Abstract: Managing a pool of virtual functions including generating a virtual function pool comprising a plurality of virtual functions for at least one single root input/output virtualization (SR-IOV) adapter; creating a control path from a client virtual network interface controller (VNIC) driver in a first client partition to a target network using an active virtual function; receiving a failure alert indicating that the control path from the client VNIC driver in the first client partition to the target network using the active virtual function has failed; selecting, from the virtual function pool, a backup virtual function for the first client partition based on the failure alert; and recreating the control path from the client VNIC driver in the first client partition to the target network using the backup virtual function.

Abstract: A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal.

Abstract: A method used in a flash memory controller includes: using a watchdog timer to automatically count a number and to generate a reset trigger signal to a processor if the number counted by the watchdog timer is higher than a threshold; after receiving the reset trigger signal from the watchdog timer, using the processor to copy registry information from at least one of processor, flash memory interface controller, and protocol controller, and then to control the memory controller to write the copied registry information into the dynamic random access memory device without rebooting a system of the flash memory controller.

Abstract: A queue-based task management system is provided. Unlike conventional queue-based task management systems, the system described herein does not handle all tasks in the conventional manner. Rather, tasks can be associated with one of several modes, including: a queue-mode (always storing the task in the queue) and an immediate-mode (record the task, but execute it immediately if possible). The two modes may be controlled programmatically to optimize utilization of system resources. Immediate-mode is implemented by monitoring available task system resources, and executing the task immediately in-process if there are resources available; otherwise the task is delegated to the queue. This in-process execution allows the sharing of parent task resources.

Abstract: Systems, apparatuses and methods may provide for technology to conduct, by a storage device, a state analysis of the storage device based on an assert log associated with a failure condition in the storage device. The technology may also return, by the storage device, the storage device to service if the state analysis indicates that the storage device is operable. Additionally, the technology may remove, by the storage device, the storage device from service if the state analysis indicates that the storage device is inoperable.

Abstract: A system, according to one embodiment, includes: an automated data storage library which includes a designated physical mechanism accessible at the automated data storage library, and a memory. The automated data storage library is configured to capture a snapshot of one or more logs in response to the designated physical mechanism being triggered. The automated data storage library is also configured to store the snapshot in the memory. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A system and method for efficiently distributing data among multiple storage devices. A data storage array receives read and write requests from multiple client computers. The data storage array includes multiple storage devices, each with multiple allocation units (AUs). A storage controller within the data storage array determines a RAID layout for use in storing data. In response to determining a failure of a first AU, the storage controller begins reconstructing in a second AU the data stored in the first AU. For read and write requests targeting data in the first AU, the request is serviced by the first AU responsive to determining no error occurs when accessing the first AU.

Abstract: An illustrative data storage management system comprises “awareness logic” that executes on computing devices hosting storage management components such as storage manager, data agent, media agent, and/or other storage management applications. The illustrative awareness logic operates within each of these illustrative components, e.g., as a thread within processes of the storage management component, such as storage management core process, file identifier process, log monitoring process, etc. The awareness logic monitors the targeted process over time and triggers remedial action when criteria are met. Certain vital statistics of each process are collected periodically and analyzed by the illustrative awareness logic, such as CPU usage, memory usage, and handle counts. Criteria for corrective action include rising trends based on local minima data points for one or more vital statistics of the process. Other criteria include exceeding a threshold based on a logarithm function of the collected data points.

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols for the memory modules. A host receives and decodes the ECC symbols and executes error correction operations. The host and the memory modules are coupled by a number of channels.

Abstract: A test system for a memory device includes: a chamber including at least one test socket column having a plurality of test sockets arranged in a first direction, wherein memory devices to be tested are in respective ones of the plurality of test sockets, a temperature adjusting apparatus configured to supply air into the chamber according to a temperature control signal to control a temperature of the chamber, a test device electrically connected to the test sockets and configured to test the memory devices, and a temperature controller configured to receive temperature information of the memory devices from temperature sensors of the memory devices and to output to the temperature adjusting apparatus the temperature control signal to compensate for a temperature difference between a detected temperature of the memory devices and a target temperature.

Abstract: An example apparatus includes a first memory and a second memory coupled to the first memory. A controller may be coupled to the first memory and the second memory. The controller may be configured to cause the apparatus to be initialized by executing instructions on the first memory device. Initializing the apparatus may include operating the apparatus according to a set of semantics different than a set of semantics used by the second memory device. The controller may be configured to cause a determination regarding at least one health characteristic of the second memory to be made subsequent to the apparatus being initialized.