Component Dependent Technique Patents (Class 714/40)
  • Patent number: 11589175
    Abstract: A method of identifying errors related to a computing device comprising detecting an input to the computing device, comparing the detected input with a threshold, wherein the threshold corresponds to a level of input indicating frustration by a user, determining whether the input meets or exceeds the threshold, and when the input meets or exceeds the threshold, identifying, by the one or more processors, an error related to the computing device.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 21, 2023
    Assignee: Google LLC
    Inventor: Jonathan D. Hurwitz
  • Patent number: 11457247
    Abstract: Provided are an edge computing method and apparatus, an edge device and a storage medium. The method includes that: multiple channels of original videos of a target scenario are acquired; synchronous access processing is performed on the multiple channels of original videos to obtain multiple channels of synchronous videos, and multiple frames of synchronous images are acquired based on the multiple channels of synchronous videos; computer vision collaborative analysis is performed on the multiple frames of synchronous images to obtain a collaborative processing result; and service logic processing is performed with configuration information synchronized from a cloud server in advance and corresponding to the target scenario, as well as the collaborative processing result to obtain a service processing result.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: September 27, 2022
    Assignee: SENSETIME INTERNATIONAL PTE. LTD.
    Inventors: Jinliang Lin, Jiacheng Wu, Dongliang Sun, Shuai Zhang
  • Patent number: 11425431
    Abstract: Provided are an edge computing method and apparatus, an edge device and a storage medium. The method includes that: multiple channels of original videos of a target scenario are acquired; synchronous access processing is performed on the multiple channels of original videos to obtain multiple channels of synchronous videos, and multiple frames of synchronous images are acquired based on the multiple channels of synchronous videos; computer vision collaborative analysis is performed on the multiple frames of synchronous images to obtain a collaborative processing result; and service logic processing is performed with configuration information synchronized from a cloud server in advance and corresponding to the target scenario, as well as the collaborative processing result to obtain a service processing result.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: August 23, 2022
    Assignee: SENSETIME INTERNATIONAL PTE. LTD.
    Inventors: Jinliang Lin, Jiacheng Wu, Dongliang Sun, Shuai Zhang
  • Patent number: 11349726
    Abstract: Service assurance using real-time monitoring, management and maintenance capabilities is enabled to provide customers and vendors with information related to the state of the service. The service assurance domain implements end-to-end functionality with a level of granularity sufficient to diagnose issues to the device and call/session level.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: May 31, 2022
    Assignee: AT&T MOBILITY II LLC
    Inventors: Melanie Sater, Ginger Chien, Dan Druta
  • Patent number: 11232012
    Abstract: A computer-implemented method that includes monitoring execution of program code by first and second processor components. A computing system detects that a trigger condition is satisfied by: i) identifying an operand in a portion of the program code; or ii) determining that a current time of a clock of the computing system indicates a predefined time value. The operand and the predefined time value are used to initiate trace events. When the trigger condition is satisfied the system initiates trace events that generate trace data identifying respective hardware events occurring across the computing system. The system uses the trace data to generate a correlated set of trace data. The correlated trace data indicates a time ordered sequence of the respective hardware events. The system uses the correlated set of trace data to analyze performance of the executing program code.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 25, 2022
    Assignee: Google LLC
    Inventors: Thomas Norrie, Naveen Kumar
  • Patent number: 11233808
    Abstract: In a networking system including a plurality of nodes connected with each other by a communication network, each node includes an abnormality discrimination unit configured, when a cumulative consumption current at the time of processing the data received from other node is out of a range (of current values estimated in advance based on an event at the other node, to discriminate the other node as an abnormal. By the networking system, the abnormality of the nodes on the network may be detected with a simple configuration.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: January 25, 2022
    Assignee: UNIVERSITY OF TSUKUBA
    Inventors: Hiroaki Nishikawa, Shuji Sannomiya
  • Patent number: 11175836
    Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo, Shyamkumar Thoziyoor, Ravindra Kumar
  • Patent number: 10972363
    Abstract: A system and methods for providing service assurance using real-time monitoring, management and maintenance capabilities to provide customers and vendors with information related to the state of the service. The service assurance domain implements end-to-end functionality with a level of granularity sufficient to diagnose issues to the device and call/session level.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 6, 2021
    Assignee: AT&T MOBILITY II LLC
    Inventors: Melanie Sater, Ginger Chien, Dan Druta
  • Patent number: 10970174
    Abstract: Methods, systems, and computer program products that can pre-emptively swap operations of a data production site to a disaster recovery (DR) site. A method includes providing, by a processor, one or more weighting factors to a set of metrics for an event occurring at a data production site based on information related to the event, analyzing the set of metrics based on the one or more weighting factors, and generating a recommendation related to swapping operations from the data production site to a DR site based on the analysis. Systems and computer program products for performing the above method are also provided.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gregory E. McBride, David C. Reed
  • Patent number: 10896001
    Abstract: Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, an integrated circuit device can be operable to determine, at a point in time during operation of the integrated circuit device, to generate a notification. The notification can include a type and a timestamp indicating the point in time. The notification can also include information about an internal status of the integrated circuit at the point in time. The device can further selectin a queue from a plurality of queues in a processor memory of the computing system that includes the integrated circuit. The device can further generate a write transaction including the notification, where the write transaction is addressed to the queue. The device can further output the write transaction using a communication interface of the device.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: January 19, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A. Volpe, Nafea Bshara, Raymond Scott Whiteside, Ron Diamant
  • Patent number: 10761915
    Abstract: Embodiments for preemptive deep diagnostics of resources in a disaggregated computing environment. Responsive to detecting a threshold breach of a recurrent event associated with a first resource of a first resource type executing a workload, an alert is generated; and responsive to receiving the alert, the execution of the workload on the first resource is ceased. Health check diagnostics are identified and invoked on the first resource based on the alert and a server telemetry. Results of the health check diagnostics are mapped to a set of learned failure patterns; and a potential failure of the first resource is predicted based on the mapping.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruchi Mahindru, John A. Bivens, Min Li, Valentina Salapura, Eugen Schenfeld
  • Patent number: 10733117
    Abstract: A radio frequency transceiver device comprises a control register unit including one or more registers and a central processing unit arranged to access the one or more registers via a memory bus. The device also comprises a sequencer module comprising one or more configuration registers connected to the central processing unit via a control bus and also comprises one or more trigger inputs. A sequencer memory module is connected to the sequencer module and is arranged to store one or more read/write commands comprising instructions to read from and/or write to the registers within the control register unit. The sequencer module is arranged such that upon receiving a trigger event via at least one of the one or more trigger inputs, it executes the one or more read/write commands.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 4, 2020
    Assignee: Nordic Semiconductor ASA
    Inventors: Joni Jäntti, Kimmo Puusaari, Hannu Talvitie, Olli Närhi
  • Patent number: 10671495
    Abstract: Examples disclosed herein relate performing a disaster recovery rehearsal of a workload in a three-datacenter topology. A workload may be selected on a computing system at a first datacenter location of a three-datacenter topology, for performing a disaster recovery rehearsal. The three-datacenter topology may comprise a first datacenter location, a second datacenter location and a third datacenter location. At least one of second datacenter location or third datacenter location may be selected for performing the disaster recovery rehearsal. A configuration of the workload may be cloned to generate a cloned workload. A resource may be identified in a selected datacenter location for performing the disaster recovery rehearsal. The cloned workload may be applied to the resource in the selected datacenter location, and a result of running the cloned workload on the resource may be generated. The computing system may receive the result from the selected datacenter location.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: June 2, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Ravi Mishra, Prabhanjan Gururaj, Bhakthavatsala K. Naidu
  • Patent number: 10673686
    Abstract: Systems and method for automatically composing resources with redundant fabric switches to support dual path HA storage access operation in a data center are provided. A data management module can be used to determine one or more drives in the data center that are connected to fabric switches. The fabric switches have a same chassis ID. The data management module can then associate the one or more drives to a first computer system via one fabric switch of the fabric switches, and associate the one or more to a second computer system via the other one fabric switch of the two fabric switches. In response to receiving a request from a specific user, the data management module can compose suitable resources of the data center to match the request based at least upon the one or more drives, the two switches, the first computer system, and the second computer system.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 2, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Feng-Kuang Wu, Ching-Chih Shih
  • Patent number: 10585943
    Abstract: In one embodiment, an operating system (on a computer device in a network of computer devices) interfaces with a distributed graph database that is distributed across the network of computer devices, and executes an application that has one or more parent data constructs that reference one or more child objects within the distributed graph database. Specifically, the one or more child objects each have a location-independent object identifier (OID) having at least: a) an OID-identifier (OID-ID) assigned upon creation to each particular child object by a data source of the location-independent OID; b) an OID-source structure that uniquely identifies the data source of the location-independent OID within the network of computer devices; and c) an OID-pointer indicative of a relative location of the particular child object in a memory mapped region. Accordingly, the operating system accesses the child objects (e.g., for an application) based on the location-independent OID.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: March 10, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Vinit Rajan Kizhakkel, Jeffrey Y. D Lo, Pratap Pereira
  • Patent number: 10484256
    Abstract: A method for determining that a defect applies to a network device that includes receiving, at a monitoring module, network device information from the network device. The network device information includes state information for the network device and does not include hardware and software version information. The method includes storing, in a network device database, the network device information from the network device and receiving, at the monitoring module, defect information about a defect. The defect information includes network device criteria specifying what state information is required for a network device to be affected by the defect. The method includes storing the defect information in a defect database, determining that the defect applies to the network device based on analyzing the network device information and the defect information from their respective databases, and, based on the determination, informing a defect alert recipient that the defect applies to the network device.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 19, 2019
    Assignee: Arista Networks, Inc.
    Inventors: Douglas Alan Gourlay, Kenneth James Duda, Andre Henri Joseph Pech
  • Patent number: 10423671
    Abstract: All environment for creating a document by collaboration of multiple concurrent users, coupled through a network to a server system, user undo and redo commands and those commands are associated with corresponding undo selection behavior data and redo selection behavior data. The undo and redo selection behavior data specify how the selection of one or more objects changes when undo or redo commands are involved. The undo and redo selection behavior data are transformed based on changes to a server copy.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: September 24, 2019
    Assignee: Apple Inc.
    Inventors: David A. Underwood, Elizabeth G. Reid, Peter Su
  • Patent number: 10296433
    Abstract: A method for testing a device under test (DUT) during a test sequence. In accordance with one embodiment, during a regular, pre-defined test sequence, data packets are transferred from a tester to a device under test (DUT) containing data related to at least one of an identification parameter of the DUT, an operational characteristic of the DUT and a request for data. Examples of such transferred data include address data for identifying the DUT (e.g., a unique media access control (MAC) address) and calibration data for controlling an operational characteristic of the DUT (e.g., signal power levels, signal frequencies or signal modulation characteristics). In accordance with another embodiment, the DUT retrieves and transmits data to the tester, either in response to the request for data or as a preprogrammed response to its synchronization with the tester.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: May 21, 2019
    Assignee: LitePoint Corporation
    Inventors: Christian Volf Olgaard, Sheguang Yin, John Christopher Lukez
  • Patent number: 10235279
    Abstract: The embodiments herein relate to Graphical User Interface (GUI) testing and, more particularly, to automate the testing of GUI for non-standard displays. Initially, an automation module is pre configured with the test cases that are required to test the GUI of the Device Under Test (DUT). Further, the DUT's display is auto configured with an interpretation & reconstruction module which fetches the display parameters and allocates required memory in a memory buffer. Later, the automation module provides the system inputs to DUT in which test cases are executed. Now, the interpretation & reconstruction module interprets and reconstructs the GUI content of DUT by fetching it from its display port. Later, the reconstructed display content will be updated to the memory buffer which is further verified by automation module.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 19, 2019
    Assignee: HCL TECHNOLOGIES LIMITED
    Inventor: Sivasakthivel Sadasivam
  • Patent number: 10235065
    Abstract: Systems, methods, and computer readable storage mediums for generating an alert on a failure of a storage subsystem to phone home to the cloud in a replication environment. A dataset is replicated from a first storage subsystem to a second storage subsystem. The first and second storage subsystems also phone home log data to the cloud on a periodic basis. In response to detecting a failure of the first storage subsystem to phone home, the cloud generates and sends an alert to the second storage subsystem. In response to receiving this alert, the second storage subsystem starts disaster recovery operations for the dataset.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: March 19, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Ethan L. Miller, Benjamin Borowiec, Steve Hodgson
  • Patent number: 10111591
    Abstract: An apparatus for real time monitoring of a patient is provided and includes a memory element for storing data, a processor that executes instructions associated with the data, an interface that receives sensor data from a sensor that takes measurements from the patient and sends the sensor data according to the sensor's measurement latency, a latency calculator that frequently calculates a latency threshold that varies according to at least a health status of the patient, a timer that continuously monitors the sensor's measurement latency, a comparator that frequently compares the sensor's measurement latency with the calculated latency threshold, and a feedback module that automatically changes the sensor's measurement latency to match with the calculated latency threshold.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: October 30, 2018
    Assignee: NANTHEALTH, INC.
    Inventors: David Dyell, Christopher Rogowski, Scott Kahler, Jennifer Milan
  • Patent number: 10067700
    Abstract: A capability to store meta-information related to file access histories on tape recording systems is provided. Base meta-information is stored on a tape. The base meta-information is meta-information that is associated with one or more files that are stored on the tape and is based, at least in part, on a tape access operation history. A first quantity of differentiated meta-information is stored on the tape at a predetermined time interval after storing the base meta-information, wherein the first quantity of differentiated meta-information is based, at least in part, on the tape access operation history and reflects a history of at least one file of the one or more files that are associated with the base meta-information.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Terue Watanabe, Noriko Yamamoto
  • Patent number: 9781024
    Abstract: Various embodiments manage data flow between at least one wireless communication device and at least one application executing at an edge of the wireless communication network. In one embodiment, a first flow regenerator disposed within the network generates a replicated set of data packets. The replicated set of data packets are a copy of a set of data packets being transmitted between an application disposed on a first node at an edge of the network and a wireless communication device. The first flow regenerator sends the replicated set of data packets to a second flow regenerator disposed in the network. The replicated set of data packets are sent to the second flow regenerator through at least a second node disposed between the first flow regenerator and the second flow regenerator. The second node is configured to perform one or more book-keeping operations on the replicated set of data packets.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: October 3, 2017
    Assignee: International Business Machines Corporation
    Inventor: Dinesh Verma
  • Patent number: 9739393
    Abstract: A valve controller configured to operate on a Foundation Fieldbus Network and including a spool valve movable between at least an opening position and a closing position, and a flapper nozzle pilot valve arranged to move the spool between the opening position and the closing position.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: August 22, 2017
    Assignee: Pentair Flow Control AG
    Inventors: Raymond P. Grandich, William F. Tatum
  • Patent number: 9729405
    Abstract: A system and methods for providing service assurance using real-time monitoring, management and maintenance capabilities to provide customers and vendors with information related to the state of the service. The service assurance domain implements end-to-end functionality with a level of granularity sufficient to diagnose issues to the device and call/session level.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 8, 2017
    Assignee: AT&T MOBILITY II LLC
    Inventors: Melanie Sater, Ginger Chien, Dan Druta
  • Patent number: 9661155
    Abstract: An image forming apparatus includes: an error detector detecting an error occurring in the image forming apparatus; a storage storing pieces of error handling information and test modes in association with each other, each of the pieces of error handling information indicating a method of error handling for each of errors occurring in the image forming apparatus, the test modes to be executed during the error handling; and an error controller reads, from the storage, the piece of error handling information and one or more of the test modes corresponding to an error detected by the error detector, generates an error handling screen including the read piece of error handling information and a transition button for transition to a test mode list screen for displaying a list of the read one or more of the test modes, and displays the generated error handling screen on a display.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: May 23, 2017
    Assignee: RISO KAGAKU CORPORATION
    Inventor: Aya Okada
  • Patent number: 9552248
    Abstract: Systems, methods, and computer readable storage mediums for generating an alert on a failure of a storage subsystem to phone home to the cloud in a replication environment. A dataset is replicated from a first storage subsystem to a second storage subsystem. The first and second storage subsystems also phone home log data to the cloud on a periodic basis. In response to detecting a failure of the first storage subsystem to phone home, the cloud generates and sends an alert to the second storage subsystem. In response to receiving this alert, the second storage subsystem starts disaster recovery operations for the dataset.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: January 24, 2017
    Assignee: Pure Storage, Inc.
    Inventors: Ethan L. Miller, Benjamin Borowiec, Steve Hodgson
  • Patent number: 9519536
    Abstract: Systems and methods for generating a visual indicator based on receiving a report of a transaction processing error, the error comprising an informality in a software instruction code executed during a first attempt to process a transaction. The systems may be configured to determine a preconfigured time period for correcting the software instruction code causing the transaction processing error and compare it to the actual time it took to correct the software instruction code to determine whether the processing error was corrected within the preconfigured time period. The system and method may then generate and communicate a visual indicator based on determining whether the error was corrected within preconfigured time period.
    Type: Grant
    Filed: January 1, 2015
    Date of Patent: December 13, 2016
    Assignee: Bank of America Corporation
    Inventor: Piyush Arora
  • Patent number: 9342414
    Abstract: A reserve power bus ring links multiple reserve power systems to computer systems in a data center. The reserve power bus ring enables multiple reserve power systems to concurrently provide reserve power support to sets of computer systems. The reserve power bus ring includes portions to which one or more reserve power systems and computer systems are coupled, and isolation devices collectively isolate particular portions of the reserve power bus ring in response to a fault condition in that particular portion, such that that computer systems on other portions of the ring continue to receive reserve power support from the reserve power systems coupled to the remaining portions. A reserve power bus ring may include respective power buses coupling two or more reserve power systems on an upstream side and a downstream side, and isolation devices can break a connection of the power bars to isolate the reserve power systems.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 17, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Huyen Van Nguyen, Kelsey Michelle Wildstone, Paul Andrew Churnock, Matthew David Striffler
  • Patent number: 9124727
    Abstract: An application in an image processing apparatus presents information about ink installed in a peripheral device, such as the shape, color, size, arrangement direction, and a remaining ink level of an ink tank, in a visually realistic manner using accurate graphics. The image processing apparatus acquires ink information about, in particular, a remaining ink level, arrangement direction, and the order of the arrangement of the ink tank, and displays the information about the peripheral device in a user interface of the application using the acquired ink information.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: September 1, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideki Honda, Koichi Abe
  • Patent number: 9092329
    Abstract: A computer implemented method may include identifying one or more business process runtime events received at an events queue of a process integration runtime component. One or more errors associated with the business process runtime events may be identified. The one or more errors may be evaluated based, at least in part, on one or more rules associated with the business process runtime event and configuration information associated with the process integration runtime component. The one or more rules may be associated with the business process runtime event and configuration information associated with the process integration runtime component having the same format. An alert for the one or more errors associated with the business process runtime event can be stored.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 28, 2015
    Assignee: SAP SE
    Inventor: Tihomir Stoyanov
  • Patent number: 9064054
    Abstract: A method and apparatus for synchronizing execution of a test application is described. In one embodiment, the method includes receiving two or more commands from a test application. The method may also include distributing a first command from the received two or more commands to a plurality of client computer systems, each client computer system to issue the first command to a server computer system. Furthermore, the method may include distributing a second command from the received two or more commands to the plurality of client computer systems after receipt of a response to the first command from each of the plurality of client computer systems.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: June 23, 2015
    Assignee: Red Hat, Inc.
    Inventors: Ji{hacek over (r)}í Locker, Luká{hacek over (s)} Petrovický
  • Patent number: 9043655
    Abstract: An apparatus includes a first memory, a second memory, a processor configured to perform an initialization process including adding data that generates a first error to initialization data and storing the initialization data together with the added data in the first memory to initialize the first memory, and a controller configured to perform an exchanging process including, when a second error occurs in the second memory during reading or writing data from or to the second memory, copying the data stored in the second memory into the first memory and switching, using a selector, a memory for use in writing and reading data from the second memory to the first memory. The processor is configured to read data from the first memory and the second memory and detect a failure of the selector or a failure of the exchanging process depending on whether the first error occurs or not.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 26, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Takahiko Kimura
  • Patent number: 9043643
    Abstract: A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David A. Elko, Steven N. Goss, Thomas C. Shaw
  • Patent number: 9037907
    Abstract: A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David A. Elko, Steven N. Goss, Thomas C. Shaw
  • Publication number: 20150100833
    Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.
    Type: Application
    Filed: April 23, 2014
    Publication date: April 9, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seong-hoon JEONG, Ho-young KIM, Soo-jung RYU
  • Publication number: 20150067406
    Abstract: Testing system includes a testing device and a testing circuit board connected to the testing device. The testing device includes a storing module, a transmit-receive module, and an analyzing module. A number of specification parameters of a fan module is stored in the storing module. The transmit-receive module sends a testing code to the testing circuit board. The testing circuit board responds to the testing code to detect a number of running information of the fan module, and sends the running information to the transmit-receive module. The analyzing module receives the number of running information from the transmit-receive module and compares the number of running information with the number of specification parameters for determining whether the fan is qualified. The disclosure further provides a testing method.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Inventor: KANG-BIN WANG
  • Patent number: 8972943
    Abstract: A method for debugging an application includes obtaining first and second fusible operation requests; if there is a break point between the first and the second operation request, generating a first set of compute kernels including programs corresponding to the first operation request, but not to the second operation request; and generating a second set of compute kernels including programs corresponding the second operation request, but not to the first operation request; if there is no break point between the first and the second operation request, generating a third set of compute kernels which include programs corresponding to a merge of the first and second operation requests; and arranging for execution of either the first and second, or the third set of compute kernels, further including debugging the first or second set of compute kernels when there is a break point set between the first and second operation requests.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 3, 2015
    Assignee: Google Inc.
    Inventors: Matthew N. Papakipos, Brian K. Grant, Christopher G Demetriou
  • Patent number: 8964779
    Abstract: An electronic controlling device and method is disclosed. One embodiment provides at least one module performing specific functions within one of a plurality of module modes on reception of a corresponding module mode request. A system control unit is provided to operate the at least module in one of a plurality of module modes by distributing a corresponding system mode request. The at least one module is adapted to translate the distributed system mode request to a module mode request which is configurable.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Harry Siebert
  • Publication number: 20150033082
    Abstract: Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC.
    Type: Application
    Filed: August 9, 2013
    Publication date: January 29, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Ryan Shirlen, Victor Wong
  • Patent number: 8935670
    Abstract: Embodiments of the present invention may provide “undo” (e.g., rollback) features, along with data management simplification features, to an update package model of software suite development/evolution. New functions, which may have disruption effects for customers, may be installed into the core configuration data with inactive switches. Upon activation, a switch status may change, and a query filter may use the activated function (e.g., as associated with the switch ID). Original functions may be maintained, giving the user the ability to deactivate an activated function, and thereby reverting the system back to the prior configuration status.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: January 13, 2015
    Assignee: SAP SE
    Inventors: Andreas Kemmler, Torsten Kamenz
  • Patent number: 8935578
    Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: James W. Alexander, Buck W. Gremel, Pinkesh J. Shah, Malay Trivedi, Mohan K. Nair
  • Patent number: 8896437
    Abstract: A system includes at least one sensor and an equipment health monitoring (EHM) unit. The at least one sensor is configured to measure one or more characteristics of an asset, where the asset includes a piece of equipment. The EHM unit includes at least one sensor interface configured to receive at least one input signal associated with the asset from the sensor(s). The EHM unit also includes at least one processing unit operable to be pre-configured to identify a specified fault in the asset using the input signals and an asset-specific model that includes a combination of standard subsystem models. The EHM unit further includes at least one output interface configured to provide an indicator identifying the fault. The standard subsystem models could include standardized fault models configured to identify faults for standard assets.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: November 25, 2014
    Assignee: Honeywell International Inc.
    Inventor: Rajat Sadana
  • Patent number: 8880323
    Abstract: A computer-implemented method includes obtaining road sensor data reflecting speeds of traffic on road segments, transforming the road sensor data using vehicle probe data for the road segments reflecting vehicle speeds, and producing speed estimates for the road segments using the transformed road sensor data. The method can further include determining speeds for road segments between road sensors by smoothing data from sensors near the road segments.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: November 4, 2014
    Assignee: Google Inc.
    Inventors: Ravi Jain, Samir Goel, Gregory Neverov
  • Patent number: 8874969
    Abstract: In one or more embodiments, a hit test thread which is separate from the main thread, e.g. the user interface thread, is utilized for hit testing on web content. Using a separate thread for hit testing can allow targets to be quickly ascertained. In cases where the appropriate response is handled by a separate thread, such as a manipulation thread that can be used for touch manipulations such as panning and pinch zooming, manipulation can occur without blocking on the main thread. This results in the response time that is consistently quick even on low-end hardware over a variety of scenarios.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: October 28, 2014
    Assignee: Microsoft Corporation
    Inventors: Matthew A. Rakow, Tony E. Schreiner, Bradley J. Litterell, Kevin M. Babbitt, Praveen Kumar Muralidhar Rao, Christian Fortini
  • Patent number: 8868975
    Abstract: A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ralph E. Bellofatto, Steven M. Douskey, Rudolf A. Haring, Moyra K. McManus, Martin Ohmacht, Dietmar Schmunkamp, Krishnan Sugavanam, Bryan J. Weatherford
  • Publication number: 20140281735
    Abstract: A method and apparatus for an asynchronous multicore common debugging system is described. Debug signals from a plurality of processor cores are synchronized to a common timing domain. Processing completed within the plurality of processor cores during a common timing interval is tracked. A single debugging tool chain is utilized to provide debugging results in response to the tracking the processing completed within the plurality of processor cores during the common timing interval.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Michael L. Olivarez, Stephen J. Benzel, Robert N. Ehrlich, Robert A. McGowan
  • Patent number: 8819488
    Abstract: One or more computers is configured to run an end-to-end test including at least a plurality of independent tests of multiple stages of an asynchronous multi-stage data processing system. One of the set of independent tests is configured to send a request for test input data from a test data repository service for a particular stage. A converted version of the test input data is obtained. A comparison of the converted version to the output of the particular stage to verify operation of the particular stage is obtained. The output of the particular stage is transmitted to the test data repository service. One or more computers is configured to provide the test data repository service. The test data repository service is configured to store in the test data storage the output of the particular stage as test input data for a next stage of the asynchronous multi-stage data processing system.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: August 26, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Carlos Arguelles
  • Patent number: 8788885
    Abstract: A test device may include an application that accesses online content. In some examples, a test intermediary and/or a test user interface (UI) are downloaded to the test device in response to a request by the application for obtaining the content from a network location. The test intermediary may be positioned to receive communications between the application and the content during testing of the content and/or the application. For example, the test intermediary may intercept metrics and other callbacks passed between the content and the application during manual or automated testing. In some instances, the test intermediary may provide the metrics and/or other test outputs for display in the test user UI rendered on the test device. The content may be rendered to be functional within the test UI, and the existence of the test intermediary and/or the test UI may be transparent to the application and the content.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 22, 2014
    Assignee: Amazon Technologies, Inc.
    Inventors: James M. Cook, Daniel Thomas Tattersall, Te-Lin Tuan
  • Publication number: 20140201575
    Abstract: Systems and methods to test processor cores of a multi-core processor microchip are provided. Comparison circuitry may be configured to compare data output from processor cores of a microchip. An encoding module may be configured to encode received data by initially assigning binary bit values to the processor cores. Based on at least one of a number of the processor cores and a first binary bit value, a first additional binary bit may be added to the first binary bit value. The first binary bit value may be assigned to a first processor core of the plurality of processor cores.
    Type: Application
    Filed: January 11, 2013
    Publication date: July 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Dennis M. Rickert