Bus, I/o Channel, Or Network Path Component Fault Patents (Class 714/43)
  • Patent number: 8627139
    Abstract: A method, a recording terminal, a server, and a system for repairing media file recording errors are disclosed in embodiments of the present invention. The method includes: generating description information about a recording error when a recording terminal identifies the recording error in live recording of a media file; sending a recording error repair request that carries the description information to a network device; and repairing the media file recorded by the recording terminal according to repair information when receiving the repair information sent by the network device according to the description information. With the present invention, the recording errors are repaired through a bidirectional network between the recording terminal and the network device, and reliability of repairing the recording errors is ensured.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: January 7, 2014
    Assignee: Huawei Device Co., Ltd.
    Inventor: Yunsong Fan
  • Patent number: 8621283
    Abstract: A method includes instantiating a cloned network that includes a second set of virtual service nodes. The second set of virtual service nodes includes at least one cloned virtual service node that is a clone of a corresponding virtual service node in a first set of virtual service nodes. The at least one cloned virtual service node has access to a history of events that occurred at the corresponding virtual service node in the first set of virtual service nodes. The method includes initiating an interactive debugging session that includes processing of the events of the history of events.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 31, 2013
    Assignee: AT&T Intellectual Property, I, L.P.
    Inventors: Jacobus Van Der Merwe, Matthew Chapman Caesar, Chia-Chi Lin
  • Patent number: 8615686
    Abstract: A method and system for managing performance over a multimedia content distribution network (MCDN), such as a digital subscriber line network, involves accessing a record of historical values of a network service parameter for a plurality of MCDN clients. The historical values may be analyzed to detect network impairment associated with an MCDN node. Network diagnostics may be initiated for MCDN clients associated with the MCDN node. The result of the network diagnostics may result in localizing a source of the network impairment.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: December 24, 2013
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: James Gordon Beattie, Jr., Stephen J. Griesmer, Edward Marsh
  • Patent number: 8612969
    Abstract: An electronic apparatus is provided that can include a first downloader downloading a replacement control program from an external host computer by way of a first communicator under the control of a first communication program, in a case where a first inspector judges a control program is not normal and a second inspector judges the first communication program is normal. The apparatus can also include a second downloader downloading a replacement first communication program from an external maintenance computer by way of a second communicator under the control of a second communication program, in a case where a second inspector judges the first communication program is not normal, so that a first communication program stored in a rewritable flash ROM is rewritten with the replacement first communication program downloaded by the second downloader.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 17, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Shuichi Nakano, Minoru Takizawa
  • Patent number: 8607113
    Abstract: A data processing apparatus capable of efficiently collecting information useful for network failure analysis. If image data transmission to a host computer has failed, a packet acquisition start instruction is given from a data transmission control unit to a packet acquisition control unit. Subsequently, image data is retransmitted to the host computer. After completion of the image data retransmission, a packet acquisition termination instruction is given to the packet acquisition control unit.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: December 10, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadahiro Nakamura
  • Publication number: 20130326280
    Abstract: Embodiments of the present invention provide a debugging method, a chip, a board, and a system and relate to the communications field. Remote debugging can be performed on a board having no main control CPU without affecting hardware distribution and software performance. The method includes: receiving, by an Ethernet port, a data packet and determining a current service type according to a service identifier carried in the data packet; when determining the current service type is a debugging service, writing the data packet into a memory through a bus and sending an interruption notification to a CPU through the bus; reading, by the CPU, the data packet from the memory according to the interruption notification, obtaining a debugging instruction by parsing the data packet, and sending the debugging instruction to an ASIC through a protocol conversion module.
    Type: Application
    Filed: May 21, 2013
    Publication date: December 5, 2013
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Jieming Dong, Weihua Li
  • Patent number: 8595547
    Abstract: Replicated instances in a database environment provide for automatic failover and recovery. A monitoring component can periodically communicate with a primary and a secondary replica for an instance, with each capable of residing in a separate data zone or geographic location to provide a level of reliability and availability. A database running on the primary instance can have information synchronously replicated to the secondary replica at a block level, such that the primary and secondary replicas are in sync. In the event that the monitoring component is not able to communicate with one of the replicas, the monitoring component can attempt to determine whether those replicas can communicate with each other, as well as whether the replicas have the same data generation version. Depending on the state information, the monitoring component can automatically perform a recovery operation, such as to failover to the secondary replica or perform secondary replica recovery.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 26, 2013
    Assignee: Amazon Technologies, Inc.
    Inventors: Swaminathan Sivasubramanian, Grant Alexander MacDonald McAlister
  • Patent number: 8595557
    Abstract: A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eric Jasinski, Michael Richard Ouellette, Jeremy Paul Rowland
  • Patent number: 8595453
    Abstract: Availability of an information system including a storage apparatus and a host computer is improved. A host system includes a first storage apparatus provided with a first volume for storing data, and a second storage apparatus for storing the data sent from the first storage apparatus. In case of a failure occurring in the first storage apparatus, the host sends the data to be sent to the first storage apparatus to the second storage apparatus.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: November 26, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Iwamura, Kenta Ninose, Yoshiaki Eguchi, Yasuo Watanabe, Hisao Homma, Yasutomo Yamamoto
  • Patent number: 8589841
    Abstract: A method, apparatus and computer program product for automatic parity check identification. The method comprising: automatically identifying a parity signal in a circuit design, wherein the parity signal is defined as a parity function of a set of support signals, wherein the automatic identification comprises: obtaining a candidate parity signal and a corresponding set of candidate support signals; and verifying that a bit flip in exactly one of any of the corresponding candidate set of support signals induces a bit flip on a value of the candidate parity signal; wherein said method further comprises reporting the automatically identified parity signal.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eli Arbel, Sergey Novimov, Karen Yorav
  • Publication number: 20130297976
    Abstract: Scalable means are provided for diagnosing the health of a parallel system comprising multiple nodes interconnected using one or more switching networks. The node pings other nodes via different paths at regular intervals. If more than a threshold number of pings are missed from a node, the system performs fault detection by entering a freeze state in which nodes do not send or receive any messages except ping messages. If ping messages still fail to reach destination nodes, the parallel system identifies faulty components that are causing ping messages to fail. Once the faulty component is identified, the parallel system is unfrozen by allowing nodes to communicate all messages. If redundant computers and/or switches are present, the parallel system is automatically reconfigured to avoid the faulty components.
    Type: Application
    Filed: March 7, 2013
    Publication date: November 7, 2013
    Inventor: Robert J. McMillen
  • Patent number: 8564466
    Abstract: To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: October 22, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masaru Hoshikawa, Shigeaki Takase
  • Patent number: 8566649
    Abstract: A network including a plurality of ports configured to exchange frames of data and a forwarding engine. The forwarding engine is configured to transfer the frames of data among the ports. Each frame of data includes an identifier that identifies a destination to which the frame is to be transferred by the forwarding engine. A first port of the plurality of ports includes a register configured to store an identifier of a backup port to be used in response to a failure of the first port, the backup port being among the plurality of port, and a redirect port. The redirect circuit is configured to, in response to the failure of the first port, replace the identifier in each frame of data identifying the first port as the destination port with the identifier of the backup port. Each frame having a replaced identifier is subsequently forwarded to the backup port.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: October 22, 2013
    Assignee: Marvell International Ltd.
    Inventor: Nafea Bishara
  • Patent number: 8566682
    Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Luis A. Lastras-Montano, Patrick J. Meaney, Lisa C. Gower
  • Patent number: 8560883
    Abstract: Storage arrangements including copy information holding correspondence of copy pairs formed from first and second and from first and third logical volumes, as copy groups concerned with a sequence of write data in the computer; and path remote copy relevant information indicating, for each copy group, correspondence of: logical paths; physical paths including the first, second and third storage ports; and take-over path information concerning a relevant path between the second and third logical volumes, needed for the take-over copy pair to take-over the remote copying when failure occurs in the first storage system, and wherein when the management system receives failure information designating a certain path indicated within the take-over path information, a management system determines and displays, by referring to the path remote copy relevant information, copy groups affected by the failure of the certain path.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 15, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Maki, Hiroshi Yamamoto
  • Patent number: 8560878
    Abstract: Reduction of data processing capacity attributable to the occurrence of a failure is prevented by promptly identifying the failure location. A storage apparatus includes a plurality of expanders connected to storage media storing data sent from a host system, and a controller for controlling the expanders, wherein the controller sends a failure detection command to the plurality of expanders; the plurality of expanders store the command in their own storage units; and if one expander from among the plurality of expanders detects a failure in another expander immediately following and connected to the one expander, the one expander reads the command stored in a storage unit for the one expander and sends a response including failure detection information corresponding to the command to the controller.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 15, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Koji Washiya, Tsutomu Koga, Nobuyuki Minowa
  • Patent number: 8549643
    Abstract: A computing device executing a data loss prevention (DLP) system tracks bait data on at least one of the computing device or a network. The DLP system identifies a potential security threat in response to detecting unscripted activity associated with the bait data. The DLP system performs an action in response to identifying the potential security threat.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: October 1, 2013
    Assignee: Symantec Corporation
    Inventor: Darren Shou
  • Patent number: 8549361
    Abstract: System and method for construction, fault isolation, and recovery of cabling topology in a storage area network (SAN) is disclosed. In one embodiment, in a method for construction, fault isolation, and recovery of cabling topology in a SAN, subsystem information associated with each subsystem in the SAN is obtained. Then, an IP port and zoning information associated with connections of each subsystem is obtained. Component information associated with each component is also obtained. Any other relevant information associated with each subsystem and each component is obtained from users. The obtained subsystem information, IP port and zoning information, component information, and any other relevant information are compiled. Test packets are then sent from end-to-end in SAN using compiled information. The sent test packets are tracked via each component in each subsystem in the SAN. The cabling topology of the SAN is then outputted based on the outcome of the tracking.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: October 1, 2013
    Assignee: Netapp, Inc.
    Inventors: Britto Rossario, Mahmoud K Jibbe
  • Patent number: 8539318
    Abstract: In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 17, 2013
    Assignee: École Polytechnique Fédérale de Lausanne (EPFL)
    Inventors: Harm Cronie, Amin Shokrollahi
  • Publication number: 20130238942
    Abstract: A port test device for a motherboard includes a conversion member and a test apparatus. The motherboard comprising a serial attached small computer system interface (SAS) port and a serial advanced technology attachment (SATA) port. The conversion member includes a SAS connector and a SATA connector, the SATA connector is coupled to the SATA port, and is electronically connected to the SAS port. The test apparatus is selectively coupled to the SAS port or the SAS connector.
    Type: Application
    Filed: February 22, 2013
    Publication date: September 12, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: BO YANG, YOU-LIANG MA, TAI-CHEN WANG
  • Patent number: 8527815
    Abstract: A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: September 3, 2013
    Assignee: LSI Corporation
    Inventors: Jeffrey K. Whitt, Sreedeepti Reddy, Edoardo Daelli, Brandon L. Hunt
  • Patent number: 8522075
    Abstract: According to an aspect of an embodiment, a storage apparatus comprising; a pair of control devices for controlling storage devices, each control device being connected with another control device; storage devices for storing data; switches being connected with the plurality of storage devices, the switches being connected between the control devices in series; wherein the control device for controlling the plurality of switches according to a process including detecting a fault in the connection of the switches, and; controlling the control devices to access the storage devices via the switches such that one of the control devices accesses a part of the storage devices via a part of the switches located between the one of the control devices and the fault, and the other of the control devices accesses remainder of the storage devices via remainder of the switches, respectively.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: August 27, 2013
    Assignee: Fujitsu Limited
    Inventor: Tomoya Makino
  • Patent number: 8522111
    Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: August 27, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Pradeep Sindhu, Srihari Vegesna
  • Patent number: 8516311
    Abstract: A method tests peripheral component interconnect express (PCI-E) switches. A second PCI-E switch to be tested electronically connects to a first PCI-E switch of a computing device. A first data packet is created by the computing device and sent from the first PCI-E switch to the second PCI-E switch. A second data packet sent back by the second PCI-E switch is received by the computing device. The second PCI-E switch works normally if the first data packet is identical to the second data packet. The second PCI-E switch does not work normally if the first data packet is not identical to the second data packet.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 20, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chao-Tsung Fan
  • Patent number: 8510593
    Abstract: A control apparatus includes a lower layer control unit configured to perform control of a load, an upper layer control unit configured to control the lower layer control unit, a communication unit configured to perform communication between the upper layer control unit and the lower layer control unit via a communication line, a detection unit configured to detect power supply voltage of the lower layer control unit, wherein the upper layer control unit detects communication abnormality of the communication unit and notifies the communication abnormality, the upper layer control unit notifying abnormality of power supply voltage of the lower layer control unit, in such a manner as to be identified from the communication abnormality of the communication unit.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: August 13, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Noriaki Adachi
  • Patent number: 8510607
    Abstract: A method for resetting and reenumerating a Universal Serial Bus (USB) device, an Electrical Fast Transient/Burst (EFTB) unit of a USB device for resetting and reenumerating the USB device and a USB device are described. In one embodiment, a method for resetting and reenumerating a USB device involves detecting a USB reset command from a host device at a USB device, setting a reset flag in the USB device in response to the detecting of the USB reset command, determining if the USB device is in a corrupted state in response to the reset flag, and causing a Single Ended Zero (SE0) signal to be issued to reset the USB device out of the corrupted state and reenumerate the USB device back to the host device if the USB device is determined to be in the corrupted state. Other embodiments are also described.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: August 13, 2013
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Rizal Jaffar, Kwai Lee Pang, Kevin Len-Li Lim
  • Patent number: 8510606
    Abstract: A method for maintaining reliable communication between a command initiator and a target device is provided. After the command initiator detects an error corresponding to the target device and a path between the command initiator and the target device, the command initiator performs a downshift evaluation. The initiator maintains a transmission speed if the downshift evaluation determines that forgoing a transmission speed downshift is required, and reduces the transmission speed if the downshift evaluation determines that transmission speed downshift is required. The command initiator then logs the downshift evaluation result and reports any transmission speed change to a user.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: August 13, 2013
    Inventors: Randolph Eric Wight, Ruiling Luo, Clive Scott Oldfield
  • Patent number: 8510479
    Abstract: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 13, 2013
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Michael D. Apel, Steve Dienstbier
  • Publication number: 20130191692
    Abstract: An approach is disclosed for performing initialization operations for a graphics processing unit (GPU). The approach includes detecting errors while performing one or more initialization operations. Further, the approach includes releasing a holdoff on a communication link that couples the GPU to a memory bridge and causing debug output to be displayed to a user that indicates the error.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 25, 2013
    Inventors: Lincoln GARLICK, Saket JAMKAR, Steven MUELLER
  • Patent number: 8495176
    Abstract: A content management system (CMS) includes a value-add application with a first set of XML content services, one or more dedicated XML processing servers with a second and other sets of XML content services, and a core CMS with a third set of XML content services. The content management system may be designed to provide XML content services at any of these three tiers of processing. A first threshold is defined that allows the value-add application to determine when to offload XML content services to a dedicated XML processing server. A second threshold is defined that allows the core CMS to determine when to offload XML content services to a dedicated XML processing server. Callback services are included that allow each tier of XML content services to send or receive additional information to complete the XML processing. The result is a content management system that is very powerful and flexible.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: David G. Herbeck, John E. Petri
  • Patent number: 8495421
    Abstract: The invention relates to a method for packet-switching transmission of media data and a device for processing media data. Media data may be video, audio or text data, or other data. Transmission of the data is usually effected according to a streaming method. The data is therein transmitted in packets and re-assembled in the receiving device. For Internet applications, the real-time transport protocol is very widely used in the transmission of data streams. However, this data transmission protocol does not enable a secure transmission which is based on a repetition of the defectively transmitted data. Sequence counters are used according to this protocol so that left-out data packets can be detected in the receiving device.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: July 23, 2013
    Assignee: Thomson Licensing
    Inventors: Frank Glaeser, Andreas Matthias Aust
  • Patent number: 8495344
    Abstract: A multi-core microprocessor includes first and second processing cores and a bus coupling the first and second processing cores. The bus conveys messages between the first and second processing cores. The cores are configured such that: the first core stops executing user instructions and interrupts the second core via the bus, in response to detecting a predetermined event; the second core stops executing user instructions, in response to being interrupted by the first core; each core outputs its state after it stops executing user instructions; and each core waits to begin fetching and executing user instructions until it receives a notification from the other core via the bus that the other core is ready to begin fetching and executing user instructions. In one embodiment, the predetermined event comprises detecting that the first core has retired a predetermined number of instructions. In one embodiment, microcode waits for the notification.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: July 23, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Jui-Shuan Chen
  • Patent number: 8489917
    Abstract: Storage arrangements including copy information holding correspondence of copy pairs formed from first and second and from first and third logical volumes, as copy groups concerned with a sequence of write data in the computer; and path remote copy relevant information indicating, for each copy group, correspondence of: logical paths; physical paths including the first, second and third storage ports; and take-over path information concerning a relevant path between the second and third logical volumes, needed for the take-over copy pair to take-over the remote copying when failure occurs in the first storage system, and wherein when the management system receives failure information designating a certain path indicated within the take-over path information, a management system determines and displays, by referring to the path remote copy relevant information, copy groups affected by the failure of the certain path.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: July 16, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Maki, Hiroshi Yamamoto
  • Patent number: 8484515
    Abstract: A computer-implemented method, executable software product, and system for performing a test of an audio/video playback device are described. The audio/video playback device includes at least one main processor, interfaces, and additional processors. The main processor(s) communicate with the additional processors through the interfaces. The method, software product, and system include monitoring at least part of the interfaces for communications between the main processor(s) and the additional processors. The method, system and software product also include storing the communications in a raw format during the test. The method, software product and system also include translating the communications from the raw format to human-readable format after the test concludes and displaying the human-readable format of the communications. In some aspects, the method and system also include reading and storing run time data during the test such that the reading and storing is Heisenberg-friendly.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: July 9, 2013
    Assignee: Sigma Designs, Inc.
    Inventor: Glen A. Adams
  • Patent number: 8484504
    Abstract: A system that incorporates teachings of the present disclosure may include, for example, an edge device having a controller to receive a Session Initiation Protocol (SIP) message from a user endpoint device (UE) requesting communication services, forward the SIP message to a network element of a Server Office, receive from the network element a first error message indicating communication services at the Server Office are unavailable, replace the first error message with a second error message, the second error message indicating a temporary unavailability of communication services, and transmit the second error message to the UE. Additional embodiments are disclosed.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: July 9, 2013
    Assignee: AT&T Intellectual Property I, LP
    Inventors: Chaoxin Qiu, Robert F. Dailey, Satish Parolkar
  • Patent number: 8478900
    Abstract: Connection of an electronic device to a particular port of the network device is detected. It is determined based on zone information whether a misconnection has occurred. The zone information defines plural zones.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 2, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lijun Qin, Balaji Natrajan, Sohail Hameed
  • Patent number: 8473275
    Abstract: A method for emulating and debugging a microcontroller is described. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: June 25, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Manfred Bartz, Craig Nemecek, Matt Pleis
  • Patent number: 8473788
    Abstract: A method for a computer, which is configured to access to hierarchical information indicating a hierarchical structure relating to processes executed by devices included in a network, includes receiving abnormal observation data from the network, detecting a transmission source device of the abnormal observation data and a process by which the abnormal observation data is issued, specifying a process relating, to the detected process in accordance with a kind of the detected transmission source device by referring to the hierarchical information, determining, by the computer, a failure occurrence point based on a status of the specified process.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: June 25, 2013
    Assignee: Fujitsu Limited
    Inventor: Taketoshi Yoshida
  • Patent number: 8473779
    Abstract: Systems and methods for recovering from a fault in an array of data storage devices are provided. Fault recovery includes determining that a first data storage device of the array of data storage devices is more likely to fail that other storage devices of the array of data storage devices. A second data storage device in the array of data storage devices is selected to be used in recovering from a failure of the first data storage device. Data from the first data storage device is stored at the second storage device. In the event of a failure at the first data storage device, data storage operations are performed using the second storage device.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: June 25, 2013
    Assignee: Assurance Software and Hardware Solutions, LLC
    Inventors: Samuel Burk Siewert, Phillip Clark, Lars E. Boehnke
  • Patent number: 8458527
    Abstract: A method for maintaining reliable communication on a bidirectional communication link is provided. A receiver on the bidirectional communication link detects an error and maintains a count of detected errors. The transmitter on the bidirectional communication link polls the receiver in order to determine the count of detected errors, and performs a downshift evaluation for the bidirectional communication link. In response to performing the downshift evaluation for the bidirectional communication link, the transmitter maintains a transmission speed of the bidirectional communication link if the downshift evaluation determines that forgoing transmission speed downshift is required for the bidirectional communication link, and reduces the transmission speed of the path if the downshift evaluation determines that transmission speed downshift is required for the bidirectional communication link.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: June 4, 2013
    Assignee: Dot Hill Systems Corporation
    Inventors: Clive Scott Oldfield, Tony Richard Kilwein, Mark Aaron VonLintel
  • Patent number: 8458528
    Abstract: Disclosed is a method and system for transmitting data on a data channel from a source to a destination. The data channel has a plurality of wavelength channels and a throughput. The system and method include a storage application for multicasting data on each of the plurality of wavelength channels, a storage protocol extension device using buffer credits to adjust the throughput during the multicasting, and an application optimization device for managing data channel latency to achieve asymmetric mirroring behavior at the same time as the multicasting.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: June 4, 2013
    Assignee: AT&T Intellectual Property II, L.P.
    Inventor: James A. Gardner
  • Patent number: 8458510
    Abstract: Various embodiments for automated error recovery in a computing storage environment by a processor device are provided. In one embodiment, pursuant to performing one of creating a new and rebuilding an existing logical partition (LPAR) operable in the computing storage environment by a hardware management console (HMC) in communication with the LPAR, at least one failure scenario is evaluated by identifying error code. If a failure is caused by an operation of the HMC and a malfunction of a current network connection, a cleanup operation is performed on at least a portion of a current HMC configuration, an alternative network connection to the current network connection is made, and a retry operation is performed.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Xu Han, Edward Hsiu-Wei Lin, Yang Liu
  • Patent number: 8458529
    Abstract: Various embodiments include one or more of systems, methods, and software to provide a status of a logical entity between entity models in network management systems, such as for fault isolation, in an efficient manner. Some embodiments, when receiving requests for a status of a logical entity while already in the process of determining the status in response to a previously received request, include adding an identifier of the subsequent requestor to a status requestor list and not responding to or taking any further action with regard to the request from the subsequent requestor until the status in response to the first received status request is determined.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: June 4, 2013
    Assignee: CA, Inc.
    Inventors: Timothy J. Pirozzi, Christopher Burke
  • Publication number: 20130139005
    Abstract: A Universal Serial Bus (USB) testing apparatus includes a Central Processing Unit (CPU); a Southbridge; a Baseboard Management Controller (BMC), connected with the Southbridge via USB. The BMC determines if a test starts or finishes, generates a first instruction of creating a virtual control computer when determining the test starts, creates a control module and a comparing module in a memory unit which are running to become the virtual control computer, and connects the memory unit with the BMC according to the first instruction. The control module sends control data to the CPU. The comparing module obtains feedback data from the CPU and compares the control data with the obtained data to determine if the control data is consistent with the obtained data, thereby determining whether the USB is working normally.
    Type: Application
    Filed: December 14, 2011
    Publication date: May 30, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventor: YU-GANG ZHANG
  • Patent number: 8453016
    Abstract: Methods for managing response data within an information handling system (IHS), where the method includes the step of obtaining response data from at least one component in the IHS, the response data generated in response to receiving a command. The method also includes accumulating the response data from the at least one component to compute a total response time.
    Type: Grant
    Filed: September 23, 2007
    Date of Patent: May 28, 2013
    Assignee: Dell Products L.P.
    Inventor: William F. Sauber
  • Patent number: 8448013
    Abstract: A method, apparatus, and computer program product for handling a failure condition in a storage controller is disclosed. In certain embodiments, a method may include initially detecting a failure condition in a storage controller. The failure condition may be associated with a specific host and a specific storage device connected to the storage controller. The method may further include determining a failure ID associated with the failure condition. Using the failure ID, en entry may be located in a data collection and recovery table. This entry may indicate one or more data collection and/or recovery processes to execute in response to the failure condition. The method may then execute the data collection and/or recovery processes indicated in the entry. While executing the data collection and/or recovery processes, connectivity may be maintained between hosts and storage devices not associated with the failure condition.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brian Dow Clark, Juan Alonso Coronado, Christina Ann Lara, Lisa R. Martinez, Phu Nguyen, Beth Ann Peterson, Jayson Elliott Tsingine
  • Patent number: 8443239
    Abstract: The invention provides a highly resilient network infrastructure that provides connectivity between a main network such as the Internet and a subnetwork such as a server-based (e.g., web server) local area network. In accordance with the invention, a network interface incorporated into a server hosting center provides a resilient architecture that achieves redundancy in each of three different layers of the Open System Interconnect (OSI) stack protocol (i.e., physical interface, data link, and network layers). For every network device that is active as a primary communication tool for a group of subnetworks, the same device is a backup for another group of subnetworks. Based on the same connection-oriented switching technology (e.g., asynchronous transfer mode (ATM)) found in high-speed, broadband Internet backbones such as that provided by InternetMCI, the network interface architecture provides a high degree of resiliency, reliability and scalability.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: May 14, 2013
    Assignee: Verizon Business Global LLC
    Inventor: Kaustubh Phaltankar
  • Patent number: 8443238
    Abstract: A method tests hard disk ports located on a motherboard of a computing device. Each of the hard disk ports connects to a respective serial port of a test fixture. The test fixture includes a group of serial ports, a multiplexer and a storage device. Each of the hard disk ports is selected to be tested during the process of hard disk ports test. A data transmission path is formed by building a connection between the storage device and a channel of the multiplexer corresponding to the hard disk port. Data are written to the storage device and read from the storage device through the data transmission path. The hard disk port is working normal if the written data are identical to the read data. The hard disk port is not working normally if the written data are not identical to the read data.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: May 14, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Ming-Xiang Hu, Ming-Shiu Ou Yang, Jun-Min Chen, Ge-Xin Zeng, Shuang Peng
  • Patent number: 8443237
    Abstract: An objective is to allow a storage apparatus to accurately locate a failure site upon occurrence of a failure. Provided is a storage apparatus 10 including: a controller 11 that performs data input and data output into and from a storage drive 171 in response to a data input/output request sent from an external device 2; and expanders 112, 121 each having a switch circuit 1122 provided with a physical port (Phy 1121). In this storage apparatus 10, the controller 11 performs a loopback diagnosis on the expanders 112, 121, and performs a connection-based diagnosis on a target device by sending a connection frame thereto, the target device being a device detected as having a failure. When a response to the connection frame includes information indicating a failure, the controller 11 disables the physical port to which the target device is coupled, or the physical port of the switch circuit 1121 existing on a path from the controller 11 to the target device.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: May 14, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Konishi, Hiroshi Izuta, Hiroyoshi Suzuki
  • Patent number: 8443117
    Abstract: A connection expansion device connected to devices includes a plurality of ports to which devices are connected, a storage unit configured to record device information obtained from each port, and a processing unit configured to specify, based on the device information, a port in which an abnormal device exists, invalidate device information belonging to the port, and cause the storage unit to hold device information of a normal device.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: May 14, 2013
    Assignee: Fujitsu Limited
    Inventors: Atsushi Katano, Atsuhiro Otaka, Nobuyuki Honjo