Abstract: A method of interleaving blocks of indexed data of varying lengths is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

Abstract: A digital broadcasting system and a method of processing data are disclosed, which are robust to error when mobile service data are transmitted. To this end, additional encoding is performed for the mobile service data, whereby it is possible to strongly cope with fast channel change while giving robustness to the mobile service data.

Abstract: A transmitter device that repeatedly transmits an identical frame includes a circuitry that generates the frame and transmits the frame a plurality of times. The frame includes marking areas that divide the frame into a plurality of frame segments having different lengths. The marking area is formed in the frame by part of the frame and is distinguishable from other parts of the frame. The marking area does not change data content transmitted by the frame. The frame segments obtained from the identical frame that is repeatedly transmitted by the circuitry are combined to reconstruct a complete frame identical to the frame transmitted by the transmitter device.

Abstract: A hierarchical cyclic redundancy check (CRC) is provided that enables CRC appending and detection. A message that includes a first message portion and a second message portion is transmitted to two or more receivers. The receivers are not aware of the first message portion. One of the receivers can be aware of the second message portion of the message. Each portion of the message can be encoded with a CRC in order to provide protection. The receiver that is aware of the second message portion is provided a higher level of cyclic redundancy check (CRC) protection than the receivers that are not aware of the second message portions.

Abstract: Techniques involving failure management of storage devices are described. One representative technique includes encoding data to enable it to be stored in a storage block that includes at least one storage failure. The data is encoded such that it traverses the storage failures when stored in the storage block. When it is determined that a storage access request has requested the data stored in a storage block having such failures, the data is decoded to restore it to its original form.

Abstract: A data converting method includes counting for each bit pattern among bit patterns that a data segment of a specific number of bits can assume, the number of data segments that have the bit pattern, where the data segments are segments of write_data written to a storage medium storing two types of bit values among which a first value has a higher error occurrence rate than a second value; correlating a bit pattern selected as a conversion source pattern, from among the bit patterns in descending order of count results, with a bit pattern selected as a conversion target pattern, from among the bit patterns in descending order of quantities of the second value respectively included in the bit patterns; and converting for each conversion source bit pattern, data segments having the conversion source bit pattern, into converted data segments having the correlated conversion target bit pattern.

Abstract: A memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. The memory system accesses blocks of data, each block including an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R?S inner checkbits and S spare bits, and (3) C-2 data-bit columns containing data bits. Each column is stored in a different memory component. When the memory system determines that a memory component has failed, the memory system examines the pattern of errors associated with the failed component to determine if the failure affects a partial component associated with S or fewer bits. If so, the memory system corrects and remaps data bits from the failed partial component to the S spare data bits in the inner-checkbit column.

Abstract: In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing.

Abstract: An error correction encoding device includes an outer encoding circuit that performs encoding processing for an outer code and an inner encoding circuit that performs encoding processing for an inner code. The inner encoding circuit includes an inner-encoding input circuit that performs interleaving processing in which a parallel input sequence is divided into lanes and in which a barrel shift is performed for each inner frame in the lanes. Thus, allocation ratios between an information sequence area and a parity sequence area are made uniform.

Abstract: Method and apparatus for writing data to be stored to a predetermined memory area, the method comprising: reading stored data from the predetermined memory area, the stored data comprising a stored data block and an associated stored error detection value, manipulating, after reading the stored data, at least one of the stored data block and the associated stored error detection value in the predetermined memory area, and writing, after manipulating, the data to be stored to the predetermined memory area.

Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.

Abstract: An error correction apparatus comprises an input for receiving data. The received data includes error-check data. The apparatus also includes a processing resource arranged to calculate parity check data. A data store is coupled to the processing resource for storing look-up data for identifying, when in use, a location of an error in the received data. The look-up data is a compressed form of indexed error location data.

Abstract: The error correction capability of block codes can be doubled if error locations are known. Prior art approaches for error location detection always involve adding dedicated redundant data which then are evaluated to yield error location information. The present invention proposes and describes how error location information in the form of clues is derived from given DC control bits that are anyway present in a data stream.

Abstract: This invention relates to a receiver circuit which comprises an equalizer (27) and an error decorrelator (25). The error decorrelator being configured for changing (501; 601, 602) the position of symbols. The invention further relates to a corresponding method. This invention finally relates to an interleaving or deinterleaving method which comprises selecting a first number of symbols (204; 302) within a stream of digital data (13; 28) thereby obtaining selected symbols. The method further comprises exchanging (601, 602) the position of at least half of said first number of symbols of said selected symbols with the position of other symbols from said selected symbols. The invention further relates to an interleaving or deinterleaving circuit.

Abstract: An error correction encoding device is provided that combines redundancy data with source data, said device including: at least three encoding stages and at least two permutation stages. Each encoding stage implements at least one set of three basic encoding modules, in which a first encoding stage receives said source data and a last encoding stage provides said redundancy data. Each encoding module implements a basic code and includes c inputs and c outputs, c being an integer. The permutation stages are inserted between two consecutive encoding stages and each permutation stage implements a c-cyclic permutation.

Abstract: A method for transmitting control information in a wireless communication system is provided. A codeword is generated by performing forward error correction (FEC) encoding on control information to generate. An interleaved code is generated by interleaving the codeword. A combined code is generated by combining the codeword and the interleaved code. A transport block is generated by repeating the combined code and is transmitted.

Abstract: An interleaver provision method for providing a continuous length, an interleaving method, and a turbo-encoder thereof are disclosed. The interleaving method selects a basic interleaver having a proper length from among the basic interleaver set, which is predetermined to have the length represented by a multiple of the ARP fluctuation vector period. The interleaving method performs the dummy insertion and the pruning process to have the length acting as the basic-interleaver length, so that it can provide the ARP interleaver having a continuous length.

Abstract: A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.

Abstract: A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N?M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.

Abstract: In one embodiment, a method for testing adjustment and configuration is disclosed. The method can include accessing source code of a test framework that is configured for testing a module, creating a configuration folder having a property override for a test suite for the module testing, determining a source root folder for the test suite, starting the test framework by passing in an identifier for the test suite, and adding a custom test to the source root folder using the configuration folder to customize the test suite. The method can further include compiling the test framework with each of the plurality of test folders enabled. The method also may use a refactoring tool to make changes in a file within the test framework.

Abstract: A data encoding circuit and a corresponding method is provided. The data encoding circuit includes a first data formatter in communication with an encoder section. The first data formatter is configured to receive blocks of source data in serial and output parallel two dimensional source data. The encoder receives the parallel two dimensional source data and that computes a plurality of serial row parity bits and a plurality of parallel column parity bits of an error correcting code from the parallel two dimensional source data. A second data formatter communicates with the encoder section and receives the parallel column parity bits and outputs serial column parity bits. A multiplexer section multiplexes the blocks of source data, the serial row parity bits, and the serial column parity bits into an output stream including the blocks of source data encoded by the error correcting code.

Abstract: A data reception device that receives scrambled and transmission data as received data and that descrambles and outputs the data after adjusting the timing with the transmitter has a descramble circuit 10 detect timing adjustment data included in a timing adjustment data set that adjusts the timing with the transmitter in the data which the descramble circuit 10 has not descrambled, and comprises an LFSR suspending signal generation circuit 9 that outputs a required number of LFSR suspending signals, after first normal timing adjustment data has been received, at the output timing of data received thereafter so as to simulate a situation as if a desired number of timing adjustment data included in the timing adjustment data set were received.

Abstract: Provided are a method and apparatus using a frequency selective baseband. Symbol-error correction modulation and demodulation is performed by generating a plurality of subgroups by dividing 2N spread codes or orthogonal codes used for frequency spreading into 2M (M<N) spread codes or orthogonal codes; selecting (P+L) subgroups; acquiring P spread codes by inputting M data bits to each of the selected P subgroups to select one spread code among the 2M spread codes of each subgroup; generating L*M parity bits for symbol error correction using P*M data bits inputted to the selected P subgroups; selecting one spread code among the 2M spread codes of the L subgroups by inputting the L*M parity bits to the L subgroups; and selecting the dominant values among the (P+L) spread codes acquired from the (P+L) subgroups to generate transmitting data including the dominant values, where N, M, P, and L are real numbers.

Abstract: In a data transmission network, such as a passive optical network, the consecutive identical digit (CID) handling requirements may be reduced by providing a CID monitoring module at the transmitter end that monitors the number of CIDs in a transmission stream. Where the CID number exceeds a threshold, an error generation module induces an error in the transmission stream to reduce the CID below the threshold. The modified transmission stream may then be transmitted to a receiver, allowing clock recovery be performed with improved stability at the receiver. Once clock recovery is achieved, the receiver can then process the transmission stream to correct the errors induced at the transmitter end.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: Provided is a radio communication device for performing radio communication with another radio communication device includes a control unit that controls to prepare for data loss during radio communication of transmission data and a transmission unit that transmits the transmission data by radio according to the control of the control unit. One of the radio communication device and the other radio communication device estimates a distance from the other based on a field intensity of a radio signal which is judged to satisfy a certain requirement regarding noise component among received radio signals received from the other of the radio communication device and the other radio communication device. The control unit performs a control of a content according to the distance estimation result.

Abstract: A channel interleaver comprises a novel constellation-based permutation module. The channel interleaver first receives a plurality of sets of encoded bits generated from an FEC encoder. The encoded bits are distributed into multiple subblocks and each subblock comprises a plurality of adjacent bits. A subblock interleaver interleaves each subblock and outputs a plurality of interleaved bits. The constellation-based permutation module rearranges the interleaved bits and outputs a plurality of rearranged bits. The rearranged bits are supplied to a symbol mapper such that a plurality of consecutively encoded bits in the same set of the encoded bits generated from the FEC encoder is prevented to be mapped onto the same level of bit reliability of a modulation symbol. In addition, the plurality of adjacent bits of each subblock is also prevented to be mapped onto the same level of bit reliability to achieve constellation diversity and to improve decoding performance.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: An interleaving method (2) and an interleaver (9) for frequency interleaving data symbols. The data symbols are for allocation to carriers in a set of NFFT carriers of a module for multiplexing and modulation by orthogonal functions in a multicarrier transmitter device (3). A block of Npm successive data symbols is interleaved in application of an interleaving law that varies over time for a given transmission mode of the transmitter device, where Npm is less than or equal to NFFT.

Abstract: The packet interleaving method includes selecting successive input sets of consecutive input packets (X1 . . . XNin) received from a forward correction module (14), each input packet (Xj) being a vector of constellation points of a predetermined constellation diagram. For each input set, it further includes generating an output set of output packets (O1 . . . ONout), each output packet (Om) being a vector of constellation points, by distributing the constellation points of each input packet (Xj) of the input set, and sending the output packets (O1 . . . ONout) of the output set to a modulator (18). The input set including Nin input packets (X1 . . . XNin) and each of the Nin input packets (X1 . . . XNin) including a same number Lin of constellation points, the number Nout of output packets in the output set is related to Lin by the relation Lin=A×Nout, where A is a fixed whole number.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant.

Abstract: A method in a communication system, where a systematic code obtained by systematic encoding of information bits having dummy bits inserted and by deletion of the dummy bits from results of the systematic encoding is transmitted. On a receiving side, the deleted dummy bits are inserted into the received systematic code and then decoded. The method includes: deciding a size of dummy bits for insertion into information bits; segmenting the information bits into a number of code blocks when a bit size of the information bits is greater than a stipulated size; inserting dummy bits into each block of the segmented information bits in conformity with a dummy bit insertion pattern; performing systematic encoding of each block of the information bits into which the dummy bits are inserted, and deleting the dummy bits from the results of the systematic encoding to generate a systematic code.

Abstract: A reference signal cyclic shift (CS) is quantized as a combination of a cell specific CS with an outcome of a pseudo-random hopping, and an indication of the cell specific CS is broadcast in the cell. In one embodiment the CS is quantized as a modulo operation on a sum of the cell specific CS, the outcome of the pseudo-random hopping, and a user specific CS, in which case an indication of the user specific CS is sent in an uplink resource allocation and a user sends its cyclically shifted reference signal in the uplink resource allocated by the uplink resource allocation. The CS may also be quantized according to length of the reference signal as cyclic_shift_symbol=(cyclic_shift_value*length of the reference signal)/12; where cyclic_shift_value is between zero and eleven and cyclic_shift_symbol is the amount of CS given in reference signal symbols.

Abstract: A cyclic shift of a reference signal is quantized as a combination of a cell specific cyclic shift with an outcome of a pseudo-random hopping, and an indication of the cell specific cyclic shift is broadcast in the cell. In one embodiment the cyclic shift is quantized as a modulo operation on a sum of the cell specific cyclic shift, the outcome of the pseudo-random hopping, and a user specific cyclic shift, in which case an indication of the user specific cyclic shift is sent in an uplink resource allocation and a user sends its cyclically shifted reference signal in the uplink resource allocated by the uplink resource allocation. The cyclic shift may also be quantized according to length of the reference signal as cyclic_shift_symbol=(cyclic_shift_value*length of the reference signal)/12; where cyclic_shift_value is between zero and eleven and cyclic_shift_symbol is the amount of cyclic shift given in reference signal symbols.

Abstract: A method for protecting digital memory against permanent and transient errors and a related device, the digital data being stored in at least one storage matrix of memory cells in a given number of rows and columns, comprises: an encoding step generating code words from data organized in binary words by application of asymmetric code introducing at least two different levels of protection, the first level of protection said to be high being associated with a first sub-group of bits of the code word and a second level of protection said to be low being associated with a second sub-group of the same word; swapping positions of the bits of the code word making the bits with a high level of protection correspond for their storage to the columns of the storage area comprising defective memory cells and the bits with a low level of protection to the remaining columns.

Abstract: Various embodiments are described for back channel communication. One embodiment is a method that comprises receiving data at customer premises equipment (CPE), determining at least one error in the received data, formatting the determined error for communication to a central office (CO), and sending the formatted error to the CO via a back channel, wherein the formatted error is sent between sync frames of a discrete multitone (DMT) superframe.

Abstract: In a communication system (100), a method and an accompanying apparatus provide for acknowledging reception of a packet of data. A receiver (400) at a serving base station (101) receives a message on an acknowledgement channel (340) for indicating the reception of the packet of data at a mobile station (102), and may determine an erasure of the message. A non-serving base station (160) may also receive the message on the acknowledgement channel (340) from the mobile station (102), determines a value of the message, and communicates the value of the message to the serving base station (101). The serving base station (101) changes the erasure to the value of the message, and terminates a transmission of a remainder of data units of the packet of data to the mobile station (102) when the value of the message is a positive acknowledgment from the non-serving base station (160).

Abstract: A method and apparatus for encoding channel quality indicator (CQI) and precoding control information (PCI) bits are disclosed. Each of the input bits, such as CQI bits and/or PCI bits, has a particular significance. The input bits are encoded with a linear block coding. The input bits are provided with an unequal error protection based on the significance of each input bit. The input bits may be duplicated based on the significance of each input bit and equal protection coding may be performed. A generator matrix for the encoding may be generated by elementary operation of conventional basis sequences to provide more protection to a most significant bit (MSB).

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path.

Abstract: An improved bit mapping method and apparatus for a communication system is provided. A bit mapping method of the present invention includes arranging coded bits in a codeword in an order of recovery capability. A shift region including a number of coded bits is set. The coded bits are rearranged in the shift region by shifting the shift region by a number of bits equal to a number of bits that is indicated by a shift factor. The rearranged coded bits are mapped into a modulation symbol in an order of reliability from a lowest reliability bit position to a highest reliability bit position of the modulation symbol.

Abstract: In a communication system (100), a method and an accompanying apparatus provide for acknowledging reception of a packet of data. A receiver (400) at a serving base station (101) receives a message on an acknowledgement channel (340) for indicating the reception of the packet of data at a mobile station (102), and may determine an erasure of the message. A non-serving base station (160) may also receive the message on the acknowledgement channel (340) from the mobile station (102), determines a value of the message, and communicates the value of the message to the serving base station (101). The serving base station (101) changes the erasure to the value of the message, and terminates a transmission of a remainder of data units of the packet of data to the mobile station (102) when the value of the message is a positive acknowledgement from the non-serving base station (160).

Abstract: The invention provides a data storage device. In one embodiment, the data storage device comprises a memory and a controller. The memory is for data storage. When the data storage device receives first source data to be written to the memory from a host, the controller generates at least one first input data according to the first source data, scrambles the first input data according to a plurality of pseudo random sequences to obtain a plurality of first scrambled signals, calculates a plurality of transmission powers of the first scrambled signals, and selects a target scrambled signal with a lowest transmission power to be stored in the memory from the first scrambled signals.

Abstract: An apparatus, system, and method are disclosed for determining the location of intermediate CRC in a data stream sent from a channel subsystem to a control unit of an I/O processing system. A CRC locating module determines the location of at least one intermediate CRC in a transport data information unit. A CRC offset module determines a CRC offset of the at least one intermediate CRC. The CRC offset is a value identifying the difference between the location of the at least one intermediate CRC and the location of the first byte of user data in the transport data information unit. An offset block creation module creates a CRC offset block which includes a CRC offset value for each of the at least one intermediate CRC within the transport data information unit and a transmission module transmits the COB to a control unit in the I/O processing system.

Abstract: A method for preventing a data storage device from data shift errors is provided. First, data is encoded into an error correction code. The error correction code is then scrambled to obtain a scrambled code to be stored in a memory. The scrambled code is then retrieved from the memory to obtain first read-out data. The first read-out data is then descrambled to obtain a first descrambled error correction code. The first descrambled error correction code is then decoded to determine whether the first descrambled error correction code has uncorrectable errors. When the first descrambled error correction code has uncorrectable errors, the scrambled code stored in the memory is read again to output second read-out data without shift errors. Following, the second read-out data is then descrambled to obtain a second descrambled error correction code, and the second descrambled error correction code is then decoded to recover the data.

Abstract: An apparatus and method for transmitting a signal using a bit grouping method in a wireless communication system is disclosed. Interleaved subblocks are maintained, and output bit sequences are modulated in due order after bit grouping and bit selection. The bit grouping method is advantageous in that bit reliability is uniformly distributed.

Abstract: In a method for improved turbo decoding in a wireless communication system, jointly allocating (S10) a predetermined maximum number of decoding iterations to a batch of received decoding jobs; and consecutively performing decoding iterations (S20) adaptively for each job in the batch until a convergence criteria is reached for each job in the batch, or until the predetermined maximum number of iterations for the batch is reached.