Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: Memory array repair where the repair logic cannot operate at the same operating condition as the memory array is presented. In one embodiment, a test is run with the memory array configured in a first operating condition that repair logic for the memory array cannot achieve, and test data is accumulated from the test in the memory array. The memory array is then read with the memory array configured in a second operating condition that the repair logic can achieve using the test data from the test at the first operating condition. As a result, repairs can be achieved even though the repair logic is incapable of operating at the same condition as the memory array. A method, test unit and integrated circuit implementing the testing are presented.

Abstract: A method for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: Design structure for memory array repair where the repair logic cannot operate at the same operating condition as the memory array is presented. In one embodiment, a test is run with the memory array configured in a first operating condition that repair logic for the memory array cannot achieve, and test data is accumulated from the test in the memory array. The memory array is then read with the memory array configured in a second operating condition that the repair logic can achieve using the test data from the test at the first operating condition. As a result, repairs can be achieved even though the repair logic is incapable of operating at the same condition as the memory array. A method, test unit and integrated circuit implementing the testing are presented.

Abstract: To facilitate a processor during a reset operation, a linked list of pointers to a list of defective cache lines is created. The good data bits in defective cache lines are used for creating a linked list or other data structure for storing relevant information regarding defective cache lines.

Abstract: An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch on a scan chain is used that holds the programming information for each eFuse. This latch allows for programming only a portion of eFuses during each stage of testing. Moreover, the data programmed in the eFuses can be sensed and read as part of a scan chain. Thus, it can be easily determined what portions of the bank of eFuses have already been programmed by a previous stage of testing and where to start programming the next set of data into the bank of eFuses. As a result, the single bank of eFuses stores multiple sets of data from a plurality of test stages.

Abstract: A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element including the non-operational memory cells. A first repair sub-circuit soft repairs the memory by substituting the selected memory elements with the redundant memory elements. A second repair sub-circuit hard repairs the memory based on the substitutions.

Abstract: Redundant storage of computer data including encoding N data values through M linear expressions into M encoded data values and storing each encoded data value separately on one of M redundant storage devices where M is greater than N and none of the linear expressions is linearly dependent upon any group of N?1 of the M linear expression.

Abstract: A hierarchical encoding format for coding repairs to devices within a computing system. A device, such as a cache memory, is logically partitioned into a plurality of sub-portions. Various portions of the sub-portions are identifiable as different levels of hierarchy of the device. A first sub-portion may corresponds to a particular cache, a second sub-portion may correspond to a particular way of the cache, and so on. The encoding format comprises a series of bits with a first portion corresponding to a first level of the hierarchy, and a second portion of the bits corresponds to a second level of the hierarchy. Each of the first and second portions of bits are preceded by a different valued bit which serves to identify the hierarchy to which the following bits correspond. A sequence of repairs are encoded as string of bits. The bit which follows a complete repair encoding indicates whether a repair to the currently identified cache is indicated or whether a new cache is targeted by the following repair.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: To reduce the area relating to location of redundant elements for relieving defects of a memory. A memory device has row address and input/output data as two dimensional redundancy parameters for relieving defects of an embedded memory 30. It comprises a built-in self-test circuit 10 for testing defects of the embedded memory 30, a redundant element location operator 20 for determining which redundant element replaces a defect based on a preset order and according to the order in which defects are detected by the self-test circuit 10, and a row redundancy unit 31 and an I/O redundancy unit 32 for replacing the defects in the embedded memory according to the determined order. The redundant element location operator 20 determines the priority axis according to the preset order and according to the order in which the defects are detected, and holds redundant element location information.

Abstract: A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.

Abstract: A self-repair circuit for a semiconductor memory provides input and output test selectors coupled to respective data bit group inputs and outputs, respectively and input and output repair selectors coupled between the input and output test selectors and functional inputs and functional outputs, respectively. This arrangement allows all data bit groups to be tested in one pass and all test and repair selector circuitry to be tested.

Abstract: In general, various methods, apparatuses, and systems that generate an augmented repair signature to repair all of the defects detected in a first test of a memory as well as in a second test of the memory.

Abstract: Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.

Abstract: An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array (50) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry (92). A selected one of these vectors stored in the actual solution storage circuitry (92) is then used to determine rows and columns in memory array (20) to be replaced with redundant rows (22, 24) and redundant columns (26).

Abstract: A method for storing memory test information includes the steps of storing a portion of information related to locations and numbers of failed memory cells detected while testing memory, and updating the stored information as failed memory cells are detected to indicate a first type of memory spare is to be assigned to repair a failed memory cell, a second complementary type of memory spare is to be assigned to repair the failed memory cell, or the memory is not repairable. The first type of memory spare corresponds to one of a row and a column portion of memory and the second complementary type of memory spare corresponds to the other of the row and column portions of memory.

Abstract: A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.

Abstract: Various methods, apparatuses, and systems that use a replacement policy algorithm to implement tracking of one or more memory locations that have incurred one or more data transfer failures.

Abstract: An apparatus and method for controlling and providing off-pitch shifting circuitry for implementing column redundancy in a multiple-array memory is described in connection with an on-board cache memory integrated with a microprocessor. Depending upon the particular sub-array being accessed, shift position data is provided to a shared, off-pitch shift circuit to control the read and/or write operations for the memory. A register bank stores data identifying the defective columns which is compared to the incoming address information to detect any matches. In response to a match, control information is provided to the off-pitch shift circuit for shifting or re-routing the incoming data to a non-defective address in the memory. In this way, defective columns located in different positions in each sub-array can be replaced by redundant paths, thereby repairing the cache and increasing the manufacturing yield of microprocessors with an on-board cache memory.

Abstract: In general, a method, apparatus, and system determine the allocation of the one or more redundant components while fault testing the memory. In an embodiment of an apparatus, one or more memories and one or more processors are located on a single chip. Each memory has one or more redundant components associated with that memory. The one or more redundant components include at least one redundant column. The one or more processors contain redundancy allocation logic having an algorithm. The algorithm determines the allocation of the one or more redundant components to repair one or more defects detected in the one or more memories while fault testing the memory.

Abstract: An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.

Abstract: Techniques for isolating and repairing failures on a programmable circuit are provided. An error on programmable circuit may be caused by a defect on the chip. The error is located, and the circuit elements effected by the defect are isolated. By identifying operable circuit elements near the defect, the number of circuit elements that are adversely effected by the defected can be narrowed down. The failed circuit elements adversely effected by the defect are then shut down and cut off from the rest of the programmable circuit. The functionality performed by the failed circuit elements is transferred to an unused portion of the programmable circuit. The se techniques reduce the amount of circuit elements that need to be shut down as a result of a defect on a programmable circuit.

Abstract: Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

Abstract: A semiconductor memory device includes memory cells, redundant cells, a redundancy repair control circuit and a test mode control circuit. Each of the memory cells is assigned a unique address to be accessed by a corresponding address. The redundant cells are replaceable with the memory cells. The redundancy repair control circuit replaces predetermined memory cells among the memory cells with the redundant cells. The test mode control circuit invalidates an operation of the redundancy repair control circuit and assigns an additional unique address to the redundant cells so that all of the memory cells and the redundant cells are accessible during a test mode.

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: An embedded test and repair (ETR) scheme and interface for generating a self-test-and-repair (STAR) memory device using an integrated design environment. User interface and supporting program code is operable to provide a dialog box for defining a memory group that includes one or more memory instances, each having corresponding fuse element requirements based on its configuration data. BIST elements and a processor compiler for providing ETR functionality are also specified via suitable portions of the integrated GUI. A fuse equation is employed for computing the number of fuses for each memory instance, which equation is derived based on the memory configuration. Fuse information for each memory instance is automatically passed to a fuse compiler that generates a fuse box having an appropriate number of fuses that can accommodate the fuse requirements of the memory instances of the group.

Abstract: A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more “planes.” Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory.

Abstract: A system and methodology for testing memory in an integrated circuit implementing BIST testing to calculate row and column redundancy and enable replacement of a defective row or column of memory cells. The system comprises circuitry for detecting a first single memory cell failure in a row; and, recording the I/O value of the first Single Cell Fail (SCF). A circuit is provided for detecting whether more than one single cell failure has occurred for a tested row, and, in response to detecting a second SCF, comparing recorded I/O value of the subsequent tested row, with the I/O value associated with the first failed memory cell. Upon detection of defective bits, the defective column and row of memory having corresponding defective bits set is replaced.

Abstract: A defect information storing device includes two tables for storing information on defective points of a semiconductor device. The first table stores column addresses and number of defective points existing at this column address for (r×c+c) lines. The second table stores row addresses, number of defective points existing at this row address, and column identifiers indicating the storage place of the column address of the defective point in the first table for (r×c+r) lines.

Abstract: A memory controller includes a check/correct circuit and a data remap circuit. The check/correct circuit is coupled to receive an encoded data block from a memory comprising a plurality of memory devices. The encoded data block includes a plurality of check bits, and the check/correct circuit is configured to decode the encoded data block and to detect a failure of one of the plurality of memory devices responsive to decoding the encoded data block. The data remap control circuit is configured to cause a remap of each of a plurality of encoded data blocks to avoid storing bits in the failing memory device. A memory controller may also be configured to detect and correct a first failed memory device and a second failed memory device of the plurality of memory devices.

Abstract: The present invention is a method for providing error correction for an array of disks using non-volatile random access memory (NV-RAM). Non-volatile RAM is used to increase the speed of RAID recovery from a disk error(s). This is accomplished by keeping a list of all disk blocks for which the parity is possibly inconsistent. Such a list of disk blocks is much smaller than the total number of parity blocks in the RAID subsystem. The total number of parity blocks in the RAID subsystem is typically in the range of hundreds of thousands of parity blocks. Knowledge of the number of parity blocks that are possibly inconsistent makes it possible to fix only those few blocks, identified in the list, in a significantly smaller amount of time than is possible in the prior art. The technique for safely writing to a RAID array with a broken disk is complicated. In this technique, data that can become corrupted is copied into NV-RAM before the potentially corrupting operation is performed.

Abstract: A memory controller may include a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be written to memory, where the memory includes a plurality of memory devices arranged on a plurality of memory modules. Each of the plurality of memory modules includes a plurality of the plurality of memory devices. The check bit encoder circuit is configured to encode the data block with a plurality of check bits to generate an encoded data block. The plurality of check bits are defined to provide at least detection of a failure of one of the plurality of memory modules. The check/correct circuit is coupled to receive the encoded data block from the memory, and is configured to detect the failure of one of the plurality of memory modules responsive to decoding the encoded data block.

Abstract: A magnetoresistive state-solid state storage device having arrays of magnetoresistive storage cells. Sparing resources such as a plurality of spare rows are allocated to replace rows of storage cells which are affected by physical failures. A count is made for the number of failed rows within each array, and a count is also made of the number of failed rows within a cross-array row set spread across plural arrays. A spare row or rows are allocated by selecting a cross-array row set affected by the highest number of failed rows and therefore most likely to lead to unreliable data storage, and then selecting an array in this cross-array row set having the lowest number of failed rows, and therefore the least competition for sparing resources. The method proceeds iteratively with counts updated as sparing resources are allocated.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: A column redundancy circuitry and a method for implementing the same are provided. One exemplary method provides routing for an access request addressed to a defective cell. The method includes providing a redundant column within a memory circuit, the redundant column in communication with a sense amplifier. Next, a defective cell of a memory circuit is located and the address is programmed. An access request is then processed, the access request containing the address of the defective cell Finally, the access request is routed to the redundant column through enable circuitry. Some notable advantages include the conservation of surface area of the memory circuit induced by locating the redundant column within the memory circuit. The externalization of the fuse box, Built In Self Repair region and the logic circuitry from the memory core also provide increased flexibility.

Abstract: Apparatus and methods for providing enhanced redundancy for a cache are provided. For example, an on-die cache is disclosed which includes a first memory array having a defective array line; a second memory array having a defective array line; and a redundant memory array having a plurality of array lines. A first one of the array lines is mapped to the defective array line of the first array and a second one of the array lines is mapped to the defective array line of the second array.

Abstract: A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.

Abstract: Circuitry is provided to allow early switching of input signals from a first configuration directed to blow a first anti-fuse to a second configuration directed to blow a second anti-fuse, yet still allow complete blowing of the first anti-fuse. Such circuitry may be applied to methods of repairing a memory device after testing. Data concerning available repair cells may be stored in at least one on-chip redundancy register.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.

Abstract: A built-in self test system (124) and method for two-dimensional memory redundancy allocation. The built-in self test system is adapted to allocate two redundant columns (116) and one redundant row (120) to an embedded memory (104) as needed to repair single cell failures (SCFs) within the rows (108) and columns of the memory. The self-test system includes a left-priority encoder (136), a right-priority encoder (140), and a greater-than-two detector (144). The left-priority encoder encodes the location of the first SCF most proximate the most-significant bit of the corresponding word. The right-priority encoder encodes the location of the first SCF most proximate the least-significant bit of the corresponding word. The greater-than-two detector determines whether a word contains more than two SCFs.

Abstract: Field repairable system-on-a-chip (SOC) devices are possible by including electrically programmable circuits on the device, for example in the embedded memory of the SOC device. The SOC device may undergo a conventional repair process prior to packaging the device for field operation. In addition to the conventional repair process, usage indicator may be marked prior to packaging. In the field, if the embedded memory of the SOC device fails to operate correctly, diagnostic programs may be run to identify the faulty rows and/or columns. Redundant rows and/or columns may be electrically programmed in the field to repair the SOC device. Multiple field repairs can be accomplished by using this invention.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: A built-in self-diagnostic (BISD) memory device includes a two-dimension memory array provided with a redundant memory rows and columns that can be substituted for various ones in the two-dimension memory array by an external repair facility. A stimulus generator outputs multi-address test sequences to the memory array during a test mode. A response evaluator receives responses from the memory. A fault table stores evaluations of the responses, and communicates them to the external repair facility. A repair register indicates which memory columns have been intermediately scheduled for repair by the response evaluator. Column counters each accumulate the number of memory bit faults detected in a respective memory column. All are disposed in a single integrated circuit semiconductor device.