Abstract: The present invention discloses methods and systems of accomplishing I/O-based redundancy for a memory device that includes two-bit memory cells. The memory device includes a core two-bit memory cell array and a redundant two-bit memory cell array. The configuration of the core two-bit memory cell array is non-uniform such that the two-bit memory cells therein are not arranged in a sequential order. Due to the non-uniform configuration, I/O based redundancy is accomplished by decoding the addresses with a redundant Y-decoder circuit and translating the addresses using an address translation circuit. The translated addresses identify the location of the two-bit memory cells within the non-uniform core two-bit memory cell array. The decoding of the addresses configures the redundant two-bit memory cell array to provide a configuration that matches the two-bit memory cells in the location identified by the translated address.

Abstract: A method is presented for built-in redundancy analysis of a semiconductor memory device. The method does not require retention of an entire memory bitmap, and may be implemented on-chip and integrated within existing BIST circuitry. The regular memory is comprehensively tested, and defective rows and columns are flagged for replacement by redundant rows and/or columns; the elements containing the most defects are the first to be flagged. If all of the defective memory locations can be replaced using redundant rows and columns, the method designates the memory as repairable; a repair solution may then be scanned out of the memory device. The method is believed to provide a fast, cost-effective means of testing and repairing memory devices, with a consequent improvement in production yields.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: A memory circuit includes a memory structure having sets of redundant columns where each set of redundant columns can replace a column of the memory array that may include a defective cell. Selection of the redundant columns for a memory access is accomplished by performing an address comparison between the address provided to the memory and one or more predetermined values that indicate which portion of the data array each set of redundant columns replaces. Based on this address comparison, a column redundancy select signal is asserted when a set of redundant columns is selected. For a read operation, the column redundancy select signal propagates through redundant column logic select the appropriate data from a particular set of redundant columns. This redundant data that is selected is substituted for data stored in the memory array for the read operation.

Abstract: A semiconductor memory device includes a redundancy selection circuit. The redundancy selection circuit includes generating means for simultaneously generating a first redundancy address and a second redundancy address in response to the column address at a read cycle. The first redundancy address indicates whether the column address is defective, and the second redundancy address indicates the place where a defective one of the first selected columns is positioned. The redundancy selection circuit further includes means for generating redundancy selection signals each corresponding to the first selected columns in response to the first and second redundancy addresses. According to the present invention, the redundancy selection circuit stores defective addresses by use of flash EEPROM cells similar to those of the main memory cell. Addresses can be programmed, without limitation in the redundancy selection circuit. All the redundant memory cells of an array are tested.

Abstract: A method is presented for self-test and self-repair of a semiconductor memory device. A single built-in self-test (BIST) engine with an extended address range is used to test the entirety of memory (i.e., both redundant and accessible memory portions) as a single array, preferably using a checkerboard bit pattern. An embodiment of the method comprises two stages. In the first stage, faulty rows in each memory portion are identified and their addresses recorded. Known-bad rows in accessible memory are then replaced by known-good redundant rows, and the resulting repaired memory is retested in a second stage. During the second stage, repair of the accessible memory portion is verified, while defects among the redundant portion are ignored. Compared to existing methods, the new method is believed to simplify the interface between the BIST and the built-in self-repair (BISR) circuitry, reduce the overall size of test and repair circuitry, and provide improved test coverage.

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more “planes.” Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory.

Abstract: Methods and an associated apparatus are disclosed for providing fault tolerance for memory. The method involves generating a remapping value. Then the remapping value may be logically combined with the address value intended for accessing a given memory location to remap the bad address to an unused address.

Abstract: A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

Abstract: A test method of a tester of a semiconductor memory device which includes recording a test pattern into the semiconductor memory device, reading the recorded test pattern to compare with a expected pattern, detecting information on a defect of the semiconductor memory device with a result of the comparison and interpreting the information on the defect of the semiconductor memory device, the method comprising the steps of: setting up minimum and maximum values relevant to a desired capacity of the semiconductor memory device to be tested; counting up from the preset minimum to the preset maximum values; generating a carry signal by comparing the preset maximum value with the counted value when the counted value gets to the preset maximum value; and resetting a value to be counted if the carry signal is generated, to thereby generate addresses of the semiconductor memory device, and a tester of the semiconductor memory device comprising: minimum and maximum address registering means for saving minimum and maxi

Abstract: A semiconductor memory of an integrated circuit has memory cells that are combined to form individually addressable normal units and redundant units for replacing normal units. The semiconductor memory has a selection circuit for selecting one of the redundant units. A non-volatile first memory unit for storing an address, which can be programmed by an energy beam, of a normal unit to be replaced is provided. A non-volatile second memory unit for storing an address, which can be programmed via electrical contact is also provided. The first and second memory units are connected to the selection circuit for transmitting their respective stored information to the selection circuit. A repair can thus be carried out on the unhoused semiconductor memory and on the housed semiconductor memory. Since only a sufficient portion of all the redundant circuits to be provided are configured in such a way, this allows a space requirement that is smaller overall.

Abstract: A memory device generator for generating memory devices in a CAD environment, the generator composed of a library file containing predefined basic circuit components; memory array generation algorithm interacting with the library file for generating a variable-size memory array representation having a variable number of memory elements, and at least one redundant memory element; memory element selection circuit generation algorithm interacting with the library file for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to memory device address inputs.

Abstract: Field repairable system-on-a-chip (SOC) devices are possible by including electrically programmable circuits on the device, for example in the embedded memory of the SOC device. The SOC device may undergo a conventional repair process prior to packaging the device for field operation. In addition to the conventional repair process, usage indicator may be marked prior to packaging. In the field, if the embedded memory of the SOC device fails to operate correctly, diagnostic programs may be run to identify the faulty rows and/or columns. Redundant rows and/or columns may be electrically programmed in the field to repair the SOC device. Multiple field repairs can be accomplished by using this invention.

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more “planes.” Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: A read/write memory includes a monolithically integrated self-test device which iteratively enables a defect test with a redundancy analysis, without significant external test aids. The test is achieved essentially by virtue of the fact that word lines to be repaired are stored and excluded from further examinations and in each case the line having the most defects not previously detected is always determined and examined first, until either the number of repair lines no longer suffices or no more defects occur. An associated test method is also provided.

Abstract: Row faulty bit storage memory corresponding to a spare row circuit and a column faulty bit storage memory corresponding to a spare column circuit are provided independently of each other, and faulty bits of these faulty bit storage memories are counted by a row faulty bit counter and a column faulty bit counter, respectively. Repairability of the faulty row and repairability of the faulty column are determined using the row faulty bit storage memory and the column faulty bit storage memory. A time required for determining repairability of the faulty bit of a semiconductor memory is reduced, and a storage capacity of the faulty bit storage memory is reduced.

Abstract: Integrated circuit memory device redundancy circuits are provided that include a plurality of transistors and fuses, a respective transistor and a respective fuse being serially coupled between a respective address line input and a logic circuit to generate a selection signal for a redundant memory cell in response to a predetermined address on the address bus of the integrated circuit memory device. In one embodiment, a decoder is coupled between the address bus of the integrated circuit memory device and a plurality of external address inputs of the integrated circuit memory device. A redundancy enable control circuit may be provided that includes a main fuse and that generates a fuse enable signal in response to opening of the main fuse wherein the plurality of transistors are responsive to the fuse enable signal.

Abstract: A method and corresponding architecture are disclosed for sharing redundant rows between banks of a memory array. The architecture is such that sub-arrays associated with different banks are alternated and coupled via a sense amp. In addition, sub-arrays belonging to the same bank are coupled via a single row decoder. This architecture allows for adjacent sub-arrays belonging to different banks to share redundant rows, thereby effectively doubling the number of redundant rows available for use in a given bank.

Abstract: A method of determining a redundancy solution for a semiconductor memory under test (DUT) having redundant rows and columns is disclosed. The method includes the steps of first testing the DUT in a first environment with a first tester to generate a first fail data set. The first fail data set is then transferred to a second tester where the DUT is test in a second environment to generate a second fail data set. The first and second failure data sets are then merged to create a merged fail data set. A highly optimized redundancy solution is then determined based on the merged fail data set.

Abstract: A memory has coding units that are used for allocating any one of redundant lines at a time to any one of first lines on an address basis. Each coding unit has a programmable activation unit. In a first programming state of the activation unit, the associated coding unit, when programmed, allocates a complete redundant line to a complete first line on an address basis. In a second programming state of the activation unit, the associated coding unit, when programmed, allocates only one of the subregions of one of the redundant lines to a corresponding subregion of one of the first lines on an address basis.

Abstract: The present invention is a method for providing error correction for an array of disks using non-volatile random access memory (NV-RAM). Non-volatile RAM is used to increase the speed of RAID recovery from a disk error(s). This is accomplished by keeping a list of all disk blocks for which the parity is possibly inconsistent. Such a list of disk blocks is much smaller than the total number of parity blocks in the RAID subsystem. The total number of parity blocks in the RAID subsystem is typically in the range of hundreds of thousands of parity blocks. Knowledge of the number of parity blocks that are possibly inconsistent makes it possible to fix only those few blocks, identified in the list, in a significantly smaller amount of time than is possible in the prior art. The technique for safely writing to a RAID array with a broken disk is complicated. In this technique, data that can become corrupted is copied into NV-RAM before the potentially corrupting operation is performed.

Abstract: A typical integrated circuit device may include a central processing unit (CPU), trap and patch (T&P) logic circuits and registers. Volatile RAM and read only memory (ROM) are also provided. A predetermined number of memory locations in the RAM are allocated for defective memory cell replacement. When power is turned on or the system is reset, the CPU executes a program stored in ROM which identifies defective RAM locations on the fly and loads the trap and path circuits and registers with the defective addresses and the replacement or patch RAM locations (addresses). When the CPU reads or writes to the bad RAM locations, the T&P logic inserts the patch address of the good RAM memory location for the reading and writing operations. In this manner, virtual defective RAM replacement is transparent to the CPU.

Abstract: A ROM including an array, each cell of which is accessible by means of a column address and of a row address, includes a parity memory for storing the expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating the parity of each row and of each column, comparing the calculated and expected parities for each row and each column, and in case they are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting the value read from the array cell, having its row and column marked in the address memory.

Abstract: A self-repair method for a random access memory (RAM) array comprises writing a value to the memory array, reading a value from the memory array and comparing the read and write values to identify faulty memory cells in the memory array. An address of a newly-discovered faulty memory cell is compared to at least one address of at least one previously-discovered faulty memory cell. The address of the newly discovered faulty memory cell is stored if a column or row address of the newly-discovered faulty cell does not match any column or row address, respectively, of a previously-discovered faulty memory cell. Flags are set to indicate that a spare row or a spare column must replace the row or column, respectively, identified by the address of the previously-discovered faulty memory cell, if the row or column address of the newly-discovered memory cell matches the respective row or column address of the previously-discovered faulty memory cell.

Abstract: An address conversion circuit is disclosed for converting a logical address to a physical address and outputting the physical address to a memory, the memory including a normal memory array and a redundant memory array wherein a defective address corresponding to a defective memory cell in the normal memory array is replaced by a redundant address in the redundant memory array so as to ensure total memory capacity of the memory.

Abstract: A fault tolerant memory system includes an array of block-erasable storage elements (12). Each block (12) of storage locations is sub-divided into sub-groups (14) of storage elements. A control information store means holds defect information for each group in each block and an address counter holds the addresses of the groups in the particular erase block being erased. A testing circuit checks whether the defect information stored in the control information store for the particular group currently addressed by the address counter indicates that the particular group contains one or more defective storage locations. If it does it increments the address counter.

Abstract: An apparatus receives a series of locations containing a row address and a column address of a fault detected within an array. A row replacement priority circuit within the apparatus logs the row address of the first fault detected, and thereafter marks a column of any subsequent faults detected in rows other than the row of the first detected fault. Concurrently, a column replacement priority circuit within the apparatus logs the column address of the first fault detected, and thereafter marks a row of any subsequent faults detected in columns other than the column of the first detected fault.

Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device includes a set of fuses, anti-fuses, or flash EEPROM cells that store a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block used to repair the defective cell. Routing circuitry, such as mux circuitry, in the block repair device is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry in the block repair device then compares the row and column address bits output by the routing circuitry with a stored portion of the address of the defective cell that defines the repair block.

Abstract: A method is provided for determining the location of faulty components in a computer memory array on a chip and for providing a software repair procedure. According to the method, the location of faulty components in a computer memory array is determined by successively reading and writing to locations in the array according to an algorithm. If a faulty component is detected, it is determined whether a spare component in a spare memory array on the chip is available. If a spare component is available, a spare component is designated to correspond to the faulty component. A look up table on the same chip stores information representing the location of the faulty component associated with information representing the location of the corresponding spare component.

Abstract: A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a host computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also counts of the number of memory cells of each row and column that are defective. After the test the counts are supplied to the host computer. When the host computer is unable to determine how to allocate the spare rows and columns from the counts alone, it requests the tester to process the data in the ECM to determine and supply the host computer with addresses of the defective memory cells.

Abstract: A mask ROM includes electrically programmable redundancy cells. Error data is stored in non-use cells among the redundancy cells and access inhibition addresses are attached to the non-use cells in which the error data is stored. If illegal copying is effected by sequentially incrementing the address of the mask ROM, the redundancy cell is accessed and the error data is output when the access inhibition address is accessed.

Abstract: A compression test mode, independent of redundancy, for a memory device is disclosed. In one embodiment, a method for testing a memory array of a memory device includes outputting individually the output bits of a predetermined number of memory cells, upon failure of a compression mode. The cells may then be checked for errors and replaced if necessary on an individual basis. In another embodiment, a memory device includes an array of memory cells, and a compression test mode circuit such that only those cells that are defective are replaced with redundant cells. The circuit checks a number of memory cells at one time, however, in a compression test mode.

Abstract: An integrated circuit includes an array of memory cells, storage circuits and a write circuit coupled to the array, and a control circuit coupled to the array and write circuit. The write circuit is operable to receive initial test data and mask data. The control circuit is operable to enable the write circuit to write the initial test data to the cells, to receive an address of one of the cells, to enable the write circuit if the addressed cell is dormant to write the mask data to the storage circuit coupled to the cell such that the storage circuit stores the mask data, and to allow reading of the cell such that if the cell is dormant, then the storage circuit provides as a read value the stored mask data, and such that if the cell is live, then the storage circuit provides as the read value data that is stored in the cell.

Abstract: An integrated circuit includes primary circuit elements selectable by n address bits. A master storage device is programmable to indicate that at least one primary circuit element is being replaced. Redundant circuit elements each include a non-precharging matching circuit, which includes sub-match circuits. The sub-match circuits include two state storage devices corresponding to one of the possible binary values of at least one of the n address bits and activate a sub-match signal when the binary value of the at least one of the n address bits corresponds to one of the two state storage devices in a first state if the master storage device is programmed. A match circuit activates a match signal in response to all sub-match signals being active to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

Abstract: A scheme for reduction of extra standby current induced by process defects is disclosed. After the bit lines and cells with failure due to process defects are repaired by using redundancy in the repairing process, the fuses connected with the pull-transistors coupled to the defect bit lines are disconnected, therefore cutting the leakage current completely. The standby leakage current can be reduced such that the SRAM can pass the standby current test and the yield is improved.

Abstract: Memory test hardware is provided for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of main memory array, a spare memory array, and reconfiguration memory array, or the apparatus may be adapted for testing all three memory arrays. The memory test hardware may include a controller for generating control signals, a data generator coupled to the controller for generating data signals, and an address generator coupled to the controller for generating address signals. The test device may further include an output data evaluator and repair unit for receiving signals from the main memory array and the spare memory array and for detecting faults in those arrays.

Abstract: Disclosed is a system for generating parity information for a data file in a distributed data structure system. Data objects in the data file are distributed into data buckets located in memory areas in servers interconnected by a network. An nth set of bucket group numbers are generated. A data bucket and a parity bucket are associated with a bucket group number in the nth set. Parity data for the data objects is generated and stored in a parity bucket associated with a bucket group number in the nth set. After adding a data object to the data file an additional data bucket may be provided for additional data object storage space. After adding a data bucket, a determination is made as to whether bucket availability has decreased below a predetermined threshold. If so, an (n+1)th set of bucket group numbers is generated and parity data for at least one of the data objects is stored in a parity bucket associated with a bucket group number in the (n+1)th set.

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more "planes." Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory.

Abstract: Surface area of a semiconductor integrated circuit memory required by programmable fuse boxes is reduced, and the capacitive loading of a column address bus from the programmable fuse boxes is reduced by reducing the number of programmable boxes. Each programmable fuse box is connected through fuses to a plurality of redundant columns in memory arrays whereby any one or more of the redundant column lines can be addressed through the programmed fuse box in replacing a defective column line. An unprogrammed redundant column select line is connected to ground through the fuses connecting the unselected redundant column select lines to ground so that unprogrammed redundant columns are inactive.

Abstract: A redundancy circuit for a semiconductor integrated circuit is disclosed, which includes each cell of the column redundancy cell block corresponding to each cell of the cell sub-array is connected opposite to the connection of the cells of the cell sub-array, wherein a state that an electric charge corresponding to a data written into each cell of the cell sub-array and the column redundancy cell block is discharged, is measured for thus accurately checking the position of the repaired cell after the redundancy operation is performed.

Abstract: A method provides an on-chip repair technique to fix defective row or I/O memory lines in an ASIC memory array with redundancy row or I/O memory lines. The method employs progressive urgency and dynamic repair schemes to optimize the allotted time for repairing defective row and I/O memory lines. Progressive urgency scheme increases the need to repair relative to the available redundancy row or I/O memory lines over the entire repairing time. Dynamic repair executes a mandatory-row or a mandatory-I/O repair as defective row or I/O memory lines are detected. In addition, a recurrence error reroutes the address location of a redundancy memory line to another address location of another redundancy memory line in the event that such redundancy memory line itself is defective, and thus requires further repair.

Abstract: An object of the present invention is that, in a semiconductor memory device having both a redundant circuit and a diagnostic circuit, a memory test for detecting positions of defective memory cells in order to replace the defective memory cells with the redundant circuit can be easily carried out by using the diagnostic circuit. A semiconductor memory device of the present invention includes a normal memory portion, a redundant circuit to replace defective memory cells of the normal memory portion by a units of a word line or a bit line, and a self-diagnostic circuit, and further, in order to realize the object, the device includes a defective cell position storage circuit for storing position information of each defective memory cell when the self-diagnostic circuit detects defective memory cells, and an output circuit for converting position information stored in the defective cell position storage circuit into serial data and outputting the position information.

Abstract: A scheme for error control on AAL in ATM networks capable of realizing a reliable communication with a high throughput and a low latency. On AAL, the segmented data are sequentially written into each column of a matrix shaped data region in an interleaver, while variably setting a last column of the data region in the interleaver. Then, an error control code for the data up to the last column in each row of the data region in the interleaver is obtained and written into a corresponding location within a matrix shaped error control code region in the interleaver. The contents of each column of the data region and the error control code region in the interleaver are then read out, and a prescribed header/trailer is attached to a prescribed number of columns of the data and/or the error control codes read out from the interleaver to form a data unit.

Abstract: A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more "planes." Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory.

Abstract: In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.

Abstract: A high-data density, high-data rate scanning memory device reads and writes data using a plurality of probes. The scanning memory device comprises a memory composed of a matrix of cell arrays each containing a submatrix of memory cells, a plurality of probes having a one-to-one correspondence to each cell array, and a positioning device that operates to simultaneously change the positions of probes relative to the cell arrays. Each of the cell arrays has a cell array status memory for storing information designating whether the cell array is functional or whether the cell array is defective. If the number of defective memory cells detected within each cell array exceeds some predetermined number, the cell array is designated as defective. Defective cell arrays are logically replaced by functional cell arrays. Error correction is applied to the data to reduce reading and writing errors by the scanning memory device and to maintain the integrity of data stored in the memory.

Abstract: A test method for a memory device wherein failures that may only occur under specified worst-case conditions are converted to hard functional failures. These locations are subsequently detected and remapped by built-in self test (BIST) and built-in self-repair (BISR) circuitry. First, a test suite is performed on a memory array which includes redundant row and column locations. Typically, this test suite is performed under conditions which are most likely to induce failure. Row and column locations that are determined to be malfunctioning are scanned out of the memory device, along with the number of available redundant rows and columns. If there are sufficient redundant locations, the failing rows and columns are permanently disabled by blowing each of the corresponding fuse links. When power is subsequently applied to the memory device, BIST will detect rows and columns, including those permanently disabled, with hard functional failures. Accesses to these locations may then be redirected by BISR circuitry.