Abstract: A target block family of a plurality of block families is identified periodically every predetermined number of program erase cycles (PECs) of a memory device. Each block family includes a plurality of blocks. A respective temporal voltage shift of each block of a subset of blocks of the target block family from each die of a plurality of dies associated with the target block family is obtained. A respective die measurement for each respective die is obtained based on an average of the respective temporal voltage shifts of the subset of blocks from each die. Each respective die to a respective die family of a plurality of consecutive die families is assigned based on the respective die measurement for each respective die.

Abstract: A non-volatile memory device includes a plurality of wordlines, each comprising a plurality of cells, a hard decode configured to read each cell of the plurality of cells at a hard decode voltage, a left read sense configured to read voltage values of each cell to the left of the hard decode voltage at a left read sense voltage, a right read sense configured to read voltage values of each cell to the right of the hard decode voltage at a right read sense voltage, a first combiner configured to determine a difference of voltage values read by the left read sense and right read sense to produce a dispersion signal, and a second combiner configured to determine a sum of the voltage values read by the left read sense and right read sense to produce a deviation signal.

Abstract: Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.

Abstract: Methods, devices, non-transitory computer-readable medium, and systems are described for compressing audio data. The techniques involve obtaining a sequence of digitized samples of an audio signal, performing a transform using the sequence of digitized samples, to generate a plurality of spectral lines, obtaining a group of spectral lines from the plurality of spectral lines, and quantizing the group of spectral lines to generate a group of quantized values. Quantizing the group of spectral lines to generate the group of quantized values may comprise performing a specialized rounding operation on a spectral line selected from the group of spectral lines and using the specialized rounding operation to force a group parity value, computed for the group of quantized values, to a predetermined parity value. One or more data frames based on the group of quantized values may be outputted.

Abstract: A system can validate multiple nonvolatile random-access memory (NVRAM) devices in parallel. The system can concurrently write a first data to a first volatile memory of a first NVRAM device and a second NVRAM device. The system can modify a first electrical power source that provides an electrical power output that is received by the first NVRAM device and is received by the second NVRAM device to modify a voltage of the electrical power from a first value to a second value to initiate the first NVRAM device and the second NVRAM device to respectively perform a vault. The system can reset the first electrical power source, causing the first NVRAM device and the second NVRAM device to reset. The system can verify whether the first NVRAM device and the second NVRAM device respectively store the first data in volatile memory subsequent to performing the resetting.

Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

Abstract: Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

Abstract: A voltage detection circuit, a power supply system and a chip are provided. The voltage detection circuit includes: a first step-down sub-circuit, a second step-down sub-circuit and a first voltage-stabilizing sub-circuit; wherein the first step-down sub-circuit has one end connected to one end of the second step-down sub-circuit in series; the first step-down sub-circuit has another end connected to a first port of the voltage detection circuit; and the second step-down sub-circuit has another end connected to a second port of the voltage detection circuit; and wherein the first voltage-stabilizing sub-circuit has one end connected to a third port of the voltage detection circuit and has another end connected to the second port, where the first voltage-stabilizing sub-circuit is turned on when the third port has a voltage higher than the second port and stabilized when the third port has a voltage lower than the second port.

Abstract: In a memory controller for controlling a memory device including a memory block coupled to a plurality of word lines, the memory block including a plurality of memory cells respectively coupled to the plurality of word lines, the memory controller comprising: an operating time calculator configured to calculate program operating times taken to perform a program operation on the memory cells respectively coupled to the plurality of word lines; and an operating voltage determiner configured to determine an erase voltage to be used to erase a memory block by comparing a first program operating time, among the program operating times calculated by the operating time calculator, with the other program operating times, except the first program operating time, among the program operating times.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.

Abstract: An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased condition. The one or more control circuits are further configured to determine a read voltage to read non-volatile memory cells of a corresponding target word line according to an amount of charge in non-volatile memory cells of the selected neighboring word line.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: A memory device and a method for reducing read disturb errors of the memory device are provided. The memory device includes a plurality of memory cells arranged in series and organized into a plurality of blocks, a plurality of word lines respectively coupled to corresponding memory cells, and a controller coupled to the word lines for performing page read operations on the pages in respective blocks through corresponding word lines, in which each of the blocks comprises a plurality of pages of two or more types. The controller accumulates a page read count of the pages of each type in respective blocks, and arranges data to be stored according to the page read count and a latency factor corresponding to the pages of each type in each of the blocks.

Abstract: Devices and techniques for an adjustable voltage drop detection threshold in a memory device are disclosed herein. A voltage drop detection threshold of a memory device is dynamically established. A power loss event is triggered when the supply voltage falls below the voltage drop detection threshold. An error parameter associated with performing multiple memory operations on the memory device is collected. The multiple memory operations are performed while applying a supply voltage at a second supply voltage level of the memory device which is less than a first supply voltage level established as a first operating voltage for the memory device. Determining whether the error parameter is below an allowable error threshold. In response to determining that the error parameter is below the allowable error threshold, the voltage drop detection threshold is established at a voltage level less than the first supply voltage level.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.

Abstract: A method and apparatus for determining a reference voltage id disclosed. The method may include: reading data from a first flash memory page by using different reference voltages, and taking, as a first target reference voltage, one of the different reference voltages at which the first number of erroneous bits of the data that is read reaches a converegence value. The first flash memory page is any one of multiple flash memory pages of a flash memory block to be tested. The method may include adjusting the first target reference voltage to obtain second target reference voltages; and reading data from the flash memory pages by using the second target referece voltages, and taking, as a target reference voltage, one of the second target reference voltages at which the second number of erroneous bits of the data that is read is the smallest.

Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.

Abstract: A semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit is configured to perform a program operation on the memory cell array. The control logic is configured to control the program operation performed by the peripheral circuit. Each of the plurality of memory blocks is coupled to a drain select line, a plurality of word lines, and first and second source select lines that correspond to the memory block. During a program operation performed on a first memory block selected as a program target, among the plurality of memory blocks, the control logic controls the peripheral circuit so that a first source select line of a second memory block that is not selected as the program target, among the plurality of memory blocks, floats.

Abstract: The disclosure discloses a reading reference current automatic regulation circuit of a non-volatile memory. A reading check control module initiates a reading operation, a row reading operation is performed by controlling the memory to switch gate voltage of memory cells to bias gate voltage row by row, a comparison result between a memory cell readout value and an expected value is received, the reading check control module determines whether a reading check is passed according to the comparison result, a reading reference current control module adjusts the digital regulation signal according to whether the reading check is passed, and thus the magnitude of the reading reference current is adjusted through the digital-to-analog conversion module. The disclosure can adaptively regulate the internal reading reference current according to the process threshold voltage deviation in the test and meet the requirements on the function and reliability of the non-volatile memory.

Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.

Abstract: An information handling system (IHS), baseboard management controller (BMC) and method are provided for preventing critical operations when power shutdown is predicted. A service processor of a BMC of the IHS executes a predicted power operation (PPO) utility to monitor health data from physical memory devices of memory of the IHS. Based on the health data, the service processor predicts that at least one of the physical memory devices will fail, causing a power shutdown of the IHS. To prevent any critical operation that is executed by a host processing subsystem of the IHS being adversely affected by the shutdown, the service processor of the BMC updates information contained in a PPO software sensor to indicate the predicted power down.

Abstract: A semiconductor memory device includes: a substrate including a cell region and a connection region; a first word line stack comprising a plurality of first word lines that extend to the connection region and are stacked on the cell region; a second word line stack comprising a plurality of second word lines that extend to the connection region and are stacked on the cell region, the second word line being adjacent to the first word line stack; vertical channels in the cell region of the substrate, the vertical channels being connected to the substrate and coupled with the plurality of first and second word lines; a bridge region that connects the first word lines of the first word line stack with the second word lines of the second word line stack; and a local planarized region under the bridge region.

Abstract: A test device capable of measuring characteristics of respective transistors constituting a memory cell is provided. The test device for testing a SRAM connects a resistor to a bit line on one side of a memory cell selected by a word line selection circuit and a bit line selection circuit of the SRAM. In a manner that a selected transistor and a resistor of the memory cell constitute a source follower circuit, the test device applies a voltage to each portion of the memory cell, applies an input voltage to a gate of the transistor constituting the source follower circuit, and inputs an output voltage outputted from a source of the transistor constituting the source follower circuit.

Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.

Abstract: A memory calibration method and system and a vehicle system are disclosed. The method includes reading a first set of data from a first memory, wherein the first set of data includes pre-stored parameters for calibrating a second memory comprising a controller; performing a first verification process on the first set of data; performing a second verification process on the first set of data when the first set of data passes the first verification process; adopting the first set of data to configure the controller of the second memory when the first set of data passes the second verification process; and performing a test for the second memory to determine whether finishing a current calibration process for the second memory, wherein the second memory has been calibrated when the second memory passes the test.

Abstract: A storage device includes circuitry and memory cells that store data in Np programming levels of threshold voltage values. The circuitry defines NRv threshold-sets, each includes Ns read thresholds that define Ns+1 zones, produces Ns readouts by reading, from a target WL, using the NS read thresholds, a target page that was stored encoded using an Error Correction Code (ECC), and produces a reference readout by reading the target page using optimal read thresholds. The circuitry identifies Np programming levels of memory cells in a neighbor WL for classifying target cells in the target WL into Np·NRv cell-groups. The circuitry calculates, per zone, Np LLR values, for the respective Np programming levels, based on the reference readout, the Ns readouts and the classification, assigns the LLR values to the target cells, and recovers the target page by applying to the assigned LLR values soft decoding for decoding the ECC.

Abstract: An operation method of a nonvolatile memory device includes receiving control signals and a data signal from external of the nonvolatile memory device, generating debugging information based on the control signals and the data signal, receiving a debugging information request from external of the nonvolatile memory device, and outputting the debugging information in response to the debugging information request.

Abstract: An inspection method for memory integrity, a non-volatile memory, and an electronic device are provided. The method includes following steps. A threshold voltage of at least one memory cell to-be-inspected in a non-volatile memory is obtained. A data value belonging to the at least one memory cell to-be-inspected is determined by comparing a read voltage and the threshold voltage. When the data value belonging to the at least one memory cell to-be-inspected is determined, a preset voltage is set according to the data value. An offset data value belonging to the at least one memory cell to-be-inspected is obtained by comparing the preset voltage and the threshold voltage of the at least one memory cell to-be-inspected. And, whether the data value and the offset data value belonging to the at least one memory cell to-be-inspected are the same is determined, so as to determine whether an integrity of the memory cell to-be-inspected is defective.

Abstract: Exemplary methods and apparatus are provided for read recovery in solid state devices (SSDs) with non-volatile memories (NVMs). In some examples, a dynamic priority read retry table (PRT) is generated for use with a static read retry table (RRT). In one aspect, a most recent successful read retry entry is determined from among the entries in the RRT. The most recent successful read retry entry is inserted as a first priority read retry entry within the PRT. A subsequent read recovery operation is performed using the first priority read retry entry of the PRT. In some examples, one or more neighboring values are selected for each entry in the PRT starting with the newest entry and proceeding chronologically to the oldest entry. The use of the PRT may help address die-to-die variations, block-to-block variations, or the transient changes that may occur in device physics within NVMs.

Abstract: A system and method are provided for memory control, having selectively distributed power-on processing. A memory controller executes responsive to a master control operation to actuate a plurality of operational tasks on a memory device. The memory controller includes a first power-on block executable to actuate one or both of initialization and training operations corresponding to the memory device. A PHY portion coupled to the memory controller portion executes to adaptively configure control, address, and data signals for physically compatible passage between the controller portion and memory device. The PHY portion includes a second power-on block executable to actuate one or both of an initialization operation and a training operation corresponding to the memory device. The PHY portion is configured according to the initialization and training operations, wherein each of the initialization and training operations are selectively actuated responsive to one of the power-on blocks.

Abstract: A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zigzag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write, circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.

Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.

Abstract: Systems and methods are provided for agentless error management by an agentless system. The agentless system can include a management processor and a memory that stores agentless management firmware. Execution of the firmware causes to obtain first graphic data corresponding to actual output graphics that are displayed via a display device. An error is detected in the actual output graphics. The error can indicate one or more differences between the actual output graphics and intended output graphics. The detected error can be addressed, such that it is remedied or attempted to be remedied by eliminating the differences and/or extraneous graphical content from the displayed data or actual output graphics.

Abstract: The present disclosure generally discloses improvements in computer performance for supporting automatic recovery for a remote management service (RMS) based on an RMS automatic recovery capability. The RMS automatic recovery capability may be configured to support automatic recovery for an RMS by supporting automatic recovery for a managed device that is experiencing a device authentication failure. The RMS automatic recovery capability may be configured to support automatic recovery for an RMS based on configuration of a load balancer of the RMS to recognize an authentication failure of a managed device and to trigger the managed device to enter a bootstrap process based on recognition of the authentication failure of the managed device. The RMS automatic recovery capability may be configured to support automatic recovery for an RMS based on configuration of a managed device to initiate a bootstrap process based on an indication from a load balancer of the RMS.

Abstract: An integrated circuit for a radio-frequency identification (RFID) tag is described. In an example embodiment, the integrated circuit (101) comprises: a memory (104) for storing data; a transceiver (107) for receiving signals from, and transmitting signals to, an antenna (102); and a controller (103) configured to process signals received via the transceiver (107) and to access data stored in the memory (104); wherein upon receiving, via the transceiver module (107), a lock command referring to a data block in the memory (104), the controller (103) is configured to perform a data integrity check on the data block to determine whether the data block is strongly stored.

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

Abstract: A method of operating a semiconductor memory device including a memory cell array and an error correction code (ECC) engine, wherein the memory cell array includes a plurality of memory cells and the ECC engine is configured to perform an error correction operation on data of the memory cell array, may include storing, in a nonvolatile storage, a mapping information indicating physical addresses of normal cells to swap with a portion of fail cells when a first unit of memory cells includes a number of the fail cells exceeding an error correction capability of the ECC engine. The first unit of memory cells of the memory cells may be accessed based on a logical address. The method may include performing a memory operation on the memory cell array selectively based on the mapping information.

Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to a dummy wordline load via a dummy wordline. The integrated circuit may include underdrive circuitry coupled to the dummy wordline between the dummy wordline driver and the dummy wordline load. The underdrive circuitry may generate an underdrive on the dummy wordline when the dummy wordline is selected and driven by the dummy wordline driver.

Abstract: A radio communication anomaly detecting method includes: gathering and storing different kinds of parameters indicating a radio quality with a sensor node in a storage unit; classifying parameter sets, each containing specific kinds of parameters gathered during a prescribed time period among the stored parameters, into clusters; estimating that a rapid radio quality degradation has occurred during the prescribed time period when there is a cluster of which all average values of specified kinds of parameters among the different kinds of parameters degrade more than those of another cluster; and performing a trend analysis for a time period during which it is not estimated that the rapid radio quality degradation has occurred to determine whether each of the different kinds of parameters gathered during the time period exhibits a trend of degradation, and estimating that a slow radio quality degradation has occurred based on a result of the trend analysis.

Abstract: An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.

Abstract: An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.

Abstract: A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.

Abstract: Receiving one or more first write commands to write a first set of data to a storage device. The first set of data is programmed in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells. One or more second write commands to write a second set of data to the storage device is received. The second set of data is programmed in the plurality of memory cells with which the first set of data is programmed. The second set of data is programmed using a second plurality of program levels available in the plurality of memory cells different from the first plurality of program levels. Each program level of the first and second pluralities of program levels is mapped to a respective bit pattern comprising three bits.

Abstract: A semiconductor chip includes a first circuit block configured to receive a first power supply voltage through a first power supply terminal of the semiconductor chip, a second circuit block configured to receive a second power supply voltage through a second power supply terminal of the semiconductor chip, and an alternative supply unit that is connected between the first power supply terminal and the first circuit block and receives the first power supply voltage through the first power supply terminal. The alternative supply circuit is configured to apply an alternative power supply voltage generated using the second power supply voltage to the first circuit block in response to a supply of the first power supply voltage being stopped.

Abstract: According to one embodiment, a storage system includes a first storage and a controller which controls the first storage. The first storage includes a first group which includes a plurality of pages which are data write units and include first nonvolatile memories, and a first counter which counts the number of data writes to the first group. The controller determines whether all the pages in the first group has been written to or not.

Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.

Abstract: A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold voltage can be adjusted by reading the memory at a current read threshold voltage to obtain a read value; applying a hard decision decoder to the read value; determining if the hard decision decoder converges for the read value to a converged word; storing bits corresponding to the converged word as reference bits and, if the hard decision decoder converges, (i) computing a bit error rate for the current read threshold voltage based on the reference bits; (ii) adjusting the current read reference voltage to a new read threshold voltage; and (iii) reading the memory at the new read threshold voltage to obtain a new read value, until a threshold is satisfied; and once the threshold is satisfied, selecting the read threshold voltage based on the bit error rates.