Abstract: A data protection method for damaged memory cells is provided. A power-on self-test (POST) is executed, and an initial backup memory is reserved in a memory. An operating system (OS) is executed, and data is loaded from a kernel region of the OS in the memory into a mirror region, so that when a processor accesses the data in the kernel region, it also accesses the data in the mirror region. An uncorrectable error (UE) is detected to determine a damaged page, and a backup page is selected from the initial backup memory or dynamically obtained from the OS to back up data in the damaged page. A mapping address of the damaged page and backup page are recorded into a page mapping table in a memory controller. Accordingly, when the OS accesses the damaged page, the memory controller accesses the backup page instead according to the page mapping table.

Abstract: A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read.

Abstract: A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

Abstract: Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.

Abstract: A non-volatile memory device and an operating method thereof are provided. The non-volatile memory device includes a memory unit including a plurality of memory blocks and a cam block, a peripheral circuit unit configured to program memory cells included in the plurality of memory blocks and the cam block or read programmed data, and a processor configured to control the peripheral circuit unit to measure an offset voltage by memory cell group in the plurality of memory blocks to set a read voltage during a test read operation and control the peripheral circuit unit to perform a read operation by memory cell group by using a new read voltage during a read operation.

Abstract: A read value that is read from a multi-level storage device is received, as are a set of bins having bin ranges. A set of amounts corresponding to the set of bins is received where each amount in the set indicates an amount of read values which fall into the corresponding bin. One or more of the bin ranges is adjusted, including by: in the event there is a first bin range that is less than the received read value, increasing at least the first bin range and in the event there is a second bin range that is greater than the received read value, decreasing at least the second bin range.

Abstract: A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.

Abstract: A test apparatus for testing a memory device including a memory cell. The test apparatus includes a storage and a controller. The storage stores a first value. The controller executes, at a given timing, determining a second value which is a threshold limit value to read data of the memory cell correctly on the basis of an output of the memory cell, calculating a difference between the first value and the second value, outputting a deterioration information on the basis of the difference between the first value and the second value, and updating the first value stored in the storage to the second value.

Abstract: An address signal generating circuit generates an address signal which designates the address in memory to be accessed. An inversion inhibition signal generating unit generates multiple patterns of inversion inhibition signals each having the same bit width as that of the address signal, and each having a function of preventing particular bits of the address signal from being inverted. A selector selects one of the multiple patterns of inversion inhibition signals generated by the inversion inhibition signal generating unit, and outputs the inversion inhibition signal thus selected. When an inversion control signal is asserted, an address signal inverting circuit inverts only the bits of the address signal which are not prevented from being inverted according to the inversion inhibition signal selected by the selector, and outputs the resulting address signal.

Abstract: Example methods, apparatus and articles of manufacture to diagnose temperature-induced memory errors are disclosed. A disclosed example method to diagnose a temperature-induced memory error includes detecting a memory error associated with a memory device, and writing a highest measured temperature of the memory device in the memory device when the memory error is detected, the highest temperature measured temporally near the detected memory error.

Abstract: Various embodiments of the invention pertain to a technique of recovering data from a portion of a non-volatile memory which was not reliably read because the number of read errors exceeded the ability of the ECC process to correct those errors. For each cell in that portion of memory, a quantized estimate is made of the amount of offset in the read reference voltage that is predicted to correct for any systematic noise that may have affected the reading of that cell. For each quantized offset, the read reference voltage is adjusted by that amount and data from the relevant cells is read. The combined results for all the cells are then processed through the ECC again.

Abstract: A resistance change memory device including a cell array, in which memory cells are arranged, the memory cell being reversibly set in one of a first data state and a second data state defined in accordance with the difference of the resistance value, wherein the memory device has a data write mode including: a first write procedure for writing the first data in the cell array; and a second write procedure for writing the second data in the cell array.

Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used.

Abstract: Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.

Abstract: A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Abstract: A method of screening manufacturing defects at a memory array may include programming a background pattern of physically inverse data along conductive lines extending in a first direction. The programming may include providing a program conductive line with a high value. The method may further include programming a memory cell at an intersection of the program conductive line and a conductive line extending in a second direction to a selected high value, and determining whether a cell initially at a low value and associated with a conductive line extending in the first direction and adjacent to the program conductive line is disturbed.

Abstract: Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times.

Abstract: Read error in a flash memory destroys data that is not requested to be read, and an efficient read disturb check method is therefore needed. In addition, data may be destroyed beyond repair by error correction before a read error check is run. A non-volatile data storage apparatus including a plurality of memory cells and a memory controller, in which the memory controller is configured to: count how many times data read processing has been executed in memory cells within the management area; read, when the data read processing count that is counted for a first management area exceeds a first threshold, data and an error correction code that are stored in the memory cells within the first management area; decode the read error correction code; and write the data corrected by decoding the error correction code in other management areas than the first management area.

Abstract: A storage medium reproducing apparatus includes a storage unit, a correction history storage unit, a correction history implementing unit, and a correcting unit. The storage unit includes a plurality of information storage units storing information depending on whether a charge quantity is greater than a predetermined charge quantity threshold value, and a correction code storage unit storing error correction codes for the information stored in the information storage units. The correction history storage unit stores a correction history containing identification information for the information storage unit corrected with an error correction code is performed, and a content of the correction. The correction history implementing unit corrects information in compliance with the content of the correction when the information is read from the information storage unit.

Abstract: In various embodiments, the reference voltage used for read operations in a non-volatile memory may be adjusted up or down in an attempt to read data from an area that previously produced at least one uncorrectable error. The direction and amount of this adjustment may be based on the number and direction of correctable errors in surrounding data.

Abstract: Memory performance in programmable logic is significantly increased by adjusting circuitry operation to adjust for variations in process, voltage, or temperature. A calibration circuit adjusts control signal timing, dynamically and automatically, to compensate real time to process, voltage, and temperature variation. A feedback system using a control block and a dummy mimicking concept are provided.

Abstract: A test apparatus comprising a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.

Abstract: The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened.

Abstract: A method for transmitting data from test device to a storage device via a parallel bus. The methods comprising the steps of setting a flag to indicate that data is available, reading the data, setting a flag to indicate the data was read. In addition test parameters are sent to the test device from the storage device, the method comprises the steps of checking to see if a test device is ready to receive data, transferring the test parameters, identifying the next channel to update.

Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used.

Abstract: A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.

Abstract: A technique for blind channel estimation is disclosed herein. A read value that is read from a multi-level storage device is received, as are a set of bins having bin ranges and (for each of the bins in the set) a corresponding portion of read values which fall into that particular bin. One or more of the bin ranges is adjusted such that the received portions of read values remain substantially the same after adjustment and after assignment of the read value to one of the set of bins after adjustment.

Abstract: A semiconductor memory apparatus includes: a first data counting unit configured to count respective programming levels of a plurality of input data and output a plurality of first data counting codes having a code value corresponding to the number of respective programming levels; a data read unit configured to sense data stored in a memory block having the plurality of input data programmed therein, based on a voltage level of a plurality of read bias signals, and output the sensed result as a plurality of output data; a second data counting unit configured to count respective programming levels of the plurality of output data and output a plurality of second data counting codes having a code value corresponding to the number of respective programming levels; a read bias control unit configured to compare the plurality of first data counting codes with the plurality of second data counting codes and output a bias control code having a code value corresponding to the comparison result; and a read bias genera

Abstract: An information processing system includes a dynamic random access memory, a processor for information processing in cooperation with the dynamic access memory, and a built-in diagnosis module including a longevity evaluation device, the longevity evaluation device comprising, a timer for measuring an elapsed time after data is entered into a memory device, a read controller for reading the data from the memory device when the elapsed time reaches a predetermined time, and an evaluator for evaluating a longevity of the memory device based on an existence of an error in the data read by the read controller and the elapsed time.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge; a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor mem

Abstract: A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.

Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Abstract: Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable.

Abstract: The invention provides a data read method. First, a training sequence stored in a storage unit of a memory is read according to at least one sense voltage to obtain a read-out training sequence. Whether the read-out training sequence is correct is then determined. When the read-out training sequence is not correct, the sense voltage is adjusted.

Abstract: An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state.

Abstract: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a capacitive storage circuit is operated at a threshold voltage that is set to provide sufficient power to operate backup functions of a data storage device, and that is further selectively adjusted during a test period to maintain such sufficient power while also providing power to carry out test functions. In other implementations, the threshold voltage is set in response to operating characteristics of one or more of a data storage device to which backup power is to be provided and the capacitive storage circuit itself. The threshold voltage is reduced or otherwise maintained at a low level that is yet sufficient to supply appropriate power (e.g., thus maintaining the capacitive circuit at a voltage level that is about as low as possible, which can enhance operational characteristics of the capacitive circuit).

Abstract: A semiconductor device includes a memory module provided with a plurality of memory cells, a verify determination unit that performs quality determination of read data that have been read from the memory cells on the basis of the read data and an expected value prepared in advance, and a power source monitoring circuit that detects fluctuations equal to or greater than a predetermined variation rate in a power source voltage supplied to the memory module and outputs a power source abnormality detection signal. Furthermore, the verify determination unit invalidates a result of the quality determination when the power source abnormality detection signal indicates an abnormal state of the power source voltage.

Abstract: A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as well, deleting the documentation data relating to the over-programmed bits.

Abstract: A storing apparatus, equipped with a control unit configured to control the writing of data into a memory and to communicate a notice to an external device with a communication unit if the remaining amount of substitute blocks becomes equal to or less than a threshold value specified by stored threshold value information, includes the control unit configured to change the threshold value information, used for the notice communicated by the control unit, by the use of threshold value information received from the external device with the communication unit.

Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.

Abstract: A method includes receiving location area-related information, associating the location area-related information with a neighbor cell information to determine if a cell belongs to a forbidden location area, and avoiding selection of the cell if the cell is determined to belong to the forbidden location area. Embodiments described include a UE, network element, computer program product, and integrated circuit.

Abstract: A PC BIOS can contain an early memory test that can identify a memory slot containing a bad memory. The BIOS can also contain a program module for using a communications port to report the identified memory slot. The communications port used for reporting is one that can be used without using system memory. In fact, the communications port can be used when there is no system memory installed in the PC. The parallel ports, LPT1 and LPT2 are such communications ports, as are the serial ports COM1 and COM2. An indicator can be electrically connected to the communications port to give a visual indication of a memory slot containing bad memory.

Abstract: Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations include one with possible data and another that is empty. Determining which of the two, if at all, have experienced brownout includes using two different sense references. One has a higher standard for detecting a logic high and the other higher standard for detecting a logic low. Results from using the two different references are compared. If the results are the same for both references, then there is no brownout. If the results are different for either there has been a brownout. The location with the different results is set to an invalid state as the location that has experienced the brownout.