Abstract: This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a clock, a save and a restore signal, and a plurality of serially connected data latches receiving the clock, save and restore signals, wherein each data latch employs one of the plurality of state retention circuits, wherein the plurality of data latches save their existing data in their corresponding state retention circuits upon an assertion of the save signal, restore the data from the plurality of state retention circuits back to their corresponding data latches upon an assertion of the restore signal, and shifting the existing data along the series of the data latches one latch a cycle of the clock signal.

Abstract: A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected serially to a number of LBIST stumps (pattern segments) between a pseudo-random-pattern generator (30) and a multiple-input-signature register. The semiconductor chip is subdivided into partitions, such that LBIST cycles may be run separately or in parallel for one or more partitions. The LBIST cycles may also be run separately or in parallel inter-connections between the partitions. The partitions to be tested are controlled by at least one corresponding clock signal, and the inter-connections to be tested are controlled by at least one corresponding clock signal.

Abstract: A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.

Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

Abstract: A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

Abstract: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Abstract: A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or interleaved loading techniques in order to minimize instantaneous power requirements. During interleave loading, the LBIST controller loads a scan bit into a first scan chain, then into a second scan chain, etc. until one bit is loaded into each scan chain. The LBIST controller then returns to load another scan bit into the first scan channel, then the second scan channel, etc. During sequential loading, the LBIST controller loads an entire scan pattern into a first scan chain (one bit per clock cycle). Once the first scan pattern is loaded, the LBIST controller proceeds to load subsequent scan patterns into corresponding scan chains on a one bit per scan channel per clock cycle basis.

Abstract: The present invention relates to a system and method for selecting one of plurality of PRBS generators for use with a modem. The modem includes a measuring device adapted to measure an operating environment of the modem; and a storage device adapted to store a list of PRBS generator definitions. The modem selects one of a plurality of PRBS generators based on the measurement of the operating environment.

Abstract: A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift register; a phase shifter connected to outputs of the linear feedback shift register, and scan chains and the combinational part of the circuit under test; an AND gate; scan chains, each being formed by serially connecting multiple scan flip-flops having the same architecture; a multiplexer; and a logic unit for generating weighted random signal, whose inputs are connected with the phase shifter; the logic unit randomly selects the input pseudo random signals, weights the selected pseudo random signals, and assigns the weighted pseudo random signals assigned to the scan enable signals of the scan chains, to control the switching of the scan chains between the scan shift mode and the functional mode. The test effectiveness of scan-based BIST can be improved greatly using the test scheme with weighted scan enable signals.

Abstract: A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.

Abstract: A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a parameter of the DUT to a first value and applies a test stimulus to the DUT, and (b) sets the parameter of the DUT to a second value and applies the test stimulus to the DUT. A change in the value of the parameter results in a change in the amount of heat dissipated by the DUT. The temperature controller maintains the DUT at a pre-determined temperature during testing with the parameter set to both the first and the second values. The DUT may be further coupled to a module that comprises circuitry employed in a product-level application environment. The module is configured by the test controller to simulate a product-level application.

Abstract: The invention relates to an electronic circuit including a sub-module assembly (2) connected to the rest of the circuit, the sub-module assembly including a secret sub-module (4) for performing a function, scan chains; a built-in self test circuit including a pattern generator (5) to apply input signals to the scan chains, and a signature register (6) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.

Abstract: A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and pseudo-random pattern generator (PRPG) circuitry, are tested. Controlled by the LBIST control logic, PRPG inputs a test pattern into scan chains within the cores of each device. A new test pattern is generated and executed during the scan shift phase of each LBIST loop. Logic output generated by each scan chain in the core is compared to other core logic output. Failures within the multi-core processors are determined by whether the logic output generated from a core, within a latch sequence, does not match the logic output of the other cores. If logic output, from a core within a latch sequence, does not match, then the latch number, loop number, and latch values are recorded as failed.

Abstract: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

Abstract: A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the user control of the pattern generator to compensate for tool and/or device under test latency timing issues. Inputs may be combined and processed into one contiguous pattern of vectors which are definable by the user.

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Abstract: A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

Abstract: A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to at least one of a plurality of decoders, wherein each decoder is adapted to recognize the coding scheme represented by one of the bit patterns.

Abstract: A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From the first set of code words, a second set of code words is selected. The number of code words in the second set is equal to said number of wiring interconnects, and the selection of the second set of code words is such that the sum of the transition counts for the code words in the second set is minimized.

Abstract: A tester and method are provided for testing semiconductor devices. Generally, the tester includes a multitasking Algorithmic Pattern Generator (APG) to concurrently execute multiple programs on multiple test sites using a single pattern generator. In one embodiment, up to eight test programs are run independently and concurrently on eight independent sixteen-pin devices on a 128 pin test site. When the multitasking APG is ready to broadcast to a device, timing system associated with that device only (and not the other devices) are loaded. While the timing system is executing the cycle of the test programs for the device just loaded, the APG continues on to load the other devices. Because of the slow cycle rates required for programming versus reading, the tester is particularly advantageous for testing flash memory. Optionally, for higher throughput, the APG can be run in lock step at up to a maximum operating frequency of the APG during read cycle of flash.

Abstract: A device and a method for forming a signature, a predefined number of shift registers being provided, to which input data to be tested is applied bit-by-bit and in parallel as successive data words and which serially shift the input data forward in a predefinable cycle, a signature being formed in the shift registers after a certain number of data words and cycles, a code generator which generates at least one additional bit position in at least one additional shift register from each data word in the signature also being provided.

Abstract: A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

Abstract: A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

Abstract: A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.

Abstract: Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.

Abstract: Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

Abstract: A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together, within said chip design, to form clock domain groups. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design and by-pass, within the chip design, the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.

Abstract: The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.

Abstract: The design support system regarding the present invention comprises a node data storage means that stores node data to generate functional models which present a group of function nodes which are functions divided from performance function of apparatus which is an objective to be designed and a group of part nodes which realize the functions in mutual relations, a functional model generating means that generates the functional models in reference to the node data storage means, a node designation receiving means that receives the designation of a node among the functional models, a node selection means that selects a node which has a mutual relation with nodes to which the designation are given, a display unit that displays the node selected by the node selection means.

Abstract: A check matrix generating apparatus calculates a parameter for pseudo-random-number permutation matrices using a predetermined information length, a coding rate, and a maximum column degree, generates the pseudo-random-number permutation matrices from the calculated parameter for the pseudo-random-number permutation matrices by using a pseudo-random-number sequence and a Latin square matrix, determines, as a parameter, a combination of degree distributions which can be adopted for optimization of a degree distribution of generation of a check matrix which can be formed with the pseudo-random-number permutation matrices, using the predetermined information length, coding rate, and maximum column degree, optimizes the degree distribution of generation of a check matrix under a restriction condition based on the determined combination of degree distributions which can be adopted, and arranges the generated pseudo-random-number permutation matrices according to the optimized degree distribution of generation of t

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: Representative embodiments are generally directed to storing compressed test pattern data on an automated test equipment (ATE) device. In one embodiment, the test pattern data is compressed according to a linear feedback shift register (LFSR). The LFSR may possess a low probability of occurrence of linear dependencies associated with compression of stimulus patterns to enable relatively highly compacted patterns to be compressed. Additionally or alternatively, repeat-filled test pattern data is run length encoded using variable length code words to facilitate parallel decompression within the ATE device.

Abstract: A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals are combined to produce a combined signal. The combined signal is transmitted over a communications channel of a memory system and is received by the memory devices of the memory system. Each memory device removes the second signal from the received combined signal to produce a received first signal. Parameters associated with transmitting and receiving may be adjusted by examining the pattern of the received first signal to determine if it has the known pattern of the first signal. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Provided is a method of forming reference information for defining a fault pattern of equipment, and monitoring equipment. One example embodiment method may include performing an angle spectrum analysis by re-classifying fault points distributed on a plane, the plane including a first component axis and a second component axis, and the re-classifying fault points including calculating an angle for each of the fault points with reference to any one of the first component axis and the second component axis of the plane, and forming a reference fault pattern for defining a fault pattern of the re-classified fault points.

Abstract: A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is injected into the virtual IC to trigger hardware error correction in the virtual IC and a software exception. A record of a type and a location of the soft error at the time of the injecting is created. The error log generated by hardware error correction is then compared with the record of injected error, the hardware error correction being part of the virtual IC. An IC design flaw is indicated when a discrepancy exists between the error log and the record of the injected error.

Abstract: The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise generators. A first embodiment of this invention includes a plurality of serially connected transition matrix multiplication circuits producing a plurality of output state matrices. A second embodiment of this invention combines a first stage having plurality of matrix multiplication circuits connected to a first multiplexer circuit which selects an state matrix or one of the matrix products with a serial chain of matrix generator circuits including second matrix multiplication circuit and a second multiplexer selecting either a first input or the output of the second matrix multiplication circuit.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: A semiconductor integrated circuit includes plural shift registers that receive plural test patterns randomly generated, respectively, a mask device that masks, among the shift registers, a target shift register specified by a mask pattern randomly generated. When a shift register other than the target shift register outputs an unknown value, the mask device masks the shift register according to a control signal. When the target shift register outputs a fault value, the mask device releases a mask of the target shift register according to a control signal.

Abstract: A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the conclusion of an execution epoch.

Abstract: The present invention relates to the fast code acquisition methods based on signed-rank statistic. In more detail, it presents novel detectors required for PN (PN) code acquisition in DS/SS system. In accordance with the present invention, first, the LOR (LOR) detector is derived and then the LSR (LSR) and MSR (MSR) detectors using approximate score functions are proposed. It is compared the single-dwell scheme without the verification mode using the proposed LSR and MSR detectors with that using the conventional squared-sum (SS) and modified sign (MS) detectors.

Abstract: A semiconductor module with a plurality of interface circuits has a configuration for the self-test of interface circuits, with two equally sized groups of interface circuits such that each interface circuit of the first group is assigned exactly one interface circuit of the second group. A circuit interacts with the first group and serves for generating test signals which can be output via the interface circuits of the first group. Another circuit interacts with the second group and serves for receiving and processing test signals received via the interface circuits of the second group, so that a connection of the assigned interface circuits of the first and second groups enables a self-test, the first and second groups of interface circuits having a separate voltage supply. This enables good test coverage by separate variation of the voltage of transmitting and receiving group.

Abstract: A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is crated for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.

Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.

Abstract: A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.