Abstract: Synchronization errors in a received pulse train are detected by detecting rising or falling transitions in the pulse train, generating numbers in a repeating cycle having a length corresponding to the pulse rate, selecting the number generated when each transition is detected, and performing a predetermined operation on the selected numbers. The predetermined operation may include, for example, comparing the average values of the selected numbers in successive groups of transitions. Alternatively, the predetermined operation may include taking a difference between consecutively selected numbers to measure pulse widths in the pulse train. Synchronization error detection can be used to supplement data error detection and correction methods such as forward error correction and cyclic redundancy checks.

Abstract: In an apparatus for analyzing a magnetic random access memory (MRAM), and a method of analyzing an MRAM, the apparatus includes an MRAM mounting unit on which an MRAM is mounted, a magnetic field applying unit positioned around the MRAM mounting unit for applying an external magnetic field to the MRAM mounted on the MRAM mounting unit, a cell addressing unit for selecting one of a plurality of unit cells of the MRAM mounted on the MRAM mounting unit, a source measurement unit for applying an internal magnetic field to the selected unit cell of the MRAM or for measuring a resistance of the selected unit cell of the MRAM, and a computer unit for storing and for analyzing data regarding the measured resistance of the each of the plurality of unit cells of the MRAM.

Abstract: A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

Abstract: A voltage margin testing blade is adapted for use in a bladed server having at least one internal adjustable power supply. The testing blade is further adapted to provide a control signal to the power supply indicative of any desire to modify the output voltage of the power supply. The testing blade senses the output voltage of the power supply and compares it to a desired power supply voltage. The control signal is generated in response to this comparison in order to control the actual power supply voltage at or about the desired power supply voltage.

Abstract: Methods are described herein, for improving the accuracy of propagation delay measurements of programmable electronic devices in a production environment. In one method, a built-in self-test is implemented by configuring an oscillator and a counter connected to each other within the PLD. The oscillator is enabled to oscillate for a pre-determined length of time and to cause the counter to count up at the end of each cycle of oscillation. The counter reading is correlated to an accurate propagation delay measurement by using a previously generated counter-delay correlation curve. In other methods, the counter is built outside of the logic of the PLD. Methods are described for adapting typical output macro cells to provide combinatorial feedback for configuring oscillators within PLDs without such capabilities.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers 15A through 15D whose output values change when boundary scan cells 13E through 13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.

Abstract: Systems and methods for performing module-based diagnostics are described. In an exemplary embodiment, sensor values from an actual engine plant are input to an engine component quality estimator which generates performance estimates of major rotating components. Estimated performance differences are generating by comparing the generated performance estimates to a nominal quality engine. The estimated performance differences, which are indicative of component quality, are continuously updated and input to a real-time model of the engine. The model receives operating conditional data and the quality estimates are used to adjust the nominal values in the model to more closely match the model values to the actual plant. Outputs from the engine model are virtual parameters, such as stall margins, specific fuel consumption, and fan/compressor/turbine efficiencies.

Abstract: A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.

Abstract: A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence.

Abstract: A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refreshing DRAM includes a test-mode enable circuit, an arbitration circuit, and a memory control logic circuit. In a normal mode of operation, the test mode enable circuit is not active. In a test mode of operation, the test mode enable circuit is active which enables the memory control logic to be controlled by an external command signal that is provided through an external pin, such as a chip-enable /CE pin when the chip is in the test mode.

Abstract: An invention is disclosed for determining integrated circuit (IC) logic speed. A storage element is provided that includes a reset input in electrical communication with a reset pin. A reset signal is then asserted at the reset pin, and a reset time is measured. The reset time is defined as the time period beginning when the reset signal is asserted and ending when the storage element resets. In this manner, the reset time can be used to determine a speed of the IC logic relative to a process. In one aspect, delay logic is provided that is in electrical communication with the reset pin and in electrical communication with the storage element. In this aspect, the delay logic delays the reset signal for a predetermined time period. Optionally, the reset time can be compared to a predetermined fast corner reset time and a predetermined slow corner reset time. Further, the IC logic speed can be correlated to a simulation using the embodiments of the present invention.

Abstract: An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference voltages by a voltage margin.

Abstract: A system for testing an integrated circuit, the integrated circuit including: flip-flops connected to a logic block and the test system including circuitry for connecting the flip-flops as a register, circuitry for inhibiting the different elements of the logic block capable of disturbing the sequencing of the register or the propagation of the signals into the logic block, and a control circuit for separately controlling the different inhibiting circuits and the circuitry for connecting the flip-flops as a register.

Abstract: Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.

Abstract: A method for testing a semiconductor memory device includes forcing the device into a logic state configuration that does not occur during normal operation of the device. The method may also include holding the logic state configuration for a user-variable length of time. In an embodiment, the device testing method includes flowing a direct current through a first input node of a bi-stable latch. This node may be electrically arranged between a node coupled to a voltage source and a node coupled to a circuit ground potential. An embodiment of a memory device may include testmode circuitry adapted to maintain a pair of bitlines at logic states that are not maintained during ordinary operation of the device. A system for testing a semiconductor memory device may include testmode circuitry adapted to force a pair of bitlines to the same logic state for a user-determined length of time.

Abstract: A method and circuit thereof for performing setup and hold (SUAH) testing on integrated circuits including, but not limited to SRAM, utilizing a relatively low number of test vectors, obviating the conventional requirement of writing to and reading back from each and every memory address. In one embodiment, a first test data signal of all zeros (0) is inputted to the input stage of the SRAM under test, and a subsequent second data signal of all ones (1) follows. In one embodiment, XOR/XNOR gates detect differences in data signals between the inputs and outputs of input stage latches/registers after clocking. In one embodiment, detected differences are combined into an error signal in combinational logic. In one embodiment, error signals are exported serially to a test system by a scan chain. Alternatively, in another embodiment, error signals are exported in parallel via individual output drivers.

Abstract: A buffer circuit is provided having a driver device and an input device to receive a first set of signals and to produce a second set of signals. The driver device may receive the second set of signals and output a third set of signals based on the second set of signals input to said driver device. A comparing device may receive the third set of signals from the driver device and produce a fourth set of signals based on the third set of signals, the comparing device may compare the fourth set of signals with the first set of signals.

Abstract: A fault detection system detecting malfunctions or deteriorations, which may result in an inverter fault, is provided. The system has a temperature sensor installed on a semiconductor module to monitor a temperature rise rate. It is judged that an abnormal condition has occurred if the thermal resistance is increased by the deterioration of a soldering layer of the semiconductor module or by drive circuit malfunctions and, as a result, the relation between an operation mode and the temperature rise rate falls outside a predetermined range.

Abstract: In one embodiment, a method is provided. In the method of this embodiment, a first range of amplitudes may be selected from a plurality of ranges of amplitudes. The first range of amplitudes may include a first amplitude of a signal received via a communication medium. The method of this embodiment may also include selecting a second amplitude of a signal to be transmitted via the communication medium. The second amplitude may be included in a second range of amplitudes included in the plurality of ranges of amplitudes. The second amplitude may be selected based, at least in part, upon the selected first range of amplitudes. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A voltage margin testing blade is adapted for use in a bladed server having at least one internal adjustable power supply. The testing blade is further adapted to provide a control signal to the power supply indicative of any desire to modify the output voltage of the power supply. The testing blade senses the output voltage of the power supply and compares it to a desired power supply voltage. The control signal is generated in response to this comparison in order to control the actual power supply voltage at or about the desired power supply voltage.

Abstract: A method of testing a semiconductor device begins by reading test information into a testing apparatus. The test information is used to determine whether to perform a normal test or a fuzzy test depending on fuzzy conditions. The order of test items included in the normal test can be changed based on defect rates. And the test items to be included in the fuzzy test can be determined by selecting one or more test items from among the normal test items. The fuzzy conditions can be satisfied if the number of consecutive products that have passed the test is greater than a first value or the number of consecutive products that have failed the test is less than a second value. The test can be automatically switched between the normal test and the fuzzy test, thereby minimizing the time taken to test a semiconductor device.

Abstract: A tool and method for increasing fault coverage of an integrated circuit. The tool includes a key nodes detection device for matching key nodes to a fault grading report list of undetected nodes, a multi-sites selection device for reading a layout file of available multi unit sites for the integrated circuit, a site matching device for matching available multi-unit sites to key undetected nodes, and a netlist generation device for building logic functions in the available multi-unit sites for connection to the key undetected nodes. Use of the invention enables increased fault coverage of integrated circuit circuits for little or no added expense.

Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.

Abstract: A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state.

Abstract: An interrupt signal EMG is put out to microprocessor 10 when package temp. is detected by thermal monitor 40 that it exceeded reference temp. Thus, rewriting of frequency division value N of freq.div.val.register 31 in clock gear mec. 30 to increase it is performed by microprocessor 10. In frequency division circuit 32, inputted clock signal MCK is divided into 1/N by freq.div.value N set in freq.div.val.register 31, so as to generate system clock signal SCK. Therefore, frequency of system clock signal SCK decreases with the increase of freq.div.value N. Consequently, electricity consumption of each module 20i decreases, increase of package temp. is restrained, and malfunction from overheat can be prevented.

Abstract: To make it possible to locate a physically abnormal portion such as low-resistance short-circuiting between signal wirings or an open fault in a CMOS logic circuit without any design information, in a fault portion locating method for a semiconductor integrated circuit device, a first information table showing a correspondence between a physical abnormality and a defined abnormal IDDQ change mode is prepared in advance, a second information table showing a relationship between a model of the physical abnormality and a change of a light emitting element for the IDDQ abnormal pattern in an operation test pattern by emission analysis is prepared in advance, and in fault analysis, the tables are compared with the abnormal IDDQ obtained from the actual integrated circuit and the change of the light emitting element, respectively, to locate a physically abnormal portion.

Abstract: An apparatus and method for determining a minimum clock delay provided to sense amplifiers of a memory array. The method first determines a response time of the overall memory circuit by varying the delay of an external clock until the output of the memory circuit is just valid. Then an externally provided sense amplifier clock is substituted for the internal sense amplifier clock and the instant of application of the externally provided sense amplifier clock is varied until the circuit output is just valid.

Abstract: A sensor in an engineering system can be tested to detect, isolate and accommodate faults. Initially, a modeled sensor value of each actual sensor value is generated as a function of a plurality of other sensors. An absolute value of a difference between the actual sensor value and the modeled sensor value is then computed and compared to a predetermined threshold. A sensor fault is detected if the difference is greater than the predetermined threshold. Once a sensor fault is detected, it is isolated using hypothesis testing and maximum wins strategies. After the fault is isolated, the fault is accommodated by substituting the modeled sensor value for the actual sensor value.

Abstract: A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.

Abstract: A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control signal controls when the integrated circuit (10) is in test mode. The test mode detector (12a) further includes a latch (27) that is responsive to the pulse detector (25) so as to set the latch (27) when the pulse detector (25) detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit (10) in test mode for a period of time that is greater than the duration of the pulse of the control signal.

Abstract: A method and apparatus for detecting disk drive head instability. Normal head fluctuation is removed from the criterion used to detect whether a head is unstable. The present invention accumulates error signals in an accumulator and calculates a criterion having an average fluctuation removed using the accumulated error signals. The criterion is calculated according to (max+min)−(2×average), wherein max is the maximum error signal, min is the minimum error signal and average is the average error signal. The criterion is then compared to a predetermine threshold to determine whether the head is unstable. A head is determined to be unstable when (max+min)−(2×average) is greater than the predetermined threshold.

Abstract: A receiver in a digital communications system, in which the digital data occupy a number of levels, equalises the erroneous-count rates for the various data levels by deriving the count rates for the levels, comparing these count rates with each other and using the comparison result to adjust the threshold level which is used to detect the received data train. The error-counts are preferably derived as a byproduct of a Forward Error Correction system already available for performing normal error correction on the received data. The receiver arrangement is envisaged to find predominant application in a two-level system involving logical “1”'s and “0”'s, though it is applicable also to systems with three or more levels.

Abstract: A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit, provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state.

Abstract: A HASS testing system provides for testing and tuning of a bus system of an electronic device having a bus interface coupled with a bus characterized by a number of parameters.

Abstract: A method of generating a vector set, said vector set being used for testing sequential circuits. The method comprises selecting a plurality of fault models, identifying a fault list each for each of said plurality of fault models, identifying a vector set each for each of said fault lists, selecting a tolerance limit each for each of said fault lists, thereby each fault model having an associated fault list, an associated vector set and an associated tolerance limit, compacting each of said vector set such that the compacted vector set identifies all the faults in the associated fault list or a drop in fault list coverage is within the associated tolerance limit; and creating a vector set by combining all vector sets compacted. A system and a computer program product for testing circuits with a compacted vector set where the compacted vector set is created by dropping faults based on a tolerance limit.

Abstract: A semiconductor integrated circuit device, which has an internal circuit that operates during a normal operation on the basis of a reference signal and input signals supplied from the outside of the device. A detecting circuit detects the voltage level of the reference signal. When the detecting circuit has detected that the reference signal is at a predetermined voltage level that differs from a voltage level assumed during the normal operation, a transfer circuit transfers an internal signal in the internal circuit to the outside of the device, instead of the regular output signal of the internal circuit.

Abstract: A method and circuit to test for defects in the input path of an integrated circuit by providing a logic pattern data to a scan chain of the integrated circuit and testing setup and hold timing parameters. The method including determining a maximum value for a timing parameter and generating a data pattern with the timing parameter having the maximum value. The method also including monitoring an output of a logic function performed on the data pattern and adjusting the value of the timing parameter based on the output of the logic function.

Abstract: A circuit for programmably grounding (or coupling to the positive rail) unused outputs to improve noise immunity of the circuit. The circuit of the present invention achieves, for example, programmable grounding of an output via already existing test signal paths, without introducing delays in speed critical output signal paths.

Abstract: A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control signal controls when the integrated circuit (10) is in test mode. The test mode detector (12a) further includes a latch (27) that is responsive to the pulse detector (25) so as to set the latch (27) when the pulse detector (25) detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit (10) in test mode for a period of time that is greater than the duration of the pulse of the control signal.

Abstract: A circuit for parametric testing of I/O's including bidirectionals includes logic which ties the I/O's into a single test chain. A pulse is applied moved down the chain to test the switching levels of the input buffers and the output buffers. The circuit features the ability to program the bidirectionals as either inputs (test mode 1) or outputs (test mode 2) and so allows for its input and output buffers to be tested. The test mode can be selected simply by writing to an externally accessed data register.

Abstract: A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control signal controls when the integrated circuit (10) is in test mode. The test mode detector (12a) further includes a latch (27) that is responsive to the pulse detector (25) so as to set the latch (27) when the pulse detector (25) detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit (10) in test mode for a period of time that is greater than the duration of the pulse of the control signal.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: A semiconductor integrated circuit for suppressing power consumption is provided. In the case where an internal signal should be monitored from outside the circuit, an output control circuit outputs the same value as that of the internal signal from each of external terminals. In the case where the internal signal does not need to be monitored, e.g., in the same manner as ordinary user's use, the output control circuit outputs an invariable value from each of the external terminals. Thus, in the case where the internal signal does not need to be monitored, the invariable value is outputted. Consequently, power consumption can be suppressed.

Abstract: An IC tester enabling the performance of the decision of the conditions of output signals of the device under test in a period of time having a predetermined time interval between two decision trigger signals, thereby providing the IC tester capable of deciding the conditions of output signals of the device under test in a scope wider than that of the conventional IC tester. If the output voltage of each device under test is higher than a high reference voltage, it is decided that each device under test outputs a high signal while if the output voltage of the each device under test is lower than a low reference voltage, it is decided that each device under test outputs a low signal. If the output voltage of each device under test is lower than the high reference voltage but higher than the low reference voltage, it is decided that the output of each device under test is in high impedance.

Abstract: A system and method for conducting a repeatable logic test on at least one functional unit of an IC chip includes steps of selecting at least one functional unit of at least several functional units, propagating test data through a part or all functional units of the time domain; and capturing test data of the selected functional unit. The functional units are either selected or held inactive such that only the selected functional unit is allowed to capture the test results for determining a critical timing path within the selected functional unit and only the functional unit. By selecting different combination of the functional unit(s), a number of the critical timing paths are readily determined in the chip.

Abstract: A method for early failure recognition in power semiconductor modules which employs a measurement across a resistor between a bonded emitter terminal and a bonded auxiliary emitter terminal that identifies the degradation of the bond point which triggers an early warning signal so that the power semiconductor module can be changed before failure and the overall reliability of an electronic power system can thereby be increased.

Abstract: A method for verifying correct operation and functional stability of a tester for semiconductor devices is disclosed. In addition, a method for creating a standard device for use with the tester is also disclosed. In creating a standard device according to the present invention, the tester repeatedly tests a candidate device a predefined number of times and evaluates the test results to determine whether the candidate device is suitable for use as a standard device. In verifying the operation and functional stability of a semiconductor device tester, data generated by repeatedly testing a standard device a predefined number of times are compared to recorded reference data of previous tests of the standard device.

Abstract: A system and method for identifying long paths in an integrated circuit are described. An integrated circuit chip is subjected to input test signals of progressively shorter cycle time until the chip fails to produce a correct output. The cycle time of the signal resulting in the failure of the chip is defined as T. A signal having cycle time T'=T+.DELTA.T is then applied to the integrated circuit, where the signal of cycle time T' is known to result in proper operation of the chip. The chip is then observed for switching activity during the period .DELTA.T which occurs beginning at a time T measured from the beginning of the second signal of duration T' until the end of the signal of duration T'. The location of the switching activity is used to identify the path or paths of the circuit that resulted in failure of the chip. In a preferred embodiment of the invention, the switching activity is detected using an optical measurement system capable of detecting light generated by transistor switching activity.