Abstract: A video error/distortion checker generates a difference signal from an input repetitive digital signal and a reference data signal corresponding to the input repetitive digital signal. The difference signal is compared with maximum and minimum threshold values to generate an error signal when the difference signal exceeds either threshold value. The difference signal also is used to generate a running range value that is compared with a total range value to produce the error signal when during one iteration of the repetitive digital signal the difference signal exceeds a specified range defined by the total range value. The error signal is suitably displayed, either visually or alphanumerically or both, so that an operator may recognize the type, severity and location of errors in the repetitive digital signal.

Abstract: A power-on reset circuit with glitch sensing capabilities is formed as part of the same integrated circuit chip containing other logical circuits. A port included in the integrated circuit chip enables a power-on reset signal generated by the integrated power-on reset circuit to be output from the chip and applied to other chips installed in a single chip or multi-chip electronic system. The power-on reset circuit compares a capacitor stored reset voltage to a reference voltage and outputs the power-on reset signal when the reset voltage falls below the reference voltage. Storage of the reset voltage by the capacitor is controlled by a glitch sensor which detects changes in voltage provided by a power supply in excess of a given threshold and, in response thereto, triggers a capacitor discharge. This causes the reset voltage to fall below the reference voltage, and the power-on reset signal to be output.

Abstract: Method and apparatus for reducing the time required to test an integrated circuit (10) using slew rate control. Using a very slow slew rate during normal operation may reduce electromagnetic interference, while using a faster slew rate during testing may reduce the test costs. In one embodiment, terminal control circuitry (40) includes a fast test control bit (50) to select a slow slew rate during normal operation, to select a faster slew rate during functional testing, and to optionally select a variety of slew rates during a special test to more fully characterize the behavior of integrated circuit (10). In one embodiment, each pre-driver circuit (80, 81) includes a low resistance device (61, 63) which may be selectively enabled or disabled to join with capacitors (66, 67) in output driver (82) to affect the slew rate of the signal driven as an output by integrated circuit terminal (83).

Abstract: A method and apparatus for locating a critical speed path in an integrated circuit. The apparatus comprises a plurality of controllable clock drivers each coupled to a circuit block of the integrated circuit. The apparatus also comprises a plurality of clocked storage devices each coupled to one of the controllable clock drivers and including a clock input, a data input and a data output. Test circuitry that operates with joint test action group (JTAG) compatible protocol is coupled to the plurality of clocked storage devices and generates a signal that controls the plurality of controllable clock drivers.

Abstract: An ordinary user can easily learn a step at which a problem occurs during semiconductor manufacturing processes and improve the yield of manufacturing products and the quality of the products. At a certain in-line inspection step, a CPU (3) stores data signals (V1) taken by an inspection apparatus (1) into a memory (2), and reads a result (V6) obtained at a precedent step and stores the same in the memory (2). The CPU (3) reads stored data signals (V2) from the memory (2), performs comparison or referral on data about defects which are detected at a current step and the result (V6) regarding the precedent step, and generates a defect data analysis processing result signal (V5) regarding the current step. The result (V5) consists of disappeared defect data, common defect data, new defect data to which a label of a current step number is assigned, and reappeared defect data.

Abstract: A data transfer system has a PC as a host computer, a terminal unit such as a printer and a parallel interface cable through which data is transferred between the PC and the terminal unit. The PC transfers a strobe signal as a rate detection signal which contains points of change to the terminal unit. The terminal unit receives the strobe signal and calculates the data processing rate of the PC on the basis of the points of change of the strobe signal. The PC adjusts the data transfer rate of the PC on the basis of a result of comparison of the data processing rate of the PC calculated by the terminal unit and a processing rate of the terminal unit.

Abstract: For use in a module, a redundancy detection circuit for, and method of, determining whether a predetermined adequate redundancy exists when the module is present in a system. In one embodiment, the module includes: (1) a sensor, associated with the module, that receives a signal that is a function of a number of modules present in the system and (2) a calculation circuit, coupled to the sensor, that determines from the signal whether a surplus capacity of the module provides at least the predetermined adequate redundancy for the system.

Abstract: A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control signal controls when the integrated circuit (10) is in test mode. The test mode detector (12a) further includes a latch (27) that is responsive to the pulse detector (25) so as to set the latch (27) when the pulse detector (25) detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit (10) in test mode for a period of time that is greater than the duration of the pulse of the control signal.