Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: The codec includes an encoding/decoding operation module and a basic matrix storage module. In the stored basic matrix Hb, for all girths with length of 4, any column element of i, j, k or l constituting the girths in anti-clockwise or clockwise always satisfies inequality: (i?j+k?1) mod z?0, wherein z is the extension factor. When generating the basic matrix, firstly the number of rows M, number of columns N, and weight vectors of the rows and columns are determined, an irregularly original basic matrix is constructed; then the position of ‘1’ is filled by a value chosen from set {0, 1, 2, . . . , z?1} to obtain the basic matrix Hb. The basic matrix Hb obtained by storing constitutes the desired encoder/decoder. The encoder/decoder according to the present invention can effectively eliminate error-floor phenomenon of LDPC codes and accelerate the falling speed of BER curve.

Abstract: Method for transmitting data in a transmission system, the data being transmitted in the form of packets including a compressed header field and a data field and according to a format suited to the transmission system comprising the following steps: recovering the data packet to be transmitted including a compressed header and useful data, identifying the header part from the useful-data part, applying a corrector coding which is selected at the level of the header, and providing the resulting new packet to the link layer, while also communicating the protection mode used, generating the link header according to the transmission format of the relevant transmission system integrating the mode of protection used, and the adaptation of the CRC checksum of the link layer, on reception, performing the error corrector decoding in two steps.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. An apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to encode or decode a packet based on a base parity check matrix and a set of lifting values. In a particular embodiment, the set of lifting values is limited to lifting values that are each a different power of two. The memory is configured to store parameters associated with the base parity check matrix.

Abstract: A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.

Abstract: The subject technology provides a decoding solution that supports multiple choices of code rates. A decoder may be configured to receive a selected code rate from a plurality of code rates. On the selection of the code rate, the decoder may determine a circulant size based on the code rate, and, on receiving the codeword, update, during one or more parity-check operations, a number of confidence values proportional to the circulant size in each of a plurality of memory units, each number of confidence values corresponding to a portion of the codeword.

Abstract: A method includes applying an error-detecting code to first input data to generate first protected data and applying the error-detecting code to second input data to generate second protected data. The method also includes generating a first encoded codeword by encoding the first protected data using a first low density parity check (LDPC) code, and generating an output by performing a binary exclusive-or operation on the first protected data and the second protected data. The method further includes generating a second encoded codeword by encoding the output of the of the binary exclusive-or operation using a second LDPC code, and multiplexing data for transmission over a communications channel based on (i) the first encoded codeword and (ii) the second encoded codeword.

Abstract: A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.

Abstract: When data containing an unrecoverable error is received, instead of discarding the data, a lower protocol layer delivers the data to a higher protocol layer along with an indication that the data contains an error. The higher protocol layer parses the data to recover portions that are not affected by the error. Additionally, the higher protocol layer can choose to accept the data if certain acceptance criteria are met.

Abstract: A packet transmission apparatus to transmit a packet limited in arrival deadline through a best-effort network includes a packet automatic retransmission section to control retransmission of an undelivered packet, a forward error correction coding section to add redundant packet to a data packet block, and a redundancy determining section to dynamically determine redundancy of the redundant packet based on observed network state information so that a loss rate after error correction at a receiver achieved by only the retransmission of the undelivered packet satisfies an allowable loss rate after error correction.

Abstract: Systems and methods are provided for decoding a vector from a communications channel using a non-binary decoder. The communications channel may correspond to a wired or wireless channel. A message passing process computes R messages corresponding to a variable node of the non-binary decoder. Decoder extrinsic information is formed for the variable node by combining the R messages. The decoder extrinsic information is provided to a soft-detector.

Abstract: A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.

Abstract: A method in a communication system, where a systematic code obtained by systematic encoding of information bits having dummy bits inserted and by deletion of the dummy bits from results of the systematic encoding is transmitted. On a receiving side, the deleted dummy bits are inserted into the received systematic code and then decoded. The method includes: deciding a size of dummy bits for insertion into information bits; segmenting the information bits into a number of code blocks when a bit size of the information bits is greater than a stipulated size; inserting dummy bits into each block of the segmented information bits in conformity with a dummy bit insertion pattern; performing systematic encoding of each block of the information bits into which the dummy bits are inserted, and deleting the dummy bits from the results of the systematic encoding to generate a systematic code.

Abstract: An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability ? in association with each first address, a check node storage section that stores TMEM variables to calculate an external value ? in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

Abstract: Encoding is performed by dividing a quasi-cyclic low-density parity-check (QC-LDPC) parity check matrix into a first sub-matrix and a second sub-matrix. The first sub-matrix includes a plurality of circulant vectors and the plurality of circulant vectors is associated with a circulant size. Input data is received having a length which is a product of an integer multiplier and the circulant size. A first stage of multi-stage LDPC encoding is performed using the input data and a subset of the plurality of circulant vectors; the number of circulant vectors in the subset equals the integer multiplier.

Abstract: A system for encoding digital signals for transmission over a channel by allocating redundant channel encoding bits, includes at least one encoder configured for: subjecting the digital signals to multiple description coding to produce therefrom multiple description encoded signals, and allocating at least part of the redundant channel encoding bits to the multiple description encoded signals.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. In an aspect, LDPC encoding and decoding of packets of varying sizes may be supported with a set of base parity check matrices of different dimensions and a set of lifting values of different powers of two. A base parity check matrix G of dimension mB×nB may be used to encode a packet of kB=nB?mB information bits to obtain a codeword of nB code bits. This base parity check matrix may be “lifted” by a lifting value of L to obtain a lifted parity check matrix H of dimension L·mB×L·nB. The lifted parity check matrix may be used to encode a packet of up to L·kB information bits to obtain a codeword of L·nB code bits. A wide range of packet sizes may be supported with the set of base parity check matrices and the set of lifting values.

Abstract: Interleaver designs and interleaving methods that perform block-wise interleaving by reading blocks into and out of memories, where a block can be written to the memory before another block has finished being read out of the memory, without data clashes, are provided. Corresponding deinterleavers and deinterleaving methods are disclosed.

Abstract: The disclosure provides a method that includes receiving a data sector of a plurality of data tiles, wherein each of the plurality of data tiles includes either nuisance data or user data, decoding the received data sector, using an error correction code, to generate a decoded data sector, and determining an error in the decoded data sector. The method further includes identifying, in response to determining the error, at least one data tile from a first plurality of data tiles, such that each of the identified at least one data tiles potentially includes nuisance data, and generating a modified data sector from the received data sector, by correcting at least one of the at least one data tiles in the received data sector.

Abstract: An encoding method generates a parity bit sequence by encoding an information sequence with feed-forward LDPC convolutional codes based on a plurality of parity check polynomials each having a coding rate of (n?1)/n, then performs an interleaving process and an accumulation process. The accumulation process is an exclusive OR operation performed on bits of the interleaved parity bit sequence and on bits of a delayed accumulated parity bit sequence. A coded sequence is then generated from the information sequence and the accumulated parity bit sequence.

Abstract: A transmitting apparatus transmits a plurality of data packets to a receiver in a communication system, by transmitting one or more data packets from a list of data packets to be transmitted, and determining whether an acknowledgment is received for each transmitted data packet. When it is determined that an acknowledgement has not been received for at least one data packet, referred to as an unacknowledged data packet, the apparatus selects one or more additional data packets from the list of data packets to be transmitted, generates one or more parity packets by encoding a block of data containing a combination of the selected one or more additional data packets and at least one unacknowledged data packet using a forward error correction scheme, and transmits at least one of the generated parity packets.

Abstract: A method and an apparatus are provided for decoding a channel in a communication system using a LDPC code. A shortening pattern and a puncturing pattern are determined based on a received signal. A value of a shortened bit is set to 0 according to the determined shortening pattern, erasures are set according to the determined puncturing pattern, and LDPC decoding is performed, when bits exist which have been used to perform shortening or puncturing. Determining the shortening pattern and the puncturing pattern includes setting a predetermined ratio of the number of punctured bits to the number of shortened bits.

Abstract: A method and apparatus for turbo coding and decoding is provided herein. During operation, a concatenated transport block (CTB) of length X is received and a forward error correction (FEC) block size KI is determined from a group of available non-contiguous FEC block sizes between Kmin and Kmax, and wherein Kmin?KI<Kmax and wherein KI is additionally based on X. The concatenated transport block of length X is segmented into C segments each of size substantially equal KI. An FEC codeword for each of the C segments is determined using FEC block size KI; and the C FEC codewords are transmitted over the channel.

Abstract: Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word.

Abstract: A method for enforcing network bandwidth partitioning. The method includes verifying that a guest driver in a guest operating system (OS) is configured to enforce a resource usage policy, wherein the guest OS resides on a host, mapping a hardware receive ring (HRR) residing on a physical network interface card (NIC) operatively connected to the host to the guest OS, wherein after the mapping the guest OS is configured to receive packets directly from the HRR, determining, using monitoring information, that the guest OS should not receive packets directly from the HRR, and in response to the determination, creating a data path from the HRR to a host OS executing on the host, receiving packets for the guest OS from the HRR by the host OS over the data path, and forwarding the packets from the host OS to the guest OS.

Abstract: Modem selection of codeword interleaver parameters given standard based, operator based and channel based communication channel performance constraints. A processor implements processes for characterizing the forward error correction codeword and interleaver solution space in terms of expressions from which targeted portions of the solution space may be identified prior to evaluation of the magnitude of the coefficients of the corresponding nodes thereof for compliance with the to communication channel performance constraints.

Abstract: An encoding system includes a first low density parity check (LDPC) module and a second LDPC module. The first LDPC module is configured to generate a first encoded codeword by encoding a first codeword using a first LDPC code. The second LDPC module is configured to generate a second encoded codeword by encoding a second codeword using a second LDPC code. Signals based on the first encoded codeword and signals based on the second encoded codeword are transmitted over a communications channel. The first LDPC code is defined by a first parity check matrix and the second LDPC code is defined by a second parity check matrix. The second parity check matrix includes the first parity check matrix, a zero matrix, and a supplementary matrix.

Abstract: The present invention relates to a receiver device and method of detecting a block length of a data block in a data network, wherein a respective theoretical maximum value for a metric of a decoding operation is calculated for each of a plurality of candidate block lengths, and the calculated respective theoretical maximum value is compared to a respective actual value of the metric obtained for each of the plurality of candidate block lengths by the decoding operation. The candidate block length with the highest ratio between the respective actual value and the respective theoretical maximum value is then selected from the plurality of candidate block lengths to determine the block length of the data block.

Abstract: A transmission device in a communication system where a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deletion of the dummy bits from the results of the systematic encoding is transmitted. The transmission device inserts dummy bits into information bits based on an interleaving pattern of an interleaving portion in a turbo encoder; performs systematic encoding of the information bits into which the dummy bits are inserted, and then deletes the dummy bits from the results of the systematic encoding to generate a systematic code; and transmits the systematic code. By considering the interleaving pattern, original bit positions, which, after interleaving, exists within the ranges of stipulated numbers of bits at the beginning and at the end, are determined in advance, and the dummy bit insertion portion executes control so as not to insert dummy bits into the original bit positions.

Abstract: A packet transmission apparatus is provided. The packet transmission apparatus transmits a packet having a limited arrival deadline through a best-effort network. The packet transmission apparatus includes an automatic packet retransmission section to control retransmission of an undelivered packet, a forward error correction coding section to add a redundant packet to a data packet block, and a redundancy determining section to dynamically determine redundancy of the redundant packet based on observed network state information, so that a loss rate after error correction at a receiver achieved by only the retransmission of the undelivered packet satisfies an allowable loss rate after error correction.

Abstract: Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.

Abstract: Provided is a transmitter for continuously and sequentially transmitting data with a variable unit for playback. The transmitter includes an obtaining section, a buffer, a computing section and a transmitting section. The obtaining section sequentially obtains segment data of the data to be transmitted. The buffer stores an error correction code to correct an error caused in the data by transmission. The computing section computes, every time newly obtained segment data reaches a predetermined size, XOR of the error correction code already stored in the buffer and the newly obtained segment data, and then updates the error correction code with the computed XOR. The transmitting section sequentially transmits the obtained segment data, as well as reads from the buffer and transmits the updated error correction code every time the computing section computes XOR for data in a size corresponding to the unit for playback.

Abstract: A transmitting device includes a setting unit that sets the data length of an error correcting code whose data length is variable, an error correcting code calculator that calculates the error correcting code having the data length set by the setting unit for transmission-subject data as an information word, and a transmitting unit that transmits, to a receiving device existing in the same device, coded data that is data of a codeword obtained by adding the error correcting code obtained by calculation by the error correcting code calculator to the transmission-subject data.

Abstract: Disclosed is a transmission device in a communication system in which a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deleting the dummy bits from the results of the systematic encoding is transmitted and, on the receiving side, the dummy bits which had been deleted on the transmitting side are inserted into the received systematic code, and then decoding is performed. In this transmission device, a dummy bit insertion portion decides the size of the dummy bits to be inserted into the information bits based on a specified code rate or based on the physical channel transmission rate, and uniformly inserts dummy bits of this size into the information bits; a systematic code generation portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the systematic encoding to generate a systematic code, which is transmitted.

Abstract: A system and method for improving signaling channel robustness. Additional error correction is provided for (L1) dynamic signaling that is carried in P2 symbols in such way that high time diversity can be provided. In other embodiments, transmitted services are scheduled such that services will rotate or “move” between frames, thereby ensuring that a first slot for a service is not always transmitted in the same frequency.

Abstract: A decoding apparatus acquires, from encoded data, a piece of additional bits that have been partly cut off, acquires, from the piece of the additional bits, the number of bits that are missing due to the cutting off as the number of missing bits, and restores the additional bits by reproducing the missing bits.

Abstract: In one embodiment, the present patent application comprises a method and apparatus to generate low rate protographs from high rate protographs, comprising copying a base graph; permuting end points of edges of a same type in copies of the base graph to produce a permuted graph; and pruning systematic input nodes in the permuted graph and the edges connected to them. In another embodiment, the present patent application comprises a method and apparatus to generate high-rate codes from low-rate codes, comprising puncturing a subset of codeword bits, wherein the step of puncturing a subset of codeword bits comprises regular-irregular puncturing the subset of codeword bits, random puncturing variable nodes, or progressive node puncturing variable nodes to obtain a desired code from a preceding code.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: Whether to process a control channel corresponding to a data channel carrying transmitted data based on a re-transmission indicator and a threshold value is determined at the receiver. The re-transmission indicator indicates a number of times the transmitted data has been transmitted. Control information received on the control channel is then selectively processed based on the determining step.

Abstract: There is provided a method for adaptive data transfer over packet networks. The method comprises selecting a first communication path for transferring the data to the second computer, starting to transfer the data over the first communication path to the second computer, monitoring transfer characteristics of the first communication path related to the data transfer, storing the transfer characteristics associated with the first communication path in a database, comparing the transfer characteristics against one or more previously stored transfer characteristics related to one or more prior data transfers, and determining whether to alter a transfer algorithm being utilized for transferring the data to the second computer based on the comparing.

Abstract: Tail-biting turbo coding to accommodate any information and/or interleaver block size. The beginning and ending state of a turbo encoder can be made the same using a very small number of dummy bits. In some instances, any dummy bits that are added to an information block before undergoing interleaving are removed after interleaving and before transmission of a turbo coded signal via a communication channel thereby increasing throughput (e.g., those dummy bits are not actually transmitted via the communication channel). In other instances, dummy bits are added to both the information block that is encoded using a first constituent encoder as well as to an interleaved information block that is encoded using a second constituent encoder.

Abstract: Codewords encoded using non-coherent codes and received at a receiver via non-coherent channels in a multi-input, multiple output (MIMO) network using orthogonal frequency demultiplexing (OFDM) are decode by concatenating multiple adjacent codewords of a received signal into a superblock at the receiver. A projector matrix based on a codebook is predetermining. Each codeword in the superblock is projected onto an orthogonal complement of a correspond transmitted codeword using the projector matrix to obtain a corresponding distance metric of a generalized likelihood ratio test (GLRT) codeword. A minimal distance metric is selected to obtain an estimate of the transmitted codeword corresponding to a transmitted signal.

Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Abstract: A memory controller includes a buffer to which data, which is to be transferred to a memory, is input, an ECC parity generating unit which generates an ECC parity in units of a predetermined data length from the data which is to be transferred to the memory, and a memory interface which adds the generated ECC parity in units of the predetermined data length, and delivers the data with the ECC parity to the memory. When a data length of the data which is to be transferred to the memory is less than the predetermined data length, the ECC parity generating unit regards data of a part that is short of the predetermined data length as “0”, and generates the ECC parity from the data of less than the predetermined data length.

Abstract: An encoding method and apparatus for a DCH (Dedicated Channel) encoder and a DSCH (Downlink Shared Channel) encoder in a transmitter for a mobile communication system including the DCH encoder for encoding k bits among 10 input TFCI (Transport Format Combination Indicator) bits and the DSCH encoder for encoding remaining (10?k) bits among the input TFCI bits. The method comprises generating, by the DCH encoder, a first coded bit stream by encoding the k input bits into 32 bits, and outputting a (3k+1)-bit stream by puncturing the first coded bit stream according to a specific mask pattern corresponding to the k value; and generating, by the DSCH encoder, a second coded bit stream by encoding the (10?k) input bits into 32 bits, and outputting a {3*(10?k)+1}-bit stream by puncturing the second coded bit stream according to a specific mask pattern corresponding to the (10?k) value.

Abstract: Disclosed herein are various embodiments of methods, systems, and apparatus for encoding OFDM packets in a digital communication system. In one exemplary method embodiment, LDPC codewords in an IEEE 802.11 wireless transmission are shortened, decreasing the iterations necessary to insure accurate communications. The codewords are shortened by adding known bits in predetermined locations in the last data symbol of a packet.

Abstract: A method of and system for rateless source coding are disclosed. The method comprises the steps of providing a set of low-density parity check (LDPC) codes, each of which accepts a range of data input lengths and a range of target compression rates; identifying a data input having a data input length; and identifying a desired compression rate. The method comprises the further steps of selecting one of said LDPC codes based on said data input length and desired compression rate; encoding the data input, using the selected LDPC code, to generate a sequence of data values; and puncturing some of said encoded data values to achieve the desired compression rate. Preferably, the encoding step includes the steps of generating a syndrome and a parity sequence from the data input, puncturing the generated parity sequence, and mixing a remaining portion of the data input with the punctuated parity sequence.

Abstract: In some embodiments, the invention involves a system and method to continuously log correctable errors without rebooting by changing the granularity of the error detection and logging mechanism. A mask register is used to identify which errors are to be logged. Each bit of the mask register may represent a different memory component of the system. Logging of the memory component is determined by the value of the bit in the mask. The masking enables granularity of error logging to the channel and/or dual in-line memory module (DIMM) level. Other embodiments are described and claimed.

Abstract: A transmitting unit combines a slot identifier (SI) and a block identifier (BI) in each header that is transmitted with the data to allow a receiving unit to associate previously received data blocks with retransmissions, or retries, of the same respective data blocks in order to perform bit error detection in accordance with a hybrid or selective ARQ protocol. The receiving unit uses the SI and BI contained in the MHBKs to determine a correspondence between a retried data and a previously transmitted data block.

Abstract: Disclosed is a A system and method for joint source-channel encoding, symbol decoding and error correction, preferably utilizing an arithmetic encoder with operational error detection space; and a combination sequential, and arithmetic, encoded symbol decoder structure.