Abstract: A data sequence may be encoded in a plurality of layers of multiple description coding. The layers of multiple description coding may include a first and a second layer of multiple description coding. The first layer of multiple description coding may include an initial part of a data sequence as well as forward error correction code for the initial part. The second layer of multiple description coding may include a next part of the data sequence as well as forward error correction code for the next part. A first set of data sequence breakpoints may be determined for the first layer of multiple description coding. A second set of data sequence breakpoints may be determined for the second layer. The data sequence may be encoded in the plurality of layers of multiple description coding as a function of the first and second sets of data sequence breakpoints.

Abstract: In a method for a variable-length communications system including encoding a message and decoding a data bit stream, the message includes a plurality of message blocks. A message block of the message is encoded by generating a parity check bit stream, flipping the parity check bit stream, appending the flipped parity check bit stream and a number of 0's to the end of the message block, and convolutionally encoding the resultant bit stream. When a data bit stream is received, a guessed message block and a guessed flipped parity check bit stream are extracted based on a guessed message block length. A parity check bit stream is generated for the guessed message block and then flipped. If the flipped parity check bit stream is the same as the guessed flipped parity check bit stream, the message block has been identified. Otherwise, the guessed message block length is increased by 1 and the above step is repeated.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence.

Abstract: A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.

Abstract: A method is provided for channel coding a parameter whose values are correlated with one another to different extents and according to which code words with better distance properties are at least partially associated with the more strongly correlated values of the parameters, and code words with weaker distance properties are at least partially associated with the more weakly correlated values of the parameter.

Abstract: A method is presented for the coded modulation of digital data, a modulation being carried out that is coded in multiple stages. In this context, the useful bits for the coded modulation are divided into parallel signal streams, and each signal stream is fed to a specific coder to carry out the channel coding. In the respective coder, the useful bits have tail bits added to them, which, in contrast to the useful bits, are channel-coded using a variable code rate, to achieve a preestablished bit number for a specific coder, so that all signal streams that are coded in parallel contain the same number of bits.

Abstract: A communication system for performing transmission and reception of a signal over a communication channel assesses a state of the communication channel and produces channel state information accordingly. A block length selector selects block lengths that are dependent on the channel state information and that are selected from a group of block lengths having an integral multiple relationship to produce a schedule of block lengths. Encoding and decoding is performed based on the schedule of block lengths.

Abstract: A method and system are provided for dynamically shortening a number of error correction codewords to correspond to an amount of user data to be recorded on a recording medium. The system and method determine in advance that the number of bytes of user data will only fill a portion of a codeword matrix, and automatically shortens the size of ECC word segments to match the actual user data fill. This allows an ECC interleave to be completed with only a partial fill of the matrix, thereby reducing the required number of recording passes and associated processing time.

Abstract: The invention relates to a method and apparatus for transmitting data packets over a channel wherein the data packets have compressed headers. After compressing a header using a context, a number of consecutive update packets are transmitted, each containing data indicating the context. According to the invention, the channel quality is determined and the number of update packets is set accordingly. The channel quality may be determined by measuring the block error rate or the signal-to-noise ratio. Alternatively, the channel quality may be estimated by evaluating whether a NACK message has been received. The total number of update and non-update packets transmitted during a context update phase may be set according to the Round Trip Time. The number of non-update packets may further be determined based on codec properties. The invention may advantageously be used over unreliable, e.g. wireless, channels.

Abstract: A disk array device selects a redundant generation method for reducing the overhead and improving the reliability associated with generating redundant data. The disk array device includes a disk controller connected to and controlling an array of disk drives. The disk controller includes a redundant data generator, a difference data generator, and a redundant data generation method selector. The redundant data generator is able to generate redundant data via a read and modify method and an all stripes method. The disk array device selects a method of generating redundant data from a method of read and modify and all stripes, and a method of generation in a drive and a method of difference, both of which are executed to generate redundant data on a disk drive.

Abstract: A method for delineating a frame. The method generally comprises the steps of (A) receiving the frame comprising (i) a length value incorporating a payload error detection length, (ii) a length error detection value, (iii) a payload data, and (iv) a payload error detection value having the payload error detection length, wherein the payload error detection value and the payload data occupy separate fields of the frame, (B) performing an error detection on the length value based upon the length error detection value, and (C) retrieving the payload data and the payload error detection value based upon the length value in response to passing the error detection on the length value.

Abstract: A method for computing Ethernet checksums for implementing ECC processing within high performance digital transmission networks. The method includes the step of receiving an input data word and receiving an input CRC. The input data word can be 64 bits. The input CRC can be 32 bits. The input data word and the input CRC are combined using an exclusive-or function to obtain a data-CRC combination. The data-CRC combination is then positioned with respect to a time line reference. The data-CRC combination is positioned by extending the data-CRC combination with a number of future bits and shifting the extended data-CRC combination with respect to the time line reference. An output CRC is then computed for the extended data-CRC combination. The output CRC can be computed without regard to a number of valid data bits of the input data word.

Abstract: A sequence of code symbols is supplied to a rate decision block. The sequence of code symbols can be output from a Viterbi decoder, and may correspond to block encoded and convolutional encoded output from a vocoder, produced in data frames at varying data rates, or frame rates, unknown to the decoder or to the rate decision block. The rate decision block determines a number of frame energies based on the sequence of code symbols, where each frame energy corresponds to a tentative frame rate. Each frame energy can be determined, by measuring the power and duration of each code symbol based on the tentative frame rate, to determine the tentative energy of each code symbol in a frame, and then adding the tentative energies of all the code symbols in the frame. The rate decision block determines a final frame rate when the frame energies meets a desired condition.

Abstract: The invention relates to an arrangement for optimizing the data transmission over a bidirectional radio channel. According to the invention, the digital data to be transmitted according to a data transmission protocol is divided into individual data packets in each of two transmitting/receiving stations. In each transmitting/receiving station, the number and/or priority and/or type (e.g. information, control characters, repeat blocks) of the data packets generated by the data transmission protocol of the higher level and transmitted to the respective transmitter of the station is determined (data packet identifications). According to the data packet identifications, the data transmission protocol is then selected in at least one of the stations in accordance with an optimum utilization of the radio channel capacity.

Abstract: An encoding method for wireless transceiving of multimedia data including video data, and an encoding device therefor are provided. The encoding method includes (a) generating a length field representing the number of bits of a payload, (b) generating an error correction code by performing error correction coding with respect to the length field, and (c) inserting the length field and the error correction code during radio link protocol (RLP) framing. The encoding method reduces overhead when multimedia data including video data is transmitted and received under the radio environment, and increases error robustness, thereby improving the quality of an image.

Abstract: Disclosed is a system and method for joint source-channel encoding, symbol decoding and error correction, preferably utilizing an arithmetic encoder with operational error detection space; and a combination sequential, and arithmetic, encoded symbol decoder structure.

Abstract: The object-oriented coder discriminates resource allocation between objects and non-objects for video messaging applications over wireless networks. The object-oriented coder executes a rate control algorithm, an unequal error protection algorithm, and an error concealment algorithm. In the rate control algorithm, an iterative feedback rate control scheme is used in which quantization values of object and non-object data are held constant. In the unequal error protection algorithm, the bit stream is partitioned by object macroblocks and non-object macroblocks. In the error concealment algorithm, five bits of QUANT values of each GOB are used for representing location and motion vectors of the object in the next frame, since the quantization value is constant. The five bits are not used for quantization value. The five bits are used for error concealment to avoid bit rate overhead. The object-oriented coder increases encoding delay, but this increase is acceptable in messaging.

Abstract: The invention relates to a method for making data transmission more effective in a telecommunication network, which comprises layer structured protocol feature for data transmission which protocol feature comprise at least an upper layer and a lower layer, wherein the purpose of the lower layer (12) is at least to compose a data unit (6) to be transmitted to the upper layer (14) from one or more segments (9a, 9b), in which method one or more errors (5a) occurring in the received segments (1a, 1b) are detected. In the invention, said data unit (6) to be transmitted to the upper layer is composed from one or more segments (9a, 9b) containing one or more errors (5a), wherein information on the location of one or more errors (5a) is also transmitted to the upper layer (14).

Abstract: An apparatus and method for generating a (n, 3) code and a (n, 4) code using simplex codes are disclosed. To encode a 3-bit information bit stream to a (n, 3) codeword with n code symbols, a simplex encoder generates a first-order Reed-Muller codeword with (P+1) code symbols from the input information bit stream for n>P, and punctures the first code symbol of the (P+1) first-order Reed-Muller code symbols to produce a (P, 3) simplex codeword. An interleaver permutates the P code symbols of the (P, 3) simplex codeword by columns according to a predetermined pattern. A repeater repeats the column-permutated (P, 3) simplex codeword until the number of repeated codes is n and outputs a (n, 3) codeword with the n repeated code symbols.

Abstract: Encoded data using reversible variable length code words is input to a forward decoder (123) to be decoded in the forward direction. When an error is detected in the encoded data in the forward decode processing, backward decode processing is started by a backward decoder (126). A decode value determination unit (125) determines a decode value by using the forward and backward decode results and the error detection positions in the encoded data in units of bits and syntax which are respectively detected in the forward decoding and the backward decoding.

Abstract: Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence.

Abstract: Correction and location information are determined from a number of data vectors. The location information comprises values determined from subsets of the data vectors. Two or more of the subsets have one or more data vectors in common, but also have one or more data vectors, in one or more of the subsets, that are not in other subsets. The subsets comprise groups of data vectors, and the groups of data vectors have a size that is a function of a power of two. Transmission codes are used on the data vectors and correction and location information. Received location information and determined location information are compared to determine a data vector having an error. Received correction information and determined correction information are compared to correct the data vector having the error. Failing optical lanes may be replaced efficiently by using a number of multiplexers coupled to electrical lanes and optical lanes.

Abstract: In one embodiment, the present invention comprises a demultiplexer to divide a bit stream into a first block at a first output and a second block at a second output, a convolutional coder coupled to the first output to encode the first block and a block coder coupled to the second output to encode the second block. The invention further includes a function module coupled to the block coder to apply one of a plurality of different functions to the encoded second block to produce a third block at an output and a mapper coupled to the function module output and to the convolutional coder to map the third block from the output of the function module and the encoded first block into one of a plurality of modulation constellations. A controller is coupled to the demultiplexer to control the size of the first and second blocks, is coupled to the block coder to control the block coding, and is coupled to the function module to control the function to be applied.

Abstract: The present invention provides a mechanism for preventing quality degradation of decoded data during the decoding of encoded data. In one embodiment, error propagation is detected and corresponding data is flagged. An error recovery process is then applied to the flagged data. In an alternate embodiment, scores for candidate hypotheses are calculated for lost/damaged data. A score distribution is used for detection of the false candidate hypotheses. The data are flagged if their score distribution is within a range defined by a threshold and an error recovery process is applied to recover those data having associated error flags set.

Abstract: An apparatus and method for receiving control information transmitted from a transmitter using one of a plurality of slot lengths in a high-speed packet transmission mobile communication system is provided. The apparatus and method includes a decoder adapted to receive symbols by the slot, and generate at least one bit stream by decoding as many symbols of at least one possible slot length among a plurality of slot lengths according to a previous decoding result. An error checker adapted to perform error checking on the bit stream from the decoder. A controller is adapted to provide symbols of one more consecutive slot to the decoder, if the error checking failed, and acquire control information from the error checking-passed bit stream, if the error check passed. The decoder is further adapted to output at least one frame quality metric for the bit stream along with the bit stream.

Abstract: A computer for data processing and a method for data processing using a computer, each of which is used for reversing, with the aid of a circuit arrangement, the bit sequence of the information, which was coded with a reversible Huffman code, when an error occurs, so that the computer decodes the reversed bit sequences using a suitable code table. In the computer, a data buffer is connected to a register in such a way that the bit sequence is reversed when transferred from the data buffer to the register. The bit sequence is not reversed when it is retransferred from the register into the data buffer. In this way, information which is located after the error does not get lost. Since to reverse the bit sequence, the end of the bit sequence, designated by a synchronization bit sequence, must be found, the synchronization bit sequence is disposed at byte boundaries due to padding bits. In this way, synchronization bit sequences are located only at byte boundaries.

Abstract: Modem selection of Reed-Solomon codeword configuration to maximize error-corrected data rate given channel analysis. A lookup table of maximal codeword size given parity bytes and channel MSE allows precomputation.

Abstract: In a heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems, an I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least one disk connected to the I/O subsystem B in a magnetic tape library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: The probability of frame destruction is lowered while suppressing the redundancy of the transmission data. On the transmitting side, a predetermined unique word is contained in a frame n for storing the n-th data, and header information n, frame length information and header information n−1 of the frame n−1 one frame before the frame n are subjected to error-correcting coding, contained in the frame n, and transmitted. On the receiving side, the header of the frame n is received. When the frame length information is transmitted with error, the timing is specified by detecting the unique word and header information in the next frame n+1. When the header of the frame n is not successfully decoded, the information data of the frame n is decoded by using the header information n inserted into a predetermined position of the frame n+1.

Abstract: Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages.

Abstract: When a stream that has been compressed and encoded with a variable length code, even if the stream has a syntax error, the operation can be stably performed. Depending on the position of an error flag on a stream of which the variable length code has been decoded, the correcting process is varied. When the flag is set at the position of a header portion followed by a DCT block is substituted with a prepared value. In addition, a DCT block is substituted with a predetermined coefficient of a DC component. EOB data is added after the coefficient. After the EOB data, the macro block is discarded. When the flag is set at the position of a DC coefficient portion, it is substituted with a coefficient that causes a gray to be displayed. When the flag is set at the position of an AC coefficient portion, EOB data is added after the AC coefficient portion. After the EOB data, the macro block is discarded.

Abstract: A scheme for configuring an FEC encoder (including an associated interleaver) for changing data channel characteristics. Channel information specifying a modulation mode and carriers capable of supporting the modulation mode for the data channel is received by a transmitting network node for use in a data transmission to a receiving network node. The received channel information is based on a prior data transmission to the receiving network node over the data channel. Configuration values are computed from the received channel information and an amount of data to be transmitted in a data transmission. The FEC encoder is configured to operate on the data transmission data amount according to the configuration information.

Abstract: A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a data block. In one embodiment, the unit also includes a selector to select one of the remainder values, and a register to store the selected remainder value, return the stored remainder value to the PDCs for formation of different bit length dividends, and output the stored remainder value of the last iteration as the generated CRC value. In one embodiment, the unit further includes alignment circuitry to align the data block. In one embodiment, multiple units are provided to generate the CRC values of successive variable length data blocks. In one embodiment, the units form a shared resource to multiple network traffic flow processing units of a network traffic routing IC.

Abstract: A method for decoding received data in a decoder which receives data from an encoder varying a length of a Walsh code according to a coding rate of transmission data, and has maximum IFHT (Inverse Fast Hadamard Transform) stages capable of decoding even the data encoded by a Walsh code with a maximum length. The method comprises selecting at least one IFHT stage among the maximum IFHT stages according to a length of the Walsh code used for the received data; and performing inverse fast Hadamard transform on the received data by the selected IFHT stage.

Abstract: This invention discloses a method for changing a configuring ot an error correction code (ECC) logic circuit for performing an error-check of a changed data-width. The method includes the steps of: A) sequentially interconnecting a set of N1 identical error-check blocks where N1 is a first positive integer. And, the method further includes a step B) of reconfiguring the ECC logic circuit by changing the ECC logic circuit to a set of N2 sequentially interconnected circuits comprising N2 of the identical error-check blocks where N2 is a second positive number. In a preferred embodiment, the step of sequentially interconnecting a set of N1 identical error-check blocks is a step of interconnecting the N1 error-check blocks only between sequentially neighboring blocks for transmitting signals only between the neighboring error-check blocks.

Abstract: An apparatus for encoding digital data for storage on a data storage medium includes a non-deterministic randomizer code generator. The randomizer code generator may select different randomizer codes for different portions of the data to be stored. The randomizer code used to randomize a given portion of the data may be stored on the media for use in subsequent data retrieval.

Abstract: A channel bit sequence converting unit detects the particular code sequence in which the minimum run is repeated from the code rule output from the run detection processing unit and converts the particular code sequence, when it is detected, to the predetermined channel bit sequence and then outputs this channel bit sequence to a buffer. Thereby, modulation and demodulation of the code having the code restriction can be performed easily.

Abstract: Disclosed is a system and method for joint source-channel encoding, symbol decoding and error correction, preferably utilizing an arithmetic encoder with operational error detection space; and a combination sequential, and arithmetic, encoded symbol decoder means.

Abstract: A digital data recording channel which uses variable rate encoding. The encoder monitors an input bit stream for sequences associated with selected readback characteristics, and inserts one or more bits where desirable to improve the characteristics of the stored bit stream.

Abstract: A method for encoding error correcting codes to generate plural coded data having different error correction ability according to significance. An error correcting code having different code length is added to a fixed length of input data according to the significance of the input data (S14). The error correcting codes added which have different error correction ability corresponding to its code length are encoded to generate coded data having different packet length according to the code length of the error correcting code. Thus, plural coded data (S15A and S15B) which have different error correction ability according to significance can be generated. Thereby, even if a quality of transmission system deteriorates when the above coded data is transmitted, the coded data having high error correction ability can be surely decoded.

Abstract: A disk array device selects a redundant data generation method for reducing the overhead and improving the reliability associated with generating redundant data. The disk array device includes a disk controller connected to and controlling an array of disk drives. The disk controller includes a redundant data generator, a difference data generator, and a redundant data generation method selector. The redundant data generator is able to generate redundant data via a read and modify method and an all stripes method. The disk array device selects a method of generating redundant data from a method of read and modify and all stripes, and a method of generation in a drive and a method of difference, both of which are executed to generate redundant data on a disk drive.

Abstract: A system and method for decoding a signal comprising fixed-length data (FL-data) and variable length data (VL-data) is disclosed. In one embodiment, groups of fixed length data (FL-data) and blocks of variable length data (VL-data) are stored in a predetermined space. Each group of FL-data corresponds to a block of VL-data. The blocks of VL-data are retrieved by referencing corresponding groups of FL-data. In one embodiment, this system and method permits bidirectional recovery of data. In one embodiment, this is used in the transmission of video signals over a potentially lossy communications channel.

Abstract: A digital data recording channel which uses variable rate encoding. The encoder monitors an input bit stream for sequences associated with selected readback characteristics, and inserts one or more bits where desirable to improve the characteristics of the stored bit stream.

Abstract: A method of passing transmissions through an error-correction code (ECC) block in a communications path of a computer system. The communications path interconnects a first component of the computer system (such as a random-access memory (RAM) device) and a second component of the computer system (such as a central processing unit (CPU)) using a first granularity, and a third component (such as a read-only memory (ROM) device) is further connected to the communications path such that the third component may transmit data to the second component using a second granularity which is smaller than the first granularity. The data from the third component passes through the ECC block by merging data from the third component with predefined data to present a merged data word to the ECC circuit, wherein the merged data word has the first granularity. The first granularity may be, e.g., 72 bits, while the second granularity is 8 bits.

Abstract: In decoding an received codeword encoded for error correction purposes, a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step is presented whereby the polynomials are generated through a number of intermediate steps that can be implemented with minimal amount of hardware circuitry. The number of intermediate steps requires a corresponding number of cycles to complete the calculation of the polynomials. Depending on the selected (N, K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of up-stream data. More specifically, an efficient scheduling of a small number of finite-field multipliers (FFM's) without the need of finite-field inverters (FFI's) is disclosed. Using these new methods, an area-efficient architecture that uses only three FFM's and no FFI's is presented to implement a method derived from the inversionless Berlekamp-Massey algorithm.

Abstract: The method for selecting CRC polynomials (or CRC generators) for linear coded systems. In the exemplary embodiment, a communication system utilizes a concatenated code comprising a CRC code and a convolutional code. The CRC generators are selected based on the distance spectrums which have been computed for all possible CRC generators of a given length L. The distance spectrum comprises a listing of the number of paths (or code words) at various weights (or Hamming distance). These paths represent error information sequences I(x) which have diverged from an all-zero transmitted sequence (or the zero state) and have merged back into the zero state. The paths are checked by the CRC generators. If the CRC check passes, indicating that the error information sequence is undetected by the CRC check, the weight of this path is calculated and the distance spectrum for this CRC generator is updated. Otherwise, if the CRC does not check, the path is ignored. The CRC generator with the maximum minimum distance d.sub.

Abstract: An error control device includes an error detection code generating section and an error detection section. The error code generating section is arranged in a recording system to generate and add an error detection code to variable-length data. The error detection section is arranged in a reproducing system to perform error detection for reproduced variable-length data on the basis of the error detection code added thereto.