Abstract: The invention discloses a distribution method of channelization code in code division multiple access system, which including: A. the spread spectrum codes distributed to every sector and the correlated coefficients between the spread spectrum codes distributed to every neighboring sector are calculated according to the cellular codes and the channelization codes distributed to every sector, when the network is programmed; B. every sector is divided into different regions and the edge region of every sector is formed; C. the priority of which every channelization code is at the edge region of every sector is decided according to the correlated coefficients between the spread spectrum codes distributed to every neighboring sector; D. the position information of user is real-time calculated during the operation of system, and which region the user positioned in sector is determined according to the position information; E.

Abstract: A method for error correction that includes receiving a bitstream, the bitstream comprising one or more bits, determining if the bitstream has one or more corrupt bits, determining one or more hypotheses representing an error pattern, and assigning a probability to each of the hypotheses, wherein the probability is determined based on one or more reference data.

Abstract: A system is provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.

Abstract: Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.

Abstract: A method is provided for encoding and decoding a sequence of digital data, according to which a portion of the sequence of digital data corresponds to a data block that includes several data packets, at least two data packets per data block containing an identifier. The position of the data packet within the corresponding data block can be determined based on the identifier, and the data is encoded or decoded by taking into account the identifier.

Abstract: A method is provided for encoding and decoding a sequence of digital data, according to which a portion of the sequence of digital data corresponds to a data block that includes several data packets, at least two data packets per data block containing an identifier. The position of the data packet within the corresponding data block can be determined based on the identifier, and the data is encoded or decoded by taking into account the identifier.

Abstract: A transmitting apparatus and a transmitting method wherein the systematic bit reception quality can be improved and the throughput performance can be improved. An IR parameter control part (101) controls, based on the number of retransmissions, the ratio of systematic bits to parity bits in mapping them to packets, and controls to map a parity bit to an initially transmitted packet, while mapping a systematic bit to a retransmitted packet. An encoding part (102) generates the systematic bits and parity bits and maps them to the packets in accordance with the IR parameters. A transmission power calculating part (105) calculates, based on reception quality information of the initially transmitted packet fed back from a receiving end, the transmission power of the transmitted packet to which the systematic bit is mapped.

Abstract: In the packet stream receiver, transport streams are sequentially input, discontinuity of continuity counters described in packet headers of transport stream packets in the stream is detected and a loss of a transport stream packet is determined. A terminator is added to part of NAL units extracted from a packet immediately before the transport stream packet is lost, and data on NAL units up to a NAL unit whose start code is detected is discarded after the start code of the NAL unit contained in the transport stream packet is detected and a terminator is added thereto. Thus, a packet stream receiver can obtain appropriate data even when part of packets is lost during transmission.

Abstract: In a transmitting entity a message of a first time period L is divided into N self-decodable blocks and transmitted towards a communications network. At the communications network the N self-decodable blocks are detected by a receiving entity and decoded on a block basis.

Abstract: An intelligent streaming media error check detection method and apparatus. The claimed invention discloses an apparatus and method where all streaming media are initially assumed to have compatible error checksums. A parameter W is initialized to zero. The parameter W is not constant and conceptually represents a state of the error check method. The destructive value of a first predefined constant is added to the parameter W each time the acceptability of a data set cannot be verified. The constructive value of a second predefined constant is subtracted from the parameter W each time the acceptability of a data set is successfully verified. If the value of the parameter W equals or exceeds a predefined threshold, the remainder of the streaming media is decoded and played without error check protection.

Abstract: Methods of managing storage of HARQ packets are disclosed. One method includes a wireless device receiving variable length HARQ packets. The wireless device performing an error check on each received variable length HARQ packet, and storing within HARQ memory the HARQ packets that fail the error check. Each failed HARQ packet is stored in the HARQ memory by dividing the HARQ packet into HARQ sub-packets, and storing each HARQ sub-packet. The storage locations and storage order of each of the HARQ sub-packets are recorded for future retrieval.

Abstract: Disclosed is a device and procedure for coding a block low density parity check (LDPC) code having a variable length. The a device and procedure includes receiving an information word; and coding the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code.

Abstract: A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

Abstract: An ECC block is constituted by RS(248, 216, 33). Of a data length of 216 bytes (symbols), only 16 bytes are allocated to BCA data and the remaining 200 bytes are used for fixed data having a predetermined value. Using the fixed data of 200 bytes and the BCA data of 16 bytes, parities of 32 bytes (symbols) are calculated. Only the BCA data of 16 bytes and the parities of the former 16 bytes of the 32-byte parities, that is, a total of 32 bytes only, are recorded in a burst cutting area of an optical disc. In decoding, error correction processing is carried out by using the fixed data of 200 bytes. The unrecorded parities of 16 bytes are processed as having been erased. Thus, the error correction capability in a burst cutting area of an optical disc can be improved.

Abstract: Methods, apparatus and systems are disclosed for block encoding/decoding information wireless networks having narrow decoding latency restrictions. A method includes identifying a length of information to be sent in a block code and encoding the information to be sent in the block code into one or more codewords, where the number of codewords and the amount of information encoded within each codeword is adjusted based on the identified length and to achieve a similar codeword error probability for each codeword considering available decoding time for decoding a last codeword is less than available decoding time for decoding a first codeword. In certain implementations low density parity check (LDPC) encoding may be used in combination with OFDM to provide reliable communications in a high throughput WLAN.

Abstract: In an exemplary embodiment, a base station includes an antenna for transmitting signals on a downlink to a plurality of user devices. The base station also includes a processor, and memory in electronic communication with the processor. Interleaving instructions are stored in the memory. The interleaving instructions are executable by the processor to interleave coded data in accordance with an interleaving algorithm in order to generate interleaved data. The interleaving algorithm is configured to accommodate use of different transmission bandwidths for data transmission. OFDMA processing instructions are also stored in the memory. The OFDMA processing instructions are executable by the processor to perform OFDMA processing on the interleaved data. The OFDMA processing facilitates the use of a varying number of sub-carriers for channel transmission.

Abstract: A transmitter determines a number of available bits (Navbits) in a minimum number of orthogonal frequency division multiplex (OFDM) symbols in which a data field of a packet may fit, by Navbits=(NCBPS*(1+USTBC))*ceil(Npld/(NCBPS*R*(1+USTBC))), where USTBC equals 1 when Space-Time Block Code (STBC) is used and 0 otherwise, where Npld=LENGTH*8+16, where NCBPS is the number of coded bits per symbol, where R is the code rate, and where LENGTH is a number of bytes in a Physical Layer Convergence Protocol (PLCP) PLCP Service Data Unit (PSDU); and determines an integer number of Low-Density Parity-Check Code (LDPCC) codewords to be transmitted, NCW, and the length of the codewords to be used, LLDPC, from information capable of being expressed in a table format.

Abstract: An extended deinterleaver the extended deinterleaver being responsive to at least one input signal, comprised of codewords, and operative to generate a deinterleaved output signal. The extended deinterleaver comprising a storage space organized into B number of appended storage branches, at least one appended storage branch having a storage branch and at least one element N, the received codewords being deinterleaved and buffered by the extended deinterleaver prior to being provided to the variable iteration decoder. Each appended storage branch further having a length that is extended by the length of N, N being at least one element, wherein as a codeword is provided to the variable iteration decoder, other codewords are provided to subsequent appended storage branches, and further wherein each appended storage branch, indexed by ‘b’, has a length of Lb+N, wherein Lb is the length of the storage branch prior to appending N.

Abstract: Techniques for generating cyclic redundancy check (CRC) values are provided. Bit messages that are to be transmitted to recipients are aligned to desired byte boundaries for purposes of generating CRC values, which are to be sent with the bit messages. The CRC values are rewound or adjusted back to values associated with original lengths of the bit messages before the CRC values are transmitted or forwarded with the bit messages to recipients.

Abstract: An ECC block is constituted by RS(248,216,33). Of a data length of 216 bytes (symbols), only 16 bytes are allocated to BCA data and the remaining 200 bytes are used for fixed data having a predetermined value. Using the fixed data of 200 bytes and the BCA data of 16 bytes, parities of 32 bytes (symbols) are caculated. Only the BCA data of 16 bytes and the parities of the former 16 bytes of the 32-byte parities, that is, a total of 32 bytes only, are recorded in a burst cutting area of an optical disc. In decoding, error correction processing is carried out by using the fixed data of 200 bytes. The unrecorded parities of 16 bytes are processed as having been erased. Thus the error correction capability in a burst cutting area of an optical disc can be improved.

Abstract: A system and method for efficiently detecting and correcting transmission errors in packet-based communications by using cumulative error detection codes. The system may comprise a transmitting unit, which transmits one or more data packets. Each of the transmitted packets may comprise a plurality of transmission subunits. The transmitting unit preferably generates a cumulative error detection code (e.g., cumulative CRC code) for each of the transmission subunits of a packet. The system may further comprise a receiving unit to receive each of the transmission subunits of the packet. The receiving unit preferably generates a new cumulative error detection code for each of the received transmission subunits. The new cumulative error detection code is compared to the received cumulative error detection code to determine if any errors occurred in the transmission of the transmission subunit.

Abstract: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.

Abstract: An apparatus for transmitting a FEC frame is provided. In order to correct an error caused by a transmission medium using FEC in a Reed-Solomon code type, FEC encoding/decoding of a frame is performed. A total transmission delay time is not influenced when FEC is bypassed, a delay caused by a shortened codeword is minimized, and a FEC encoding/decoding delays for frames having different lengths are equalized.

Abstract: A forward error correction method including inserting at least one filler symbol into an input data stream at a pre-determined position, thereby generating a precoded symbol group, FEC encoding the precoded symbol group, thereby generating a code word, removing at least one of the filler symbols from the code word, thereby generating an optimized code word, inserting at least one filler symbol into the optimized code word at the predetermined position, thereby generating a deoptimized code word, FEC decoding the deoptimized code word, thereby generating a decoded symbol group, and removing at least one of the filler symbols from the decoded symbol group, thereby generating an output data stream.

Abstract: A reconfigurable bit-manipulation node is disclosed that includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit is comprised of interconnected elements that include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

Abstract: An apparatus and method for receiving control information transmitted from a transmitter using one of a plurality of slot lengths in a high-speed packet transmission mobile communication system is provided. The apparatus and method includes a decoder adapted to receive symbols by the slot, and generate at least one bit stream by decoding as many symbols of at least one possible slot length among a plurality of slot lengths according to a previous decoding result. An error checker adapted to perform error checking on the bit stream from the decoder. A controller is adapted to provide symbols of one more consecutive slot to the decoder, if the error checking failed, and acquire control information from the error checking-passed bit stream, if the error check passed. The decoder is further adapted to output at least one frame quality metric for the bit stream along with the bit stream.

Abstract: A method of writing data includes receiving a record of a variable-length data format, creating a field-checking code for each field of the record received, creating a block-checking code in units of the fixed-length data for the data received, and writing data by reading the record, assembling fixed length data that includes the field-checking code and the block-checking code by using the field-checking code and the block-checking code, and transferring the data to a cache memory.

Abstract: A loop status monitoring apparatus monitors a status of an arbitration loop that includes a plurality of devices and a switch that controls connections between the devices, has at least one of loop status detection data, primitive detection data, and frame count data, and includes a failure detecting unit that detects whether an initialization failure, which is a connection failure, has occurred during an initialization of the arbitration loop from the loop status detection data; and a device identifying unit that identifies, when the initialization failure is detected, a device with the initialization failure occurred from the primitive detection data or the frame count data.

Abstract: An apparatus and method for generating a (n, 3) code and a (n, 4) code using simplex codes are disclosed. To encode a 3-bit information bit stream to a (n, 3) codeword with n code symbols, a simplex encoder generates a first-order Reed-Muller codeword with (P+1) code symbols from the input information bit stream for n>P, and punctures the first code symbol of the (P+1) first-order Reed-Muller code symbols to produce a (P, 3) simplex codeword. An interleaver permutates the P code symbols of the (P, 3) simplex codeword by columns according to a predetermined pattern. A repeater repeats the column-permutated (P, 3) simplex codeword until the number of repeated codes is n and outputs a (n, 3) codeword with the n repeated code symbols.

Abstract: Systems and methods are disclosed for denoising for a finite input, general output channel. In one aspect, a system is provided for processing a noisy signal formed by a noise-introducing channel in response to an error correction coded input signal, the noisy signal having symbols of a general alphabet. The system comprises a denoiser and an error correction decoder. The denoiser generates reliability information corresponding to metasymbols in the noisy signal based on an estimate of the distribution of metasymbols in the input signal and upon symbol transition probabilities of symbols in the input signal being altered in a quantized signal. A portion of each metasymbol provides a context for a symbol of the metasymbol. The quantized signal includes symbols of a finite alphabet and is formed by quantizing the noisy signal. The error correction decoder performs error correction decoding on noisy signal using the reliability information generated by the denoiser.

Abstract: An encoding method and apparatus for a DCH (Dedicated Channel) encoder and a DSCH (Downlink Shared Channel) encoder in a transmitter for a mobile communication system including the DCH encoder for encoding k bits among 10 input TFCI (Transport Format Combination Indicator) bits and the DSCH encoder for encoding remaining (10-k) bits among the input TFCI bits. The method comprises generating, by the DCH encoder, a first coded bit stream by encoding the k input bits into 32 bits, and outputting a (3k+1)-bit stream by puncturing the first coded bit stream according to a specific mask pattern corresponding to the k value; and generating, by the DSCH encoder, a second coded bit stream by encoding the (10-k) input bits into 32 bits, and outputting a {3*(10-k)+1}-bit stream by puncturing the second coded bit stream according to a specific mask pattern corresponding to the (10-k) value.

Abstract: A data sequence may be encoded in a plurality of layers of multiple description coding. The layers of multiple description coding may include a first and a second layer of multiple description coding. The first layer of multiple description coding may include an initial part of a data sequence as well as forward error correction code for the initial part. The second layer of multiple description coding may include a next part of the data sequence as well as forward error correction code for the next part. A first set of data sequence breakpoints may be determined for the first layer of multiple description coding. A second set of data sequence breakpoints may be determined for the second layer. The data sequence may be encoded in the plurality of layers of multiple description coding as a function of the first and second sets of data sequence breakpoints.

Abstract: A system for verifying data integrity includes a central processing unit (CPU) (1), a non-volatile random access memory (NVRAM) (2), and a program memory (3). The NVRAM includes: a plurality of data blocks (23), each data block including a plurality of data bits (20) for storing bit data; a first recognition bit (21) for storing a first recognition code; and a second recognition bit (22) for storing a second recognition code. The program memory stores program modules. The CPU updates and deletes data in data blocks, reads a first recognition code and a second recognition code in a data block in which bit data are to be read, and identifies whether the bit data are complete according to a combination of the first recognition code and the second recognition code. A related method for verifying data integrity is also disclosed.

Abstract: An intelligent streaming media error check detection method and apparatus. The claimed embodiment discloses an apparatus and method where all streaming media are initially assumed to have compatible error checksums. A parameter W is initialized to zero. The parameter W is not constant and conceptually represents a state of the error check method. The destructive value of a first predefined constant is added to the parameter W each time the acceptability of a data set cannot be verified. The constructive value of a second predefined constant is subtracted from the parameter W each time the acceptability of a data set is successfully verified. If the value of the parameter W equals or exceeds a predefined threshold, the remainder of the streaming media is decoded and played without error check protection.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: A method and apparatus to preserve bandwidth in a communication system are described wherein a receiver receives a first frame of transport blocks from a mobile device and an error detection module connected to the receiver detects whether each transport block contains an error. The error detection module generates an error indicator value to indicate whether each transport block contains an error or does not contain an error. A frame generator connected to the error detection module generates a second frame with the transport blocks that do not contain an error and the error indicator values. A first network interface is configured to send the second frame to a radio network controller. Other embodiments are described and claimed.

Abstract: A system for processing data packets comprising a plurality of data processing blocks and a controller, which allows the configuration parameters used in processing the data blocks to be updated in each data processing blocks at the data packet boundary. The present invention involves a system that utilizes a handshaking method for synchronously exchanging data between data processing blocks, wherein the data processing blocks update configuration parameters based on the type of networking standard used. Each data processing block identifies a first data block in the data packet and transmits a first data signal along with a first output data block of the data packet, wherein the block updates the configuration parameters from the controller only when the first data signal is present. In this manner, the first data signal, which is indicative of the data packet boundary, is propagated along the sequence of data processing blocks.

Abstract: Performing soft error correction includes receiving a word at a soft correction engine capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results for the received word using combinations of the soft bit positions and the more than one correction modes. The soft correction engine may include a Golay engine.

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

Abstract: An error detection and correction scheme for multi-level cell memory arrays is disclosed. By separating adjacent bits of data into multiple bit streams, the likelihood of error correction is increased.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: One embodiment relates to a method of generating an N-bit checksum for variable-length data. An N-bit data word of the variable-length data is received by data input circuitry, and an N-bit input checksum generator is used to calculate an updated value of the N-bit checksum for N-bit data words. A plurality of smaller checksum generators and the N-bit input checksum generator are each used to calculate a last value of the N-bit checksum for the last data word of the variable-length data. Control signals are used to controllably select the last value of the N-bit checksum from outputs of said checksum generators. Other embodiments and features are also disclosed.

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

Abstract: A system for improving a memory's error detecting and error correcting capabilities. During operation, the system receives a data-word. Next, the system compresses the data-word into a compressed-word. If the amount of compression is greater than or equal to a compression-threshold, the system applies a strong error-correcting-code to the compressed-word to generate a coded-word. On the other hand, if the amount of compression is less than the compression-threshold, the system applies a weak error-correcting-code to the data-word to generate a coded-word. In either case the size of the coded-word is less than or equal to the size of a storage-word. The system then generates a flag that indicates the type of error-correcting code that was used to generate the coded-word. The system then stores the flag along with the coded-word in the memory.

Abstract: A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between the remainder XOR subtree levels; a combinatorial XOR tree, outputs of the remainder partition and outputs of the data partition connected to inputs of the combinatorial XOR tree; and a remainder latch, combinatorial XOR tree connected to the remainder latch and the outputs of the remainder latch connected to the remainder partition.

Abstract: In a method to protect and/or detect information in a data transmission system, the pieces of data exchanged have a format comprising one or more headers and a data zone. The method comprises at least one step for the insertion, into at least one header, of at least one EPB marker segment comprising redundancy data to detect and/or correct errors.

Abstract: The invention relates to a variable-length error-correcting (VLEC) code construction method, in which the main steps are: defining all the needed parameters, generating a code having a fixed length L1, storing in a set W thus obtained all the possible L1-tuples dista22nt of the minimum diverging distance d ‘min! from the codewords (one extra-bit being affixed at the end of all words if the new set W thus obtained is not empty), deleting all words of W that do not satisfy a distance criterion with all codewords, and verifying that all words of the final set W satisfy another distance criterion. Assuming that all distributions of number of codewords for the best VLEC codes have a similar curve allure of a bell shape type, it is then proposed, according to the invention, to define an optimal length value Lm until which the number of codewords increases with their length, whereas it decreases after said value Lm.

Abstract: Techniques for transmitting and receiving multiple channels with block coding in a communication system are disclosed. In one aspect, a secondary broadcast channel is transmitted concurrently with parity information, encoded from a primary broadcast channel. In another aspect, a mobile station repurposes its receiving circuitry to receive one or more portions of the secondary broadcast channel after a sufficient portion of the primary broadcast channel is received without identified error. In another aspect, secondary broadcast channels associated with a plurality of primary broadcast channels are multiplexed onto a single secondary channel. Various other aspects are also presented. These aspects have the benefit of minimizing mobile station resources required to receive multiple broadcast channels, as well as reducing the complexity and channel resources required to transmit multiple broadcast channels.

Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) transmitting data on a bus, wherein data is presented on the bus using varying widths; (2) configuring a cyclic redundancy check (CRC) to be performed on the data based on the manner in which the data is presented on the bus; and (3) performing the CRC on the data. Numerous other aspects are provided.

Abstract: In a method for a variable-length communications system including encoding a message and decoding a data bit stream, the message includes a plurality of message blocks. A message block of the message is encoded by generating a parity check bit stream, flipping the parity check bit stream, and appending the flipped parity check bit stream to the end of the message block. When a data bit stream is received, a guessed message block and a guessed flipped parity check bit stream are extracted based on a guessed message block length. A parity check bit stream is generated for the guessed message block and then flipped. If the flipped parity check bit stream is the same as the guessed flipped parity check bit stream, the message block has been identified. Otherwise, the guessed message block length is increased by 1 and the above step is repeated.