Abstract: A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a predetermined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the predetermined column among one or more column(s) of the parity check matrix.

Abstract: Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H0 of a sparse parity check matrix H1 to obtain at least a first codeword; truncating the at least first data element to obtain at least a first truncated data element; systematically encoding the at least second data element and the at least first truncated data element using the sparse parity check matrix H1 to obtain a nested codeword; and generating a second codeword based at least in part on a combination of the first codeword and the nested codeword. Integrated-interleaved LDPC decoding is also provided.

Abstract: In a communications device a grouping unit uses channel state information when mapping data bits to a plurality of different constellation groups. Each constellation group is assigned to another modulation scheme. A plurality of sub-carriers is assigned to none or one of the constellation groups and each modulation uses another one of the constellation groups. The communications device includes at least one scalable interleaver unit, wherein each interleaver unit is assigned to one of the constellation groups and interleaves the assignment of data bits mapped to each constellation group and the sub-carriers that carry a symbol information derived from the data bits. As an example, the interleaver unit performs frequency interleaving by interleaving, at constellation level, the sub-carriers that carry the symbol information.

Abstract: A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a plurality of rows and a plurality of columns. The plurality of rows include a row component code. The plurality of columns include a column component code. The row component code is configured to achieve a lower bit error rate than the column component code in communication channels having a same signal to noise ratio.

Abstract: A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.

Abstract: A method for accessing a semiconductor device having a memory array, includes receiving a chip select signal, receiving a command signal and an address signal, receiving a verification signal, calculating an error signal based on the address signal, the command signal, and the verification signal, generating an internal chip select signal based on the received chip select signal if the error signal indicates no error, and generating an external alert signal if the error signal indicates an error.

Abstract: Techniques for handling uncorrectable errors occurring during memory accesses reduce the likelihood of mis-correction of errors due to the presence of noise. When an uncorrectable memory error is detected in response to an access to a memory device, a memory controller managing the interface to the memory halts issuing of access requests to the memory device until a predetermined time period has elapsed. In-flight memory requests are marked for retry, and responses to pending request are flushed. A calibration command may be issued after the predetermined time period has elapsed. After the predetermined time period has elapsed and any calibration performed, the requests marked for retry are issued to the memory device.

Abstract: Techniques for handling uncorrectable errors occurring during memory accesses reduce the likelihood of mis-correction of errors due to the presence of noise. When an uncorrectable memory error is detected in response to an access to a memory device, a memory controller managing the interface to the memory halts issuing of access requests to the memory device until a predetermined time period has elapsed. In-flight memory requests are marked for retry, and responses to pending request are flushed. A calibration command may be issued after the predetermined time period has elapsed. After the predetermined time period has elapsed and any calibration performed, the requests marked for retry are issued to the memory device.

Abstract: Techniques to perform forward error correction for an electrical backplane are described including forward error correction (FEC) circuitry to perform forward error correction, physical coding sublayer circuitry, and physical medium attachment (PMA) circuitry. The FEC circuitry provides primitives comprising a FEC_UNITDATA.request primitive, a FEC_UNITDATA.signal primitive, and FEC_UNITDATA.indication primitive, the FEC sublayer and includes an encoder having a reverse gearbox and a pseudo-noise generator.

Abstract: A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.

Abstract: A memory device includes a parity circuit configured to detect presence or absence of an error using a plurality of command signals and a plurality of address signals, a command shift circuit configured to shift the plurality of command signals by a preset delay value in synchronization with a control clock, a clock control circuit configured to deactivate the control clock when there is no valid command signal in command signals being shifted in the command shift circuit, and a decoder circuit configured to decode a plurality of command signals output from the command shift circuit.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Abstract: Methods and apparatus for temporarily storing parity information for data stored in a storage device are provided. A first data block and parity information associated with the first data block are received. The first data block is stored in a first region of the storage device. The parity information is stored until a second data block is successfully stored in a second region of the storage device. The first region of the storage device is associated with the second region of the storage device.

Abstract: The present inventions are related to systems and methods for detecting trapping sets in LDPC decoders, and particularly for detecting variable nodes in trapping sets in a non-erasure channel LDPC decoder.

Abstract: This disclosure describes a low-density parity-check (LDPC) decoder that is configured to decode a codeword using an iterative process. The decoder includes a first syndrome memory configured to store a syndrome result determined in a previous iteration. The decoder further includes circuitry to flip bits of the codeword based on the syndrome result and one or more parity-check equations, and a second syndrome memory configured to update a current syndrome result during a current iteration based on the bits of the codeword that are flipped by the circuitry.

Abstract: A method and apparatus are described including receiving content, applying fountain codes to symbols of the content to generate fountain encoded symbols at one of a transport layer and an application layer and transmitting the generated fountain encode symbols via a mobile network that uses a multi-link delivery system. Also described are a method and apparatus including receiving data packets of fountain encoded symbols via a mobile network that uses a multi-link delivery system, decoding the received data packets of fountain encoded symbols to content data, attempting to recover any corrupted content data and determining if the content data was recovered.

Abstract: A method automatically performs regression testing of output of an altered variable information print job (program). In one embodiment, the method begins by supplying test data to a variable information (VI) print job to produce first sample data. Next, the method applies a numeric generation application to the sample data to produce numerical representations. Then, the VI print job is altered and the same test data is supplied to the altered VI print job to produce second sample data. Again, the numeric generation application is applied to the second sample data to produce more of the numerical representations. The numerical representations are then compared to identify altered data records caused by the altering of the VI print job.

Abstract: A client device or other processing device comprises a file encoding module, with the file encoding module being configured to separate a file into a plurality of sets of file blocks, to assign sets of the file blocks to respective ones of a plurality of servers, to define a plurality of parity groups each comprising a different subset of the plurality of servers, to assign, for each of the servers, each of its file blocks to at least one of the defined parity groups, and to compute one or more parity blocks for each of the parity groups. The file blocks are stored on their associated servers, and the parity blocks computed for each of the parity groups are stored on respective ones of the servers other than those within that parity group. Such an arrangement advantageously ensures that only a limited number of parity block recomputations are required in response to file block updates.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. In some cases, embodiments include a variable length data decoder circuit that is operable to apply a decode algorithm to the encoded input based upon a first selected H-Matrix to yield a first decoded output and apply the decode algorithm to the encoded input based upon a second selected H-Matrix to yield a second decoded output.

Abstract: The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved.

Abstract: An embodiment of an apparatus for encoding. For this embodiment of the apparatus, an encoder block is coupled to receive input data. The encoder block has an R-matrix block. The R-matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n?1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n?1) parity bits to generate an (n) parity bit 9-to-7.

Abstract: An encoder block to receive input data has a KR-Matrix block. The KR-Matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n?1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n?1) parity bits to generate an (n) parity bit.

Abstract: According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.

Abstract: Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows.

Abstract: According to at least one embodiment, a storage apparatus reads first sector data and a first error correcting code. The storage apparatus performs first decoding for the read first sector data using the read first error correcting code. The storage apparatus stores an error correction result by the first decoding. The storage apparatus performs second decoding for decoding-data associated with a second error correcting code using the second error correcting code. The storage apparatus transfers the second error correcting code and the decoding-data via the first buffer storing the error correction result.

Abstract: A method may include storing data in one or more first-type stripes spanning a plurality of N storage resources and having N?1 data strips for storing the data and a parity strip for storing parity information for the data stored to the particular first-type stripe and each of the plurality of storage resources includes one of a data strip or a parity strip of the particular first-type stripe if the data to be stored exceeds a threshold size. If the data to be stored does not exceed a threshold size, the method may include storing the data in a second-type stripe and a third-type stripe each spanning N storage resources, such that each stripe comprises N?1 data strips for storing the data and a metadata strip for storing address information for the corresponding second-type strip or third-type strip.

Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Abstract: A group of numbers from which the smallest and second-smallest are to be selected are compared in a cascaded tree. Each comparison stage will select the smallest number from two numbers output by the previous stage, into which four numbers are input. The second-smallest number is one of the other three inputs to the previous stage and, as before, all bits of the second-smallest number will not be known until the smallest number is determined. However, because at each stage of the determination, the next stage is reached because the bit values being examined are the same, those bit values of the second-smallest number (and indeed of the smallest number) are known ahead of the final determination of the smallest number. Accordingly, one can begin to output bits of the second-smallest number (as well as of the smallest number) even before that final determination.

Abstract: Systems and methods for decoding a received codeword are provided. The received codeword is decoded based on a parity code to produce a plurality of checks. A first unsatisfied check is selected from the plurality of checks, and a first set of symbol positions in the received codeword that are connected to the first unsatisfied check is identified. A second set of symbol positions in the received codeword that are not connected to the first unsatisfied check is identified. The received codeword is modified by setting the first set of symbol positions to first predetermined values and by setting the second set of symbol positions to second predetermined values. The modified received codeword is decoded based on the parity code.

Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate.

Abstract: A demodulation unit demodulates a received signal in which carrier wave of a navigation message that is modulated according to a BPSK modulation scheme are included. An error detection processing unit performs an error detection process on the demodulation result using an error detection bit that is included in the demodulation result. A verification word generator generates a verification word using the demodulation result and a check code when an error is detected by the error detection process, the check code being determined in advance for each bit of the navigation message based on a predetermined encoding rule. An estimation unit estimates an originating bit of a demodulation error by comparing the verification word generated by the verification word generator with a verification word table stored in a storage unit. A correction unit corrects the demodulation result by inverting the bit values of bits subsequent to the estimated originating bit.

Abstract: A non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the device comprises one or more non-volatile memories for storing data and a memory controller for carrying out control of the non-volatile memory. The memory controller writes data to the error correcting group and writes a provisional error correcting code with respect to the data to the parity table if a data size is smaller than the first size when writing the data.

Abstract: An NoC-based error correction apparatus capable of supporting a network interface that transmits a flit between Tx and Rx IP-elements includes: an encoder configured to receive a k-bit flit from the Tx IP-element and encodes the k-bit flit into n-bit data; and a decoder configured to receive the n-bit data, decode the n-bit data into the k-bit flit, and output the k-bit flit, the decoder having an error correction circuit for correcting an error in the n-bit data, wherein a t-bit adaptive error correction code having a variable error correction capability depending on the number of bits (n) of the received data is applied to the error correction circuit, the error correction capability is proportional to the number of bits (n) of the received data, and the t-bit error correction code has the number of bits proportional to the number of bits (n) of the received data.

Abstract: A data access request is received specifying a data block stored in a stripe of a parity group that includes a plurality of data storage devices to store data blocks and a parity storage device to store parity information for the data. The stripe includes a data block from each of the plurality of data storage devices and the stripe includes a parity block from the parity storage device. An error is detected in the data block specified by the data access request. The error is identified as a lost write error for the data block or a lost write error for the parity block. Identifying the error includes comparing a first storage device signature stored in a metadata field associated with the data block to a second storage device signature stored in a label block identifying a data storage device where the data block is stored.

Abstract: In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, a plurality of information bits to be included in the PHY data unit is received. A number of padding bits that need to be added to the information bits such that the information bits, after having been encoded, fill an integer number of orthogonal frequency division multiplexing (OFDM) symbols is determined. The number of padding bits is added to the information bits prior to encoding and the information bits are parsed to a number of encoders. The information bits are encoded to generate coded data bits. A last block of the data unit is encoded differently from the previous blocks. The PHY data unit to include the coded data bits is generated.

Abstract: A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.

Abstract: An electronic communication system including at least first and a second communication units (master, slave) which are connected to one another by means of at least one first data line, wherein the communication system has a data transmission protocol which is designed such that at least one defined communication process comprises the transmission of a synchronization packet (frame sync) and/or of an identification packet (ID) and/or a command packet (CMD) and/or of an address packet (ADDR) from the first communication unit (master) to at least the second communication unit (slave) via at least the first data line.

Abstract: Biometric data relating to a biological part are processed by obtaining, on the one hand, a first set of transformed biometric data (f(B1)) by applying at least one irreversible transformation to a first set of biometric data (B1), and, on the other hand, a second set of transformed biometric data (f(B2)) by applying said transformation to a second set of biometric data (B2). Thereafter, a decision is made as to whether the second biometric data set corresponds to the first biometric data set on the basis of a comparison between the first transformed biometric data set and the second transformed biometric data set, said comparison being performed at the bit level of a digital representation of said first and second transformed biometric data sets as a function of an error corrector code word.

Abstract: Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.

Abstract: A semiconductor memory device comprising of a parity check unit configured to receive a command signal and a parity signal to perform error checking in the command signal and output a parity indication signal; a delay unit including a plurality of registers configured to time delay by n clock cycles the parity indication signal and output a delayed parity indication signal; a command register configured to time delay by n clock cycles the command signal and output a delayed command; and a decoder configured to pass or block the delayed command signal based on the delayed parity indicator signal.

Abstract: Provided are a method of decoding an LDPC code for producing several different decoders using a parity-check matrix of the LDPC code, and an LDPC code system including the same. The system includes: an LDPC encoder outputting an LDPC codeword through a channel; a first LDPC decoder decoding the LDPC codeword received through the channel, and when the decoding has failed in a second LDPC decoder, decoding the LDPC codeword according to original parity check matrix of the LDPC codeword, using soft information newly generated after the decoding is ended in the second LDPC decoder; and the second LDPC decoder, when the decoding has failed in the first LDPC decoder, receiving the soft information on each bit from the first LDPC, and decoding the LDPC codeword according to a new parity-check matrix produced from the parity-check matrix of the LDPC codeword using the received soft information on each bit.

Abstract: A data stream is transmitted from a transmitting device to a receiving device via a communication network. Data of the data stream is transmitted to the receiving device by using a transport protocol without data acknowledgement. In a transmission method, parity-encoding parameters for parity encoding a data set of the data stream is determined via the transmitting device. The transmitting device also generates parity data from the data set by using the determined parity-encoding parameters. The transmitting device further transmits the generated parity data to the receiving device via the communication network by using a transport protocol with data acknowledgement.

Abstract: A system and method are provided for ensuring reliable data transfers by automatically recovering from un-correctable errors detected in data traversing throughout a system and being retrieved from an unreliable intermediate data buffer between a first memory and a secondary slower memory. Additionally, measures to compensate for the use of unreliable or error-prone components and interconnects, such as, for example, SRAM memory as a temporary buffer are provided. Further, measures to detect and correct errors—whatever the type—injected or occurring at any stage throughout traversal of the system are provided.

Abstract: A nonvolatile semiconductor memory outputs the first parity flag corresponding to the error-corrected read data from the second input/output pin in synchronization with the error-corrected read data in the data buffer outputted from the first input/output pin.

Abstract: A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include: a data decoder circuit, a decoder log, a mis-correction detection circuit, and a controller circuit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.

Abstract: An apparatus for a dual mode low density parity check (LDPC) decoder including edge random access memory (RAM), last-in-first-out/first-in-first-out (LIFO/FIFO) RAM, channel RAM, and parallel datapath engines, where the datapath engines include a standard belief propagation decoding (SBD) datapath and a layered belief propagation decoding (LBD) datapath, where the SBD datapath includes a shifter, an accumulator, multiplexers, and a g( )_sbd calculator, and where the LBD datapath includes the shifter, the multiplexers, and a g?( )_lbd calculator.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.