Abstract: Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Abstract: In a transmission apparatus, a first parity calculation controller calculates parity by the frame and inserts a calculation result into a next frame to a first frame sequence. A second parity calculation controller calculates the parity by the frame and inserts a calculation result into a next frame to a second frame sequence. The second parity calculation controller receives from the first parity calculation controller first parity data which is a parity calculation result by the first parity calculation controller and which has the same value as that of a parity calculation result to be inserted into a target frame of a parity calculation in the second frame sequence. Then, the controller calculates the parity of the target frame including the first parity data and second parity data which is a parity calculation result of a previous frame in the second frame sequence before one frame of the target frame.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system.

Abstract: Systems and techniques for serial data stream operations are described. A described system includes a serial bus communicatively coupled with a memory structure to handle a serial data stream from or to the memory structure; generators configured to generate enablement signals that are associated with different bit-groups of the serial data stream, each of the enablement signals including pulses that are aligned with time-slots that are associated with a respective bit-group; logic elements configured to store internal states and produce output signals that are based on the serial data stream, the enablement signals, and the internal states, and circuitry configured to capture values. Each of the enablement signals enables a respective logic element to selectively change a respective internal state responsive to bit-values of a respective bit-group. Each of the captured values represents an output of a respective logic element that is responsive to all bit-values of a respective bit-group.

Abstract: A data encoding system includes an interleaving module, a generating module, and an insertion module. The interleaving module is configured to receive a data stream. The data stream includes a plurality of data blocks. The interleaving module is configured to, for each data block of a selected subset of the plurality of data blocks, swap positions of a pair of adjacent bits of the data block. The generating module is configured to (i) receive the data stream and (ii) for each of the plurality of data blocks, generate at least one corresponding error checking bit. The insertion module is configured to (i) receive the plurality of data blocks as modified by the interleaving module and (ii) generate an output data stream by inserting the at least one corresponding error checking bit into each one of the plurality of data blocks received from the interleaving module.

Abstract: There exists a need to reduce re-transmission delays in real time feeds (such as video) by sending the packet with sufficient repair/recovery information inside the packet container so the relaying stations and/or the receiving devices can fix errors in transmission by perusing the contents of the packet and the repair information, and modify the packet and then relay it. By providing the relaying station the ability to fix the error, retransmission of the packet is avoided along each relay station along the network path from source to destination and also by receiving devices that would otherwise request a re-transmission. This application teaches a method so real time streams (e.g. video) may be more efficiently transported over a CSMA based network.

Abstract: A decoder-implemented method for layered decoding that, when the decoder converges on a near codeword using an initial schedule, (i) selects a subsequent schedule from a schedule set based on the layer Lmaxb of the near codeword, which layer contains the greatest number of unsatisfied check nodes and (ii) re-performs decoding using the subsequent schedule. When used in an offline schedule-testing system, the layered-decoding method (i) identifies which schedules, out of a population of schedules, correctly decode a decoder input codeword and (ii) associates the identified schedules with the Lmaxb value of the near codeword.

Abstract: A method of RAID migration comprising reading first and second blocks from a first RAID array. Said first blocks are written to a second RAID array within a first write cycle. Said second blocks are read simultaneously with a portion of said first write cycle in a pipelined fashion. In a first embodiment, pipelining increases the speed of RAID migration from a one-disk stripe array to a two-disk mirror array. In a second embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a two-disk mirror array to a three-disk RAID 5 array. In a third embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a three-disk RAID 5 array to a four-disk RAID 5 array.

Abstract: Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

Abstract: In one embodiment, a turbo equalizer is selectively operable in either first or second modes. In the first mode, layered (low-density parity-check (LDPC)) decoding is performed on soft-output values generated by a channel detector, where, for each full local decoder iteration, the updates of one or more layers of the corresponding H-matrix are skipped. If decoding fails to converge on a valid LDPC-encoded codeword and a specified condition is met, then LDPC decoding is performed in a second mode, where the updates of all of the layers of the H-matrix are performed for each full local decoder iteration, including the one or more layers that were previously skipped in the first mode. Skipping one or more layers in the first mode increases throughput of the decoder, while updating all layers in the second mode increases error correction capabilities of the decoder.

Abstract: A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.

Abstract: A method for wireless backhaul communication comprising receiving, by a wireless backhaul transmitter, a data stream in a bit format and generating, by the wireless backhaul transmitter using a single-carrier block transmission scheme, a radio frame to include a plurality of physical data channel (PDCH) blocks, a pilot signal (PS) block and a physical control channel (PCCH) block with each block type pre-appended with a cyclic prefix (CP). A length of the PS block in symbols, a length of the PCCH block in symbols and a length of the PDCH block in symbols is determined by a frequency band, a bandwidth, and a channel condition. The wireless backhaul transmitter then transmits the radio frame.

Abstract: A non-volatile semiconductor memory device can include a RAID controller configured to, upon data recording, distributively record a plurality of pieces of division data obtained by dividing the corresponding data and parity data generated from the division data in respective non-faulty blocks of a plurality of memory mats with reference to a bad block table, upon data reading, read a plurality of pieces of division data and parity data corresponding to designated data from respective blocks of the plurality of memory mats, and when an error occurs, recover data of a memory mat in which the error has occurred using data of another memory mat, store the recovered data in a block of the same memory mat in which the error has occurred other than a previous block, and store data representing the block in which the error has occurred in the bad block table.

Abstract: A memory system is provided. The memory system includes a memory element that is configured to selectively output data stored to and data fetched from the memory element. An error checking station is configured to receive the data stored to and the data fetched from the memory element. The error checking station is further configured to perform error checking on the data.

Abstract: Method of elementary updating a check node of a non-binary LDPC code during a decoding of a block encoded with said LDPC code, comprising receiving a first input message (U) and a second input message (V) each comprising nm doublets having a symbol and an associated metric, delivering an output message (S) possessing nm output doublets by computing a matrix of nm2 combined doublets on the basis of a combination of the doublets of the two input messages (U,V), and reducing the number of the combined doublets so as to obtain the nm output doublets of the output message (S) possessing the nm largest or lowest metrics. The method further includes tagging redundant symbols within each input message (U, V) and fixing same at a reference value, the value of the metric of each combined doublet resulting from a combination of at least one doublet comprising a tagged redundant symbol.

Abstract: Apparatus and methods for generating checksums may process two or more segments of a message in parallel, and may be used with a communications channel having time slots. An apparatus may include a cumulative checksum generator to generate a cumulative checksum for a message, a partial checksum generator to generate one or more partial checksums from one or more respective message segments, and a speculative checksum generator to generate a speculative checksum for each of one or more time slots. In one aspect, a partial checksum corresponding with an initial segment of the message may be generated from at least an initialization vector. A speculative checksum selector may select a first speculative checksum for use in determining whether the message was transmitted without error. The generating of partial and speculative checksums results in a maximally pipe-lined architecture with speed limited only by a minimal cumulative CRC calculation that is fundamentally unavoidable.

Abstract: A plurality of information bits are encoded using a parity-check matrix that is equivalent to a modular code matrix. The modular code matrix is a diagonal sub-matrix structure immediately above a connection layer that includes a plurality of diverse connection layer sub-matrices, all but at most one of which are below corresponding diagonal matrix structure sub-matrices. The information bits are assembled with a plurality of parity bits produced by the encoding to provide a codeword that is exported to a medium. Preferably, all the diagonal matrix structure sub-matrices are identical. Preferably, some of the parity bits are computed using only diagonal matrix structure sub-matrices.

Abstract: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by incorporating results from a previous decoding iteration. In one embodiment, a final multiplexer selects between the final detector output or a previous detector output based on the absence or presence of defective data. In another embodiment, the branch metrics for the defective data, which otherwise would be combined with a priori LLRs from an outer decoder of a prior stage, are ignored so that the a priori LLRs themselves are used alone. The two embodiments can be used together.

Abstract: An integer partitioning unit inputs an order p of a finite group G and an integer e, and calculates an integer e1 and an integer e2 that satisfy e1·e?e2 (mod p) based on the order p of the finite group G and the integer e which are input. A verification value calculation unit inputs an element s of the finite group G and an element h of the finite group G, and calculates an element a (=e1·h?e2·s) of the finite group G based on the element s and the element h which are input and the integer e1 and the integer e2 which are calculated by the integer partitioning unit in the integer partitioning process. A verification judging unit judges, based on the element a calculated by the verification value calculation unit, whether or not the element a is an identity element O of the finite group G. Hence, whether or not h =e·s is judged at high speed.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant.

Abstract: Provided is a relay transmission method capable of obtaining the diversity effect even when a relay station has detected an error in a relay signal when performing communication between a base station and a mobile station via a relay station. In the relay station used in this method, a decoding unit (104) performs error-correction-decoding of a systematic bit by performing repeated decoding such as a turbo decoding by using a parity bit and obtains a decoding result formed by a systematic bit after the error-correction-decoding. An error judging unit (105) judges whether the decoded result has an error by using CRC (Cyclic Redundancy Check). An encoding unit (106) performs error-correction-encoding of the decoded result and obtains a systematic bit after error-corrected-encoded and a parity bit.

Abstract: A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

Abstract: This disclosure introduces the concept of a strategy for a Convolutional Turbo Code decoder to make a prediction with regards to the likelihood of convergence. If a failure of convergence appears likely, the decoding process is aborted, The predictions regarding failure of convergence are made at the end of each half-iteration in a decoding process, leading to more efficient use of decoders in a system.

Abstract: A data rate matching method is disclosed. More particularly, a rate matching method using at least two parameters is disclosed. The rate matching method includes selecting bits from an input bitstream using a primary-indication parameter for selecting at least one bit and a secondary indication parameter for canceling the selection using the primary indication parameter or additionally selecting unselected bits, and processing the selected bits according to a rate matching mode so as to generate an output bitstream. By using the rate matching method, highspeed processing is realized by a simple calculation and the locations of target bits can be efficiently decided using at least two indication parameters. Accordingly, it is possible to reduce a calculation amount or improve performance.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. In an aspect, LDPC encoding and decoding of packets of varying sizes may be supported with a set of base parity check matrices of different dimensions and a set of lifting values of different powers of two. A base parity check matrix G of dimension mB×nB may be used to encode a packet of kB=nB?mB information bits to obtain a codeword of nB code bits. This base parity check matrix may be “lifted” by a lifting value of L to obtain a lifted parity check matrix H of dimension L·mB×L·nB. The lifted parity check matrix may be used to encode a packet of up to L·kB information bits to obtain a codeword of L·nB code bits. A wide range of packet sizes may be supported with the set of base parity check matrices and the set of lifting values.

Abstract: A memory includes cells at intersections of word lines and bit lines, word and bit line selection mechanisms and a programming mechanism. The cells on each bit line are connected in series. Cells of a word line are programmed simultaneously. For low-power reading, only some of the bit lines that intersect the word line at the programmed cells are selected and only the cells at those intersections are sensed. Another type of memory includes a physical page of cells, a sensing mechanism and a selection mechanism. Hard bits are sensed from all the cells of the physical page. Only some of those cells are selected for sensing soft bits. Another memory includes a plurality of cells, a sensing mechanism, an export mechanism and a selection mechanism. Hard and soft bits are sensed from all the cells of the plurality. Only some of the soft bits are selected for export.

Abstract: To decode a manifestation of a codeword in which K information bits are encoded as N>K codeword bits, messages are exchanged between N bit nodes and N?K check nodes. During computation, messages are expressed with a full message length greater than two bits. In each iteration, representations of at least some of the exchanged messages are stored. For at least one node, if representations of messages sent from that node are stored, then the representation of one or more of the messages is stored using at least two bits but using fewer bits than the full message length, and the representation of one other message is stored with full message length. Preferably, the messages that are stored using fewer bits than the full message length are messages sent from check nodes.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: An error correction method corrects and replaces erroneous digital signal samples (having N companded bits) in a receiver after ascertaining by parity check that a sample is erroneous. The method chooses M MSBs where M is less than or equal to N, and produces M test samples, each test sample being obtained by inverting a single bit from the M bits, keeping other bits unaltered. Each test sample is expanded and passed through a selected low pass filter (e.g., 15 kHz) to obtain a filtered output and a differential value between the test sample and its filtered output. The test sample producing the least differential value is chosen to replace the erroneous signal sample. The technique is applicable in NICAM demodulators receiving 14 bit sample signals (at 32 kHz) companded to (N) 10 bits from which (M) 6 MSB parity encoded bits are chosen for producing test samples.

Abstract: A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes.

Abstract: Method and system embodiments of the present invention are directed to encoding information in ways that are compatible with constraints associated with electrical-resistance-based memories and useful in other, similarly constrained applications, and to decoding the encoded information. One embodiment of the present invention encodes k information bits and writes the encoded k information bits to an electronic memory, the method comprising systematically encoding the k information bits to produce a vector codeword, with additional parity bits so that the codeword is resilient to bit-transition errors that may occur during storage of the codeword in, and retrieval of the codeword from, the electronic memory, ensuring that the codeword does not violate a weight constraint, and writing the codeword to the electronic memory.

Abstract: Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

Abstract: A parity-check-code decoder includes: a verifying device that multiplies (N) bit nodes by a matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator that generates a reliability index for each of the bit nodes in accordance with a channel; a reliability-updating device that uses the bit nodes and the check nodes to exchange message iteratively, and following each iteration, updates (N) exchange results corresponding to the (N) columns; and a recording controller that includes a separator, a quantizing determiner and a quantizer. The separator divides the matrix into at least one column group based on the characterizing signals. The quantizing determiner determines a shift signal for each column group based on the characterizing signals. The quantizer quantizes the characterizing signals according to the shift signals for subsequent output.

Abstract: An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information.

Abstract: Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows.

Abstract: Some embodiments of the invention shift the responsibility for creating parity and error correction blocks from the hardware or software RAID units or modules to the computer system's file system, allowing the file system's existing mechanisms of write atomicity to be used to help ensure consistency of the on-disk information throughout all or increasing portions of the information saving and/or updating cycle.

Abstract: A teletext decoder is provided which is suitable for decoding a packet of teletext signal to generate a teletext. The teletext decoder includes an error judgment device for judging the accuracy of a plurality of sliced bits, and correcting an error occurrence bit in the sliced bits on the basis of a plurality of sampling points and a slicer level when the plurality of sliced bits are incorrect.

Abstract: A method and apparatus to select bits for puncturing forward error correcting code frames to synthesize higher code rates. For example, there is provided a method of puncturing a digital data stream that includes a first parity bit stream and a second parity bit stream to generate a punctured bit stream. In one example, the method includes operating a first counting loop to select a first number of punctured bits from the first parity bit stream, comparing the first number of punctured bits with a desired number of bits for the punctured bit stream, and if the first number of punctured bits is less than the desired number of bits, operating a second counting loop to select a second number of punctured bits from the second parity bit stream until the sum of the first number of punctured bits and the second number of punctured bits is equal to the desired number of bits for the punctured bit stream.

Abstract: A transmitting apparatus transmits a plurality of data packets to a receiver in a communication system, by transmitting one or more data packets from a list of data packets to be transmitted, and determining whether an acknowledgment is received for each transmitted data packet. When it is determined that an acknowledgement has not been received for at least one data packet, referred to as an unacknowledged data packet, the apparatus selects one or more additional data packets from the list of data packets to be transmitted, generates one or more parity packets by encoding a block of data containing a combination of the selected one or more additional data packets and at least one unacknowledged data packet using a forward error correction scheme, and transmits at least one of the generated parity packets.

Abstract: A method for encoding data bits includes computing checksum parity bits based on the data bits. A set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense parity-check matrix. The dense parity-check matrix comprises sums of permutation sub-matrices.

Abstract: A data processing system has cache circuitry having a plurality of ways. Mirroring control logic indicates a mirrored way pair and a non-mirrored way of the plurality of ways. The mirrored way pair has first and second ways wherein the second way is configured to store cache data fields redundant to cache data fields of the first way. In one form, comparison logic, in response to an address hitting in the first way or the second way within the mirrored way pair, performs a bit comparison between cache data from the first way addressed by an index portion of the address with cache data from the second way addressed by the index portion of the address to provide a bit parity error signal. In another form, allocation logic uses a portion of the address and line locking information to determine whether a mirrored or non-mirrored way is selected for allocation.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: A system includes an error correction encoder that encodes data and produces parity bits, and a parity bit processor that disperses the parity bits across the data, placing respective i-bit parity sub-blocks between selected multiple-bit data sub-blocks. The system also modifies one or more of the bits in predetermined positions in respective data sub-blocks based on the bits of the parity sub-blocks that precede them, such that the precoding does not sign invert the data sub-blocks.

Abstract: Redundant storage of information is provided by distributing storage functions between a RAID controller and switching device. The switching device multi-casts writes to storage devices and to the RAID controller. The RAID controller generates parity for the information and writes the parity to the storage devices in space reserved for parity by the switching device. Information is read from the storage devices through the switching device without action by the RAID controller.

Abstract: An apparatus, system, and method for generating and decoding a longer linear block codeword using a shorter block length. The method comprises receiving data from a storage area and generating a codeword from the received data with an encoder, the codeword having a data portion and a parity portion, wherein the codeword has a first block length, and wherein the encoder applies a linear block code, the linear block code having a second block length that is shorter than the first block length.

Abstract: A system and method are provided for creating codewords using common partial parity products. The method initially accepts an algorithm for creating p indexed parity bit positions, where the parity bit for each position is calculated from mathematical operations performed on bits from n indexed user word positions. A first group of parity bit positions is found, where the parity bit for each position in the first group is calculated using at least a first number of common mathematical operations. A second group of parity bit positions is found, where the parity bit for each position in the second group is calculated using at least a second number of common mathematical operations. The common mathematical operations are subtracted from the first and second group of parity bit position calculations, so that unique mathematical operations can be found, associated with each parity bit position calculation in the first and second group.

Abstract: A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas for receiving data; a plurality of memory units for storing the received data; and a number of decoders configured to perform a Low Density Parity Check (LDPC) decoding operation. Each of the decoders further is configured to independently decode at least a portion of the received data using a portion of a decoding matrix. Each of the number of decoders coordinates the low density parity check decoding operation with other decoders. The decoders can use a parallel process, a pipeline process or a combination of a parallel and pipeline process.

Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate.

Abstract: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by incorporating results from a previous decoding iteration. In one embodiment, a final multiplexer selects between the final detector output or a previous detector output based on the absence or presence of defective data. In another embodiment, the branch metrics for the defective data, which otherwise would be combined with a priori LLRs from an outer decoder of a prior stage, are ignored so that the a priori LLRs themselves are used alone. The two embodiments can be used together.