Abstract: Embodiments of a decoder and method of decoding blocks of soft bits in a wireless receiver are generally described herein. Other embodiments may be described and claimed. In some embodiments, a memory is initialized with encoded input data and updated with sums of extrinsic reliabilities. Decoded output data is provided from the memory after a predetermined number of iterations.

Abstract: Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

Abstract: A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding.

Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

Abstract: An apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix is provided. The apparatus includes an interleaver for interleaving a descending bit-ordered codeword having a predetermined size and in accordance with a predetermined modulation scheme; and a bit mapper for mapping codeword bits constituting the interleaved codeword in accordance with a predetermined mapping scheme that takes into account degrees of the codeword bits and reliability characteristics of modulation symbol-constituting bits based on the predetermined modulation scheme.

Abstract: Embodiments of the present invention provide a method, system, and computer program product for optimizing I/O operations performed by a storage server operating on behalf of multiple clients to access data on a plurality of storage devices (disks). Embodiments of the present invention eliminate the need for selected read operations to write new data to physical data blocks by zeroing the physical data blocks to which new data will be written. Additionally, the need for reading old parity to compute new parity is eliminated. Instead, new parity is computed from the data to be written without the need of old parity or the storage server sends a command to a disk that stores parity. A module implemented at the disk that stores parity executes the command without reading, by the storage server, old parity. Eliminating the need for reading old data and for reading old parity eliminates some rotation latency and improves overall system's performance.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: The present invention is intended to provide an LDPC coding scheme which is capable of efficiently implementing a high-performance and high-speed encoder and decoder of an error correcting code suitable for the field of communications such as mobile communications. As to the configuration, a Tanner graph for representing codes with variable nodes and check nodes is used to classify the individual nodes into a plurality of categories. For calculating a probability propagation in iterative decoding, weighting previously determined for each category is performed on a log-likelihood ratio (LLR) subjected to propagation.

Abstract: A system, method and article of manufacture are disclosed for processing Low Density Parity Check (LDPC) codes. The system comprises a multitude of processing units for processing the codes; and a processor chip including an on-chip, multi-port data cache for temporarily storing the LDPC codes. This data cache includes a plurality of input ports for receiving the LDPC codes from some of the processing units, and a plurality of output ports for sending the LDPC codes to others of the processing units. An off-chip, external memory stores the LDPC codes and transmits the LDPC codes to and receives the LDPC codes from at least some of the processing units. A sequence processor controls the transmission of the LDPC codes between the processor units and the on-chip data cache so that the LDPC codes are processed by the processing units according to a given sequence.

Abstract: Encoding of a low-density parity check code uses a block-circulant encoding matrix built from circulant matrices. Encoding can include partitioning data into a plurality of data segments. The data segments are each circularly rotated. A plurality of XOR summations are formed for each rotation of the data segments to produce output symbols. The XOR summations use data from the data segments defined by the circulant matrices. Output symbols are produced in parallel for each rotation of the data segments.

Abstract: A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.

Abstract: A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction.

Abstract: Disclosed is an apparatus for recovering data in the case of single or double failures of N partial data blocks generated by dividing the data where N is a natural number greater than 1. The apparatus recovers the data on the basis of a Galois field product computation table including first and second search key data, and products of the first and second search key data. The first search key data includes possible symbol values. The second search key data includes a weighting value set and an inversed weighting value set. The weighting value set includes weighting values each assigned to one of the N partial data blocks and different from each other, and is closed under addition in the Galois field. The inversed weighting value set includes multiplicative inverses of the weighting values included in the weighting value set.

Abstract: An error correction system for decoding transmitted data in multichannels is disclosed. The system uses low density parity check nodes. A method of error correction using LDPC is also disclosed.

Abstract: A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.

Abstract: A method that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor (50) of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 of m rows and m columns on the right side. The processor (50) generates partial matrix H2 as a unit matrix. The processor (50) generates partial matrix H1 to satisfy the conditions that, when any two rows contained in partial matrix H1 are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor (50) then joins partial matrix H1 and partial matrix H2 to generate parity check matrix H.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one item from one or more of the other parity fields. A decoder can regenerate as many as M missing or corrupted fields of either data or parity using combinations of correct and/or previously corrected items as inputs using M independent parity equations to solve for and correct each missing or corrupted item in turn.

Abstract: An add-compare-select (ACS) unit generates first path metrics having a first bit-pair and a most significant bit-pair (MSB) each including a high bit and a low bit. A first ACS circuit produces the first bit-pair and a first carry. A limiting circuit generates the MSB based on the first carry, and limits the MSB to a first predetermined value. A MSB maximum select (MS) unit receives an MSB of second path metrics from another ACS unit, and compares the MSBs of the first and the second path metrics to determine MSB decision signals based on maximum likelihood selection. A MSB storage unit stores the MSB of the first path metrics. A reset unit resets the high bit of the MSB of the first path metrics to a second predetermined value when the high bits of the MSBs of the first and the second path metrics reach the first predetermined value.

Abstract: A method of preparing data for transmission. The method includes providing a block of data, generating a plurality of first dimension code words including first dimension forward error correction FEC elements, the elements of each code word may be used interchangeably to reconstruct a data portion of the block corresponding to the code word, defining a plurality of second dimension source words formed of the generated elements and generating for at least two of the defined second dimension source words, different numbers of parity elements.

Abstract: Method and apparatus for using long FEC codes in a content distribution system is described. One aspect of the invention relates to encoding frames of content. Each frame is partitioned into un-coded bits and bits to be encoded. For each frame, an FEC code is applied to the bits to be encoded to generate a codeword. Groups of bits from the codeword are divided among a plurality of channels. Symbols formed from the groups of bits and the un-coded bits are mapped to a constellation for each of the plurality of channels. The symbols are modulated across a respective plurality of bonded channels for transmission.

Abstract: Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.

Abstract: A method of operating a matrix checksum includes the steps of determining a column checksum for the data bytes in an information packet. A row checksum for the data bytes in an information packet is determined. The information packet including the column checksum and the row checksum is transmitted.

Abstract: Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one item from one or more of the other parity fields. A decoder can regenerate as many as M missing or corrupted fields of either data or parity using combinations of correct and/or previously corrected items as inputs using M independent parity equations to solve for and correct each missing or corrupted item in turn.

Abstract: An embodiment of the present invention provides an apparatus, comprising a transceiver capable of a unified quasi-cyclic low-density parity-check structure for variable code rates and sizes using a unified base matrix definition. This base matrix definition may be a concatenation of multiple square matrices Sm×Rm=(Sm×mR|Sm×mR?1| . . . |Sm×m3|Sm×m2|Sm×m1) and the base matrix for rate (r?1)/r may be Sm×rm=(Sm×mr|Sm×mr?1| . . . |Sm×m3|Sm×m2|Sm×m1) for r=2, 3, . . . , R.

Abstract: A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix. The system also comprises a plurality of parity check update modules (PCUMs) in parallel with each other, coupled to the first adder module and adapted to update the check node value estimate, and a second adder module coupled to the plurality of PCUMs and adapted to update the probability value estimate using the extrinsic estimate and the updated check node value estimate. The PCUMs process at least some columns of at least some rows of the parity check matrix in a serial fashion.

Abstract: An architecture and method for executing write commands in a storage array is disclosed. The data strips of the data stripes of the storage array each include a parity check bit. The parity strip of each stripe includes a plurality of parity check bits, each of which is uniquely associated with one of the data strips of the stripes. The inclusion within each data stripe of parity bits associated with each data strip and the party strip provides a method for identifying a corrupted or degraded data condition that occurs as a result of a server failing fails during a write command.

Abstract: Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: A memory checking device for cells arranged in memory rows and columns, wherein, in a state of integrity, the memory has parity values for two memory rows or two columns that differ from each other with the same parity value calculation rule or with different parity value calculation rules or are equal with different parity value calculation rules. The checking device includes a reader for reading out the binary memory values of the two memory columns or rows. The memory checking device includes a checking unit designed to calculate the parity value according to the calculation rule valid for the corresponding memory column or row for the two memory columns or the two rows, and to compare it with an expected parity value for the state of integrity, and, in the case of a deviation, to provide an error indication in one of the rows or one of the columns.

Abstract: High throughput parallel LDPC decoders are designed and implemented using hierarchical design and layout optimization. In a first level of hierarchy, the node processors are grouped on the LDPC decoder chip, physically co-locating the processing elements in a small area. In a second level of hierarchy, clusters, e.g., subsets, of the processing elements are grouped together and a pipeline stage including pipeline registers is introduced on the boundaries between clusters. Register to register path propagating signals are keep localized as much as possible. The switching fabric coupling the node processors with edge message memory is partitioned into separate switches. Each separate switch is split into combinational switching layers. Design hierarchies are created for each layer, localizing the area where the interconnect is dense and resulting in short interconnect paths thus limiting signal delays in routing.

Abstract: The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S21. Then, at step S22, an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S21. Where the processing at step S22 is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.

Abstract: A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor (50) of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 of m rows and m columns on the right side. The processor (50) generates partial matrix H2 as a unit matrix. The processor (50) generates partial matrix H1 to satisfy the conditions that, when any two rows contained in partial matrix H1 are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor (50) then joins partial matrix H1 and partial matrix H2 to generate parity check matrix H.

Abstract: A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data parity includes storing a plurality of data bits in the memory cells, scanning a row of memory cells independently of a memory read operation to ascertain the stored data bits; and determining parity for the row of memory cells by the results of the scanning. The method is accomplished by means of a dedicated parity scanning circuit.

Abstract: A transmitter (1) converts an input signal from a microphone (2) into a plural-bit digital signal by means of an A/D converter (4) at predetermined time intervals. An encoder (6) divides the digital signal into plural blocks and adds a parity bit to each block to thereby form a coded signal. A transmitting unit (8) modulates a carrier with the coded signal and transmits the modulated carrier through an antenna (10). A receiver (12) includes two tuning units (18A, 18B). Corresponding coded signals outputted from the tuning units (18A, 18B) are inputted to a decoder (20). The decoder (20) makes a parity check on respective blocks of the corresponding coded signals and selects and outputs an error-free one of the corresponding blocks of the corresponding coded signals.

Abstract: Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code. A novel approach is presented by which a GRS code may be employed to generate a wide variety of types of LDPC codes. Such GRS based LDPC codes may be employed within various types of transceiver devices implemented within communication systems. This approach may be employed to generate GRS based LDPC codes particular designed for various application arenas. As one example, such a GRS based LDPC code may be specifically designed for use in communication systems that operate in accordance with any standards and/or recommended practices of the IEEE P802.3an (10GBASE-T) Task Force.

Abstract: A PCI Express compliant method and apparatus for preventing corrupt data being transmitted from a retry buffer of a transmitting component to a receiving component over a PCI Express compliant link. The method including storing parity or electronic error correction bits for each data entry in the retry buffer along with the data itself and then comparing parity or electronic error correction bits generated from a copy of the data from the retry buffer to the parity or electronic error correction bits stored in the retry buffer. If the two sets of bits do not match, a PCI Express link between the transmitting component to a receiving component is forced down.

Abstract: A set of irregular LDPC (Low Density Parity Check) codes having a pseudo-random structure and low encoding complexity. A block-cyclic LDPC code has an irregular row or an irregular column weight and includes a parity check matrix and an encoding matrix each of which has a pseudo-random structure. This allows the code to have the irregular row weight or irregular column weight together with an overall randomness to the code structure. Blocks within the code can be shortened, adjacent blocks of code can be overlapped, and adjacent columns within a block can be arbitrarily permuted so to change the weighting of rows and columns. The LDPC codes are particularly useful in two-way communications system for an electrical distribution system (1) to restore data lost or corrupted during its transmission.

Abstract: A method for storing data for correction of multiple data storage failures in a storage array is presented. The storage array is organized as a plurality of sub-arrays, each sub-array including a set of data storage devices and a plurality of local parity storage blocks, each of the plurality of local storage blocks storing parity information for a corresponding sub-array. A plurality of diagonal parity sets is computed, one diagonal parity set for each sub-array. A global diagonal parity is computed by logically combining together a plurality of the diagonal parity sets. The global diagonal parity is stored in a plurality of global diagonal parity storage blocks.

Abstract: A transmitter and method include a LDPC encoder configured to encode source data, and a mapper configured to generate three coordinates in accordance with a 3D signal constellation where the coordinates include an amplitude coordinate and two phase coordinates. A laser source is modulated in accordance with each of the three coordinates to provide a transmission signal. A receiver, includes a demapper receives an input signal from three branches to demap the input signal using a three-dimensional signal constellation having three coordinates. The three branches include a direct detection branch, and two coherent detection branches such that the direct detection branch detects an amplitude coordinate of the input signal and the two coherent detection branches detect in-phase and quadrature coordinates of the input signal. A bit prediction module and at least one LDPC decoder are configured to iteratively decode bits by feeding back extrinsic LLRs to the demapper.

Abstract: In a communication system 10, a method and apparatus provide for decoding a sequence of turbo encoded data symbols. The channel nodes Rx, Ry and Rz are updated based on a received channel output, and the outgoing messages from symbol nodes (701, 707, 708) are initialized. The symbol nodes symbol nodes (701, 707, 708) are in communication with the channel nodes Rx, Ry and Rz. Updates of computational nodes C (704) and D (706) at different time instances are performed in accordance with a triggering schedule.

Abstract: Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.

Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). In one embodiment, an encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. A corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

Abstract: Disclosed are an error-detecting encoding apparatus for creating parity bits by error-detecting encoding processing, appending the parity bits to an input data string and encoding the data string, and an error-detecting decoding apparatus for detecting error using these parity bits. Data segmenting means segments an input data string, which is to undergo error-detecting encoding, into a plurality of sub-data strings, dividing means divides the segmented sub-data strings by a polynomial, which is for generating an error-detecting code, and calculates remainders, converting means applies conversion processing, which conforms to a segmentation position of the sub-data strings, to the remainders on a per-remainder basis, and combining means combines converted values, which have been obtained by the conversion processing, and outputs parity bits. An encoder appends this parity to a data string, and a decoder detects error using this parity.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: A method for decoding information received at a network device may include a first decoding process which applies a first algorithm iteratively until a stopping criterion is reached and a second decoding process which may flip a logic state of one or more bits. In one implementation using low density parity check (LDPC) codewords, bits may be flipped after evaluating check nodes having the lowest metrics and/or assessing the parity relationships of bit nodes and/or edges associated with those check nodes. Devices and systems for decoding are also disclosed as well as various other embodiments.

Abstract: One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.

Abstract: Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to variable node messages. The signs of messages received from variable nodes may be stored by the check node processor module of the invention for use in message extraction. The check node processor can process messages in variable node order thereby allowing the variable node processor and check node processor to operate on messages in the same order reducing or eliminating the need to buffer and/or reorder messages passed between check nodes and variable nodes. Graph structures which allow check node processing on one graph iteration to proceed before the previous graph iteration has been completed are also described.

Abstract: Decoding LDPC (Low Density Parity Check) code with new operators based on min* operator. New approximate operators are provided that may be employed to assist in calculating one or a minimum value (or a maximum value) when decoding various coded signals. In the context of LDPC decoding that involves both bit node processing and check node processing, either of these new operators (i.e., the min† (min-dagger) operator or the min? (min-prime) operator) may be employed to perform the check node processing that involves updating the edge messages with respect to the check nodes. Either of these new operators, min† operator or min? operator, is shown herein to be a better approximate operator to the min** operator.

Abstract: An error correcting apparatus includes a storing means for storing product code with n2 rows and n1 columns, an error correcting unit 5 that performs error correction for four code sequences simultaneously in parallel, and a bus control unit 2 for reading codes on four rows from the buffer memory 1 and transferring the codes to the error correcting unit 5. The bus control unit 2 reads and transfers four consecutive codes on each of four rows in order before shifting the reading position by four codes in the row direction.