Abstract: A method and apparatus to transmit turbo-encoded data in a multitone channel assigns the original data and selected parity bits across multitone subchannels allowing transmission of an entire turbo-encoded block within one or few symbol time frame. Parity bits are selected by a procedure using data derived by optimization using simulation of a single-channel system. The optimization determines, for a specified bit error rate, for each possible number of information bits per symbol, the code rate corresponding to the lowest signal-to-noise ratio. Alternatively, in the simulation non-identical integer values may be applied to the channels to approximate non-integer values of code rate and information bits-per-channel in the aggregate. The optimized data are used to determine an optimal code rate and SNR for each channel.

Abstract: A mechanism for decoding linear shifted codes employs two shift registers. The shift registers are independently controlled by an associated control unit. Initially, the received parity bits are stored in a first shift register and the global syndrome bits are stored in a second shift register. While the right-most cell in the first shift register contains a logical “0”, both shift registers are shifted right one position. When the right-most cell of the first shift register contains a “1”, the content of the right-most cell of the second shift register is recorded as a first bit of a syndrome code which identifies the position of an error with any groups with an error. If the value recorded is a “1”, a bit-wise exclusive OR operation is then performed on the values in the first and second shift registers, and the result is stored in the second shift register. Subsequently, the contents of the second shift register are shifted by one position.

Abstract: A method for preventing errors in transmission of a telecommunication signal via a network domain forming part of a network, wherein the signal is transmitted in the form of a succession of binary data frames via two border points in the network domain, and each of the frames comprises a parity array including one or more bits assigned for parity check and a temporary use array including a number of bits assigned to serve one or more temporary data channels between the two border points; the method comprising:

Abstract: An error correcting apparatus includes a storing means for storing product code with n2 rows and n1 columns, an error correcting unit 5 that performs error correction for four code sequences simultaneously in parallel, and a bus control unit 2 for reading codes on four rows from the buffer memory 1 and transferring the codes to the error correcting unit 5. The bus control unit 2 reads and transfers four consecutive codes on each of four rows in order before shifting the reading position by four codes in the row direction.

Abstract: Data read from a recording medium, such as a CD or DVD, is checked for errors and the errors are corrected in a fast and efficient manner. First, an error detection code (EDC) is appended to the data, which is arranged in matrix form, by performing a predetermined checking arithmetic operation. Then, a first checking operation is performed on the data using the EDC to generate a first sample value. The data is then error corrected in a first direction and a first correction value is generated if an error is detected. A second checking operation is performed in the first direction using the first correction value to generate a second sample value. The first and second sample values are compared and a first check value is generated. The data is then error corrected in a second direction and a second correction value is generated if an error is detected. A third checking operation is performed in the first direction using the second correction value to generate a third sample value.

Abstract: The present invention concerns a method and system for protection against corruption of data. In order to backup files to be stored in a storage medium, a set of redundant parity symbols is computed by encoding cross-sections across said files using a systematic code. These parity symbols and the files are then stored for later retrieval. If some of these files are erased, corrupted, damaged or infected by a virus, they are reconstructed by decoding the surviving files and the parity symbols.

Abstract: A method of encoding data is described herein. According to the method, source data elements are coded using one or more product codes having a common component code. The resulting one or more primary product codewords consist of a plurality of first codewords of the common component code. One or more first sets of codewords of the common component code are assembled such that each of the first sets comprises two or more distinct first codewords forming part of a same primary product codeword. Each of the codewords of each of the first sets is codeword-mapped to a second codeword of the common component code using a one-to-one codeword-mapping. One or more second sets of second codewords are provided, where each second set corresponds to a first set of codewords. The codeword-mapping includes re-ordering, according to a known interleaving pattern, the symbols within a codeword.

Abstract: An on-the-fly integrity checking system which dupicates data passing through a main systems bus, functions concurrently to recognize the size of data blocks being transferred from a sending module to a receiving module. Each word transferred is immediately parity checked. A counter indicates when the entire data block has transferred so as to initiate the comparison of an original block EDC signature with that of a internally generated EDC value to indicate the validity or invalidity of the data transfer. No delay is involved on the data transfer operations of the main system bus due to the integrity checking system operating independently as an independent module which does not delay data transfers on the main system bus.

Abstract: A scheme for protecting memory stored in a DRAM using a combination of horizontal and vertical parity data to detect and correct errors in a protected space of memory in which code is stored. The DRAM memory of this scheme is architected with the code stored in horizontally contiguous bytes and the vertical parity, generated when the code is compiled, also stored in horizontally contiguous bytes, but in a row of DRAM memory separate from those in which the code is stored.

Abstract: A data transmission system for transmitting information data with a parity of an error correcting code for correcting an error in the information data. A read-out controller controls a transmitter to transmit information data and a parity so that each data component of the information data obtained by dividing the information data of one data block area into a plurality of data components and each parity component of the parity obtained by dividing the parity of one block area into a plurality of parity components are transmitted at intervals of each sector having a sector address. The sector is defined as an data area obtained by dividing one data block area of a predetermined data amount into a plurality of sectors each having an identical data amount.