Abstract: A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

Abstract: A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a first iteration, the channel decoder decodes data read by the read circuit. In succeeding iterations, the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block decoder from an immediately preceding iteration. The storage system includes a threshold check circuit to select (i) an output of the soft linear block code decoder if the number of parity-check violations has a first relationship with respect to a threshold, or (ii) an output of the channel decoder if the number of violations has a second relationship with respect to the threshold. The storage system includes a decoder to decode an output of the threshold check circuit.

Abstract: A method for generating parity codes of a data sector having data information and main data. The main data is scrambled to generating outer-code parity. The main data is scrambled to generating inner-code parity. The outer-code parity generating is superior to the inner-code parity generating. The outer-code parity is generated by vertically scrambling the corresponding vertical data block.

Abstract: A memory error detection device for a memory having cells arranged in memory rows and columns, wherein the memory is occupied such that the protection memory row or column has a predetermined reference parity value in a state of integrity, the parity value is chosen so that a row or column error signaling a write-protected state of the memory also results in the reference parity value, with a binary value memory reader of the protection memory row or column. The memory error detection device includes a comparing device designed to calculate a test parity value for the memory values of the protection memory row or column read out and to compare it with a reference parity value expected for the protection memory row or column. The memory error detection device includes a detector designed to take an error measure when the test parity value does not match the reference value.

Abstract: A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file system with a RAID system. In response to a request to store (write) data on the array, the file system determines which disks contain free blocks in a next allocated stripe of the array. There may be multiple blocks within the stripe that do not contain file system data (i.e., unallocated data blocks) and that could potentially store parity. One or more of those unallocated data blocks can be assigned to store parity, arbitrarily. According to the dynamic parity distribution technique, the file system determines which blocks hold parity each time there is a write request to the stripe. The technique alternately allows the RAID system to assign a block to contain parity when each stripe is written.

Abstract: A communication channel including Reed-Solomon (RS) and single-parity-check (SPC) encoding/decoding. Multiple RS codewords are combined and then SPC encoded into an RS/SPC array. A soft-input soft-output (SISO) channel detector detects the RS/SPC encoded bits and provides soft (reliability) information on these bits. A combined RS and SPC error correction block provides a recovered user output. An iterative soft input decoding algorithm combines RS and SPC error correction.

Abstract: In a data recording method and a data recording apparatus relating to the present invention, ECC blocks using 36 product codes are recorded on 12 tracks through scanning operations performed three times. First of all, first sync-blocks each constituted by adding a C1 parity to the data string of video data constituting an internal encoding calculation data stream are sequentially recorded. When the first sync-blocks are completely recorded, second sync-blocks each constituted by adding the C1 parity to the data string of C2 parity constituting the internal encoding calculation data stream are sequentially recorded. By recording the C2 parity at one time in a later stage, the system delay can be minimized.

Abstract: A higher code rate Low-Density Parity Check (LDPC) matrix may be designed by concatenating additional matrices to a ?-rotation parity check matrix. The concatenated matrix may be selected such that the resultant LDPC matrix exhibits good expansion characteristics to enable the LDPC matrix to be used with variable block length codes. The codes may be designed by generating an ensemble of available codes, encoding them with information vectors of weight 1 and 2 and discarding codes with a low minimum distance. The approximate upper bounds for the remaining codes are then calculated and a small set of codes with the lowest bound under high signal to noise ratio is selected. The girth distributions for the remaining codes are then calculated and the code that has the minimum number of short cycles is selected. The selected code is concatenated to the original ?-rotation parity check matrix.

Abstract: An iterative method of correcting errors in a data block. Bad bytes are first identified using information derived from an 8B/10B decoding of the data block. Within each identified bad byte, suspect bits are subsequently identified using information derived from parity decoding of a row of the data block. Each suspect bit is then classified as either a confirmed error bit or an unconfirmed error bit using information derived from parity decoding of a column of the data block in which the suspect bit is located. Confirmed error bits are then corrected, the parity bits corresponding to the confirmed error bit reset, and the bad byte cleared. The process is then repeated if one or more bad bytes remain in the data block.

Abstract: A signal includes a runlength limited (RLL) encoded binary d,k channel bitstream, parameter d defining a minimum number and k defining a maximum number of zeroes between any two ones of the bitstream, or vice versa. The signal further includes a number of sections of respectively N successive RLL channel bits, called RLL rows, each RLL row representing a row parity-check code-word, in which a row-based parity-check constraint for the RLL row has been realized. K sections of respectively N successive channel bits, called column parity-check rows, are located at predetermined positions of a group of M RLL rows. The column parity-check rows include column parity-check enabling channel words, each realizing a column-based parity-check constraint for all corresponding segments of at least the M RLL rows of the group that correspond to a specific column parity-check enabling channel word, thereby constituting a column parity-check codeword.

Abstract: A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f; i, j)} for a code size corresponding to expansion factor zf are derived from {p(i,j)} by scaling p(i,j) proportionally, and a model matrix defined by {p(f,i,j)} is used to determine the parity-check bits for the f-th code.

Abstract: A method for determining r error detection bits of a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix. The parity control matrix includes at least two consecutive complementary columns. The present invention also relates to a method for determining a syndrome, as well as a coding and decoding circuit.

Abstract: A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f,i,j)} for a code size corresponding to expansion factor zf are derived from {p(i,j)} by scaling p(i,j) proportionally, and a model matrix defined by {p(f,i,j)} is used to determine the parity-check bits for the f-th code.

Abstract: An error correction coding apparatus includes a parity check matrix generation unit which generates a parity check matrix having a number of elements having a value of 1 in each row thereof, having a predetermined number of elements having a value of 1 in each column thereof, and having the other elements having a value of 0; a parity check matrix adjustment unit which receives the parity check matrix from the parity check matrix generation unit, searches the parity check matrix for a cycle forming group of four elements positioned at respective vertexes of a rectangle and having a value of 1, and when there is at least one cycle forming group, replaces the value of 1 of at least one element of the cycle forming group with the value 0 of another element, to output a adjusted parity check matrix without a cycle forming group therein; and an LDPC coding unit which receives the adjusted parity check matrix from the parity check matrix adjustment unit and receives an m-bit message word to perform LDPC coding.

Abstract: With two consecutive product-coded ECC blocks, EB1 and EB2, as a set, the rth row of first ECB block EB1 is followed by the rth row of second ECC block EB2 in such a way that the first row of first ECC block EB1 is followed by the first row of second ECB block EB2, which is followed by the second row of first ECC block ECB1, which is followed by the second row of second ECC block EB2, and so on, to interleave data on a row basis. That is, data of two ECC blocks, EB1 and EB2, is allocated alternately on a row basis. This allocation method allows an error to be distributed after reproduction even when a serious burst error extending 18 rows occurs in an ECC block.

Abstract: A method, system and program for generating parity in a data storage system are provided. The invention comprises organizing an incoming data block into a specified number of data stripes and cascading the data stripes into a parity creation mechanism. The parity creation mechanism creates a specified number of parity stripes based on the data stripes, wherein the number of parity stripes is independent of the size of the data block. The parity creation mechanism can operate offline to reconstruct lost data stripes and parity stripes without using critical system resources, wherein the number of devices required for stripe reconstruction is less than the combined number of data stripes and parity stripes.

Abstract: A decoding system and method for decoding parallel concatenated parity-check code defines a parity check matrix (e.g., a sparse parity check matrix) for the parallel concatenated parity check code. One or more bipartite graph representations are determined based on the parity check matrix with each of the one or more bipartite graph representations including bit nodes and check nodes. At least one of the one or more bipartite graph representations is decoded using an iterative decoding process (e.g., using an algorithm based on belief propagation).

Abstract: The Hamming distance of an array of storage devices is increased by generating a parity check matrix based on column equations that are formed using an orthogonal parity code and includes a higher-order multiplier that changes each column. The higher order multiplier is selected to generate a finite basic field of a predetermined number of elements. The array has M rows and N columns, such that M is greater than or equal to three and N is greater than or equal to three. Row 1 through row M?2 of the array each have n–p data storage devices and p parity storage devices. Row M?1 of the array has n?(p+1) data storage devices and (p+1) parity storage devices. Lastly, row M of the array has N parity storage devices.

Abstract: Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to variable node messages. The signs of messages received from variable nodes may be stored by the check node processor module of the invention for use in message extraction. The check node processor can process messages in variable node order thereby allowing the variable node processor and check node processor to operate on messages in the same order reducing or eliminating the need to buffer and/or reorder messages passed between check nodes and variable nodes. Graph structures which allow check node processing on one graph iteration to proceed before the previous graph iteration has been completed are also described.

Abstract: A method transforms a generalized parity check matrix representing a linear block binary code. First, an input generalized parity check matrix is defined for the linear block binary code. Auxiliary sets are formed from the input generalized parity check matrix and organized into a partially ordered set. The subsets of each auxiliary set are ordered in a list, and parity check equations are constructed from the list of ordered subsets. The parity check equations are translated into an output generalized parity check matrix, which can be used to decode a message encoded according to the linear block binary code.

Abstract: A technique efficiently corrects multiple storage device failures in a storage array. The storage array comprises a plurality of concatenated sub-arrays, wherein each sub-array includes a set of data storage devices and a local parity storage device that stores values used to correct a failure of a single device within a row of blocks, e.g., a row parity set, in the sub-array. Each sub-array is assigned diagonal parity sets identically, as if it were the only one present using a double failure protection encoding method. The array further includes a single, global parity storage device holding diagonal parity computed by logically adding together equivalent diagonal parity sets in each of the sub-arrays.

Abstract: Provided is a method of recording data on an optical recording medium having a plurality of addressable unit areas. 62 sync frames, each having a sync code and data, can be recorded in each of the addressable unit areas. Thus, user data can be recorded on a recordable optical disc at a higher density.

Abstract: A code error corrector that enables high speed reproduction of DVD data with a high error correction capability. The data read from the DVD is stored in a DRAM. A PI correction circuit, which performs error correction with an inner parity, and a PO correction circuit, which performs error correction with an outer parity, alternately perform error correction for a predetermined number of times on the data stored in the DRAM. The detection circuit checks whether an error is included in the error corrected data whenever error correction is performed. If an error is not detected, the repeating of the error correction is stopped even if the error correction has not been performed for the predetermined number of times.

Abstract: The present invention is directed to a detector for a high-density magnetic recording channel and other partial response channels. The present invention presents a method for decoding a high rate product code and a decoder which uses this method, comprising receiving a high rate product code; using a row detector to find a most likely codeword and a most likely error sequence for each row; and using a column processor to correct any remaining errors based on column parity bits and the most likely error sequence of each row. In a first aspect of the present invention, the row detector is implemented through a 2-VA detector. In a second aspect of the present invention, the row detector is implemented through a conventional VA detector and a hank of matched filters.

Abstract: A method of generating low density parity check codes for encoding data includes constructing a parity check matrix H from balanced incomplete block design (BIBD) in which a plurality B-sets which define the matrix have no more than one intersection point. The parity bits are then generated as a function of the constructed parity check matrix H.

Abstract: Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages.

Abstract: A method evaluates an error-correcting code for a data block of a finite size. An error-correcting code is defined by a parity check matrix, wherein columns represent variable bits and rows represent parity bits. The parity check matrix is represented as a bipartite graph. A single node in the bipartite graph is iteratively renormalized until the number of nodes in the bipartite graph is less than a predetermine threshold. During the iterative renormalization, a particular variable node is selected as a target node, and a distance between the target node and every other node in the bipartite graph is measured. Then, if there is at least one leaf variable node, renormalize the leaf variable node farthest from the target node, otherwise, renormalize a leaf check node farthest from the target node, and otherwise renormalize a variable node farthest from the target node and having fewest directly connected check nodes.

Abstract: A method evaluates and optimizes an error-correcting code to be transmitted through a noisy channel and to be decoded by an iterative message-passing decoder. The error-correcting code is represented by a parity check matrix which is modeled as a bipartite graph having variable nodes and check nodes. A set of message passing rules is provided for the decoder. The decoder is analyzed to obtain a set of density evolution rules including operators and operands which are then transformed to projective operators and projected operands to generate a set of projective message passing rules. The projective message passing rules are applied iteratively to the error-correcting code modeled by the bipartite graph until a termination condition is reached. Error rates of selected bits of the error-correcting code are then determined by evaluating the corresponding operands. The error rates can be passed to an optimizer to optimize the error-correcting code.

Abstract: A computer-implemented system and method is for generating low-density parity check (LDPC) codes. One aspect of the invention includes a method for generating high rate LDPC codes that first constructs a matrix (H) of size m×n having m rows of check nodes and n columns of bit nodes. The matrix meets the following requirements: the weight of the j−th column equals aj; each row, r, has weight at most br; and the matrix H can be represented by a Tanner graph that has a girth of at least g≧g. The method then iteratively adds an (n+1)th column (U1) to matrix H, wherein the size of U1, is initially empty and is at most an+1, and wherein U1, comprises a set of i check nodes such that i is greater than or equal to 0 and i is less than an+1. The method then iteratively adds check nodes to U1. such that each check node does not violate predetermined girth and check-degree constraints. The matrix H is updated when a new column is added.

Abstract: A data buffer receives and temporarily stores data including a product code enabling error correction in first and second directions. An exclusive-OR operation circuit uses an error amount detected by error correction in the first direction and data stored in a storage element to calculate a first error check result. A PI direction error-checking circuit according to the first error check result performs error check after error correction in the first direction. A PO direction partial error-checking circuit and a PO direction aggregate error-checking circuit use an error amount detected in error correction in the second direction and calculate a second error check result. The first and second error check results are used to generate a final error check result by an exclusive-OR operation circuit.

Abstract: Multi-dimensional packet recovery systems and methods that permit recovery of lost packets and packets containing transmission errors that are transmitted over a network. The packet recovery systems and methods transmit a multi-dimensional array comprising rows, columns and hyperdimensional volumes of data packets between a source node and one or more destination nodes.

Abstract: A data transmission system which allows received data to be decoded and reproduced in real time by simple decoding and which allows signal reproduction and recording by highly reliable error-correcting decoding, wherein a transmitter encodes transmission data by an error-correcting code enabling control of the error-correcting characteristic and the real-time characteristic at the receiving side and transmits it through a transmission line and a receiver 2a demodulates the received data by a demodulation circuit 102, decodes it by a simple decoding circuit 104 and simultaneously stores it in a storage circuit 110, demultiplexes the decoded data 105a by a demultiplexing circuit 106, and reproduces it by a reproduction circuit 123 in a form for viewing and listening by a user.

Abstract: Advantage is taken of the presence of ordinary parity check bits occurring in the data flow in a computer or other information-handling system to improve error correction capability while at the same time providing simpler decoding. More particularly, the encoding and decoding system, methods, and devices herein include the capability of separating error correction in data bits and in parity check bits. In this regard, it is noted that the present invention therefore provides an improved memory system in which the parity check bits do not have to be stripped off prior to storage of data into a memory system with error correction coding redundancy built in. Instead of these parity check bits being stripped off, they are incorporated into a generalized and generalizable error correction system which produces a significantly simple decoding and error correction structure.

Abstract: A serializer and deserializer are disclosed that provide an efficient scheme for both forward error correction and symbol alignment and frame alignment by the deserializer. In particular, the illustrative embodiment provides an efficient method for generating row and column parity bits for an S by K-bit matrix that can, in some cases, require fewer that S+K parity bits. This is particularly useful for when a single word is broken up and its pieces are sent via different serial communications channels and the deserializer needs to be capable of properly reassembling the fragments into the word.

Abstract: A product code and interleaving/de-interleaving process are designed to work in combination to improve the coding gain of the product code. Such improvement of coding gain is based on an error constraint. The error constraint is a maximum number of values in error per block in the detected decisions for received output channel samples. The error constraint may be a burst error constraint, such as a maximum number of errors in a block introduced by burst noise in the communication channel; or the error constraint may be an error event constraint, such as the error event generated by an incorrect decision for a path through the trellis of the Viterbi algorithm employed by the detector or a combination of both. In one implementation, a block of data of length N is encoded with a product code of two dimensions with N a positive integer. The product code includes an error correcting capability of detection and correction by a receiver of single one-bit errors in the encoded block.

Abstract: An apparatus and method for reconstructing missing data using cross-parity stripes on a storage medium is provided. The apparatus and method may operate on data symbols having sizes greater than a data bit. The apparatus and method makes use of a plurality of parity stripes for reconstructing missing data stripes. The parity symbol values in the parity stripes are used as a basis for determining the value of the missing data symbol in a data stripe. A correction matrix is shifted along the data stripes, correcting missing data symbols as it is shifted. The correction is performed from the outside data stripes towards the inner data stripes to thereby use previously reconstructed data symbols to reconstruct other missing data symbols.

Abstract: An error correction code (ECC) block for a data storage disk, includes an array of data that is 88 rows by 172 columns. Each row includes ten bytes of inner parity code and each column includes sixteen bytes of outer parity making the array 104 rows by 182 columns. The ECC block is divided into eight sectors, each sector having eleven rows of data and two associated rows of outer parity, for a total of thirteen rows per sector. The ECC block in accordance with the present invention is half the size of a conventional ECC block but has a higher ratio of parity bytes to data. Consequently, the ECC block of the present invention is particularly advantageous with small form factor disks and first-surface media, i.e., disks with the recording layer on the exterior of the disk or under a very thin transparent layer.

Abstract: A method evaluates an error-correcting code for a data block of a finite size. An error-correcting code is defined by a parity check matrix, wherein columns represent variable bits and rows represent parity bits. The parity check matrix is represented as a bipartite graph. A single node in the bipartite graph is iteratively renormalized until the number of nodes in the bipartite graph is less than a predetermine threshold. During the iterative renormalization, a particular variable node is selected as a target node, and a distance between the target node and every other node in the bipartite graph is measured. Then, if there is at least one leaf variable node, renormalize the leaf variable node farthest from the target node, otherwise, renormalize a leaf check node farthest from the target node, and otherwise renormalize a variable node farthest from the target node and having fewest directly connected check nodes.

Abstract: A computer-implemented system and method is for generating low-density parity check (LDPC) codes. One aspect of the invention includes a method for generating high rate LDPC codes that first constructs a matrix (H) of size m×n having m rows of check nodes and n columns of bit nodes. The matrix meets the following requirements: the weight of the j−th column equals aj; each row, r, has weight at most br; and the matrix H can be represented by a Tanner graph that has a girth of at least g≧g. The method then iteratively adds an (n+1)th column (U1) to matrix H, wherein the size of U1, is initially empty and is at most an+1, and wherein U1, comprises a set of i check nodes such that i is greater than or equal to 0 and i is less than an+1. The method then iteratively adds check nodes to U1. such that each check node does not violate predetermined girth and check-degree constraints. The matrix H is updated when a new column is added.

Abstract: A method is described of detecting two-dimensional codes, in particular matrix codes, which include a plurality light and dark data bits arranged two dimensionally, in particular in matrix form. In the method, the code is detected as a gray scale value image; the detected gray scale value image is split into image areas corresponding to the individual data bits and a binarizing threshold representing a specific gray scale value is determined for the image areas. A respective binarizing of the gray scale value of the individual image areas is carried out by means of the binarizing threshold to produce a bit sequence which represents the data bits and consists of the values 0 and 1. The bit sequence is subsequently supplied to an error correction algorithm to recognize and/or correct bit errors within the bit sequence. In accordance with the invention, those so-called uncertain image areas are determined whose gray scale values each lie close to the binarizing threshold.

Abstract: Multi-dimensional packet recovery systems and methods that permit recovery of lost packets and packets containing transmission errors that are transmitted over a network. The packet recovery systems and methods transmit a multi-dimensional array comprising rows, columns and hyperdimensional volumes of data packets between a source node and one or more destination nodes. Parity packets are derived from source packets, on a linear array of data packets, where a span of data packets is defined as a packet block. Respective bits of the data packets of the packet block are modulo-2 added to produce a respective plurality of parity bits. Rows of packets are assembled to form a rectangular array of packets. Parity packets are computed on columns of packets where each column is treated as a span of packets. The process may be expanded to produce three dimensional and higher dimensional packet arrays. The multi-dimensional block is transmitted over a network.

Abstract: A method of checking for errors in a set associative cache array, by comparing a requested value to values loaded in the cache blocks and determining, concurrently with this comparison, whether the cache blocks collectively contain at least one error (such as a soft error caused by stray radiation). Separate parity checks are performed on each cache block and if a parity error occurs, an error correction code (ECC) is executed for the entire congruence class, i.e., only one set of ECC bits are used for the combined cache blocks forming the congruence class. The cache operation is retried after ECC execution. The present invention can be applied to a cache directory containing address tags, or to a cache entry array containing the actual instruction and data values. This novel method allows the ECC to perform double-bit error as well, but a smaller number of error checking bits is required as compared with the prior art, due to the provision of a single ECC field for the entire congruence class.

Abstract: An optical information recording medium, a data recording apparatus, a data recording method used by the recording apparatus, and a data reproducing apparatus are provided. The optical information recording medium contains data included in one or more recording blocks. Identifiers included in a plurality of sectors comprising a plurality of error correction code (ECC) blocks are sequentially extracted so that the ECC blocks are equally selected, and are alternately arranged at predetermined intervals. As a result, the optical information recording medium, the data recording apparatus, and the data recording method used by the apparatus, which have higher error correction rates, are provided.

Abstract: A method of soft input to soft output decoding of a word s of a block linear code of dimension k and length n received from a transmission channel is provided, including generating a list of firm words (ub) of the code close to the received code word (s) by coding a list of k-tuplets obtained by firmly approximating components of the received word and changing the least likely components, and calculating the jth component of the output soft word as the difference between the metrics of the closest generated code word and the closest generated code word having an opposite jth component, or, failing this, the farthest generated code word. Also provided is a method of iterative decoding of a product code word received on a transmission channel using the soft input to soft output decoding method. It rapidly and efficiently decodes product code words without an algebraic decoder.

Abstract: A method of verifying the integrity of a file transferred as a plurality of sectors. During a first pass transfer of a sectored file, first pass sector CRC codes are generated for each sector and stored in system memory. During a second pass transfer, second pass CRC codes are generated for each sector. The second pass CRC codes are compared to the first pass CRC codes for corresponding sectors. If the second pass CRC code matches the first pass CRC code, the sector is committed to the destination medium. The CRC sector values for an initial sector of the file are preferably generated from a predefined seed. Each successive CRC sector value is then preferably generated from the preceding sector's CRC code such that the sector CRC code of the last sector comprises a final CRC code of the file.

Abstract: Erroneous column(s) in the matrix of data obtained from a transmission channel are first determined on the basis of column parity violation. An error instance in the matrix is next ascertained by matching the erroneous column(s) with an error event characteristic of the transmission channel. A candidate error row is then located in the matrix with respect to the error instance. Lastly, positions in the matrix specified by an intersection of the candidate error row and the erroneous column(s) of the error instance are corrected. Data reliability values assigned to positions of the matrix are used to determine the candidate error row. In particular, with respect to the erroneous column(s) of the error instance, and for each of plural rows of the matrix, factors (e.g., squares) of the reliability values assigned to positions of the matrix are summed to determine a least reliable row as the candidate error row.

Abstract: A ROM including an array, each cell of which is accessible by means of a column address and of a row address, includes a parity memory for storing the expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating the parity of each row and of each column, comparing the calculated and expected parities for each row and each column, and in case they are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting the value read from the array cell, having its row and column marked in the address memory.

Abstract: A data allocator allocates (N×kV×kH)-byte source data distributively in N (kV bytes×kH bytes) tow-dimensional arrays and sends the data to a V coder and an H coder. The V coder codes each column of the tow-dimensional arrays according to an (nV, kV) code V, and the H coder codes each row of the two-dimensional arrays according to an (nH, kH) code H. The V and H coders send redundant data to a data allocator.

Abstract: System and method for improved formation of a Q-parity checkbyte matrix used for error control for a sequence of message bytes and error control bytes, using an algorithm, rather than a lookup table, to determine the order of the words used for the sequence. Entries of a Reed-Solomon parity check rectangular array are set up sequentially and diagonally, including the syndrome bytes and checkbytes to be used for error detection, so that all matrix entries can be written to, or read from, a computer memory in a stream of bytes whose order is determined by the algorithm without reference to a lookup table.

Abstract: A data transmission system for transmitting information data with a parity of an error correcting code for correcting an error in the information data. A read-out controller controls a transmitter to transmit information data and a parity so that each data component of the information data obtained by dividing the information data of one data block area into a plurality of data components and each parity component of the parity obtained by dividing the parity of one block area into a plurality of parity components are transmitted at intervals along each sector having a sector address. The sector is defined as an data area obtained by dividing one data block area of a predetermined data amount into a plurality of sectors each having an identical data amount.