Abstract: A method for processing data packets of a data stream, in which the received data packets are processed in real-time by a first unit and only data packets that are received error-free are processed by a second unit, include a data sink initially receiving only the data packets processed by a first unit. Once a second unit and the first unit are processing identical data packets nearly simultaneously, data packets processed by the second unit can be routed to the data sink. Embodiments of the invention can be used advantageously in video coding, for example with a video-on-demand service or image analysis within the framework of a surveillance system.

Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.

Abstract: A transmission apparatus includes a mapping unit configured to map a first information associated with detecting an error of a frame into a payload area of the frame; and a transmission unit configured to transmit the frame including the first information and a second information associated with detecting an error of the frame.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for enhancing error protection for wireless transmissions.

Abstract: A terminal apparatus and a response signal transmitting method wherein the system transmission efficiency can be improved by devising a bundling rule. In a terminal (200), a PDSCH receiving unit (208) receives first and second code words, which comprise code word block (CWB) groups to be mapped to the respective ones of a plurality of downstream unit bands, and detects errors of the CWBs; and an A/N bundling unit (216) transmits, based on a bundling rule in which each CWB is associated with any one of first and second bundling groups, a single bundle of response signals into which the error detection results are bundled for each bundling group. According to the bundling rule, at least one of the first and second bundling groups includes both the CWB belonging to the first code words and the CWB belonging to the second code words.

Abstract: Methods, apparatus, and fabrication processes relating to implementing cyclic redundancy checks (CRCs) in processors, such as CRC32 instructions in x86 computer architectures. A method may comprise extracting a first CRC value from a data packet, performing a carryless operation upon the data packet to determine a second CRC value, and determining that a data error is present in the data packet when the first and second CRC values do not match.

Abstract: A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less.

Abstract: A system comprising a plurality of storage systems, which uses storage devices of multiple levels of reliability. The reliability as a whole system is increased by keeping the error code for the relatively low reliability storage disks in the relatively high reliability storage system. The error code is calculated using hash functions and the value is used to compare with the hash value of the data read from the relatively low reliability storage disks.

Abstract: The invention relates to measured value transmitting devices for serially transmitting data in accordance with the SSI method, Synchronous Serial Interface. At least one slave is provided which provides the data bits of a measured value detected by at least one sensor for the purpose of a serial bit-by-bit transmission to a master. The master requests a measured value from the slave by means of a clock burst that has multiple clock cycles, the number of which matches the number of the data bits to be transmitted. A first measured value transmitting device according to the invention is characterized in that the clock cycles of the clock burst have a specified duty cycle which corresponds to the ratio of the pulse duration to the period duration of one clock cycle, and the master contains a comparator. The master reads the clock bursts outputted on the at least one clock line and checks the duty cycle in the comparator to determine whether an upper threshold and/or a lower threshold has been exceeded.

Abstract: An updating system for updating an electronic device, comprises a storage unit, an obtaining unit for obtaining an update data from a storage medium and a first check value corresponding to the update data, and storing the updating data to the storage unit, wherein the first check value is calculated according to the update data. A calculating unit for calculating a second check value according to the updating data stored in the storage unit. A determining unit for determining whether the second check value matches the first check value, and an updating unit for updating the electronic device according to the obtained update data when the second check value matches the first value. Thus, the updating system can avoid an error occurs during the updating process. An updating method applied in the updating system is also provided.

Abstract: Processing a received signal includes receiving a code word that is different from an expected code word, determining, at least in part using a logic circuit, whether the difference between the received code word and the expected code word is acceptable based at least in part on one or more bit differences, and in the event it is determined that the difference is unacceptable, providing an indication of an error.

Abstract: A system is provided for generating data packets of a message according to a first protocol, then analyzing the message according to a second protocol. The system determines if the message provides a correct checksum according to the second protocol. If the message provides the correct checksum according to the second protocol, the system alters the message and transmits the message according to the first protocol.

Abstract: A data validation method comprises associating a validation chunk with one or more data chunks stored on one or more storage mediums. The validation chunk comprises validation information for verifying whether data recorded in a subdivision of the one or more data chunks is lost. A request is received for an operation to be performed on first data stored in a first subdivision of a first data chunk from among said one or more data chunks. One or more portions of the validation information are examined to determine whether the data recorded in said first subdivision is deemed to be lost.

Abstract: This invention relates to a method for allocating resources in a wireless communication system and a system thereof The disclosed method comprises steps for: allowing a user's terminal to receive information about the wireless transmission resources among semi-permanent transmission resources; performing CRC-calculation by receiving a message about the allocation of the semi-permanent transmission resources based on the received information; verifying the validity of the message by comparing the information about the wireless resources indicated in the received message with the received information about the wireless transmission resources; and receiving data as the transmission resources indicated in the message if there is no error in the verification.

Abstract: In accordance with the teachings described herein, systems and methods are provided for calculating a Cyclic Redundancy Check (CRC) code for a message. A system includes a first CRC calculator and a second CRC calculator. The first CRC calculator is configured to receive a first data block of the message, and to calculate a first CRC value based at least in part on the first data block, the message including the first data block and a second data block. The second CRC calculator is configured to receive the first CRC value and the second data block of the message, and to calculate a second CRC value based on the first CRC value and the second data block, the second CRC calculator being different from the first CRC calculator.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: A method and device for determining a size of a transport block based on modulation and coding related information, and resource information.

Abstract: A method for detecting control information in a wireless communication system is provided. The method includes checking a cyclic redundancy check (CRC) error by monitoring control channels, determining whether a value of an error check field is equal to a specific value, and, if the value of the error check field is equal to the specific value, detecting the control information on the control channel.

Abstract: Disclosed are a wireless communication base station device, a wireless communication terminal device, and a wireless communication method with which the amount of signaling is reduced while maintaining a high scheduling gain. A judgment unit (117) stores in advance a correspondence between the number of code words and the number of clusters to reduce the maximum value for the number of clusters allocated to each terminal as the number of code words increases, and thus determines the maximum value for the number of clusters based on the number of code words acquired.

Abstract: A method and system are provided for efficiently verifying the integrity of file-based video audio and other essence in a content production system. The method involves creating a sequence of hash codes for the editable units of the essence, which are stored as metadata apart from the content (either in a separate file or in a separate portion of the same file), and are correlated to the content by a time label (which may be an offset or a timecode number). Upon retrieval from storage, the hash codes are generated for the retrieved essence and compared to the stored hash codes to verify that the content has not been modified.

Abstract: An apparatus includes, in at least one aspect, a plurality of buffers and circuitry configured to store encoded data in one buffer of the plurality of buffers concurrently with storing other data in another buffer of the plurality of buffers and to write the stored encoded data from the one buffer to a storage device concurrently with storing encoded other data in the other buffer, replacing the stored other data in the other buffer.

Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to techniques for accurately determining a number of data symbols in a data packet. The techniques provided herein may allow a receiving terminal to correct number of symbol calculations based on such ambiguous length field values.

Abstract: A data receiving apparatus includes: a header analyzing unit that analyzes a header of a frame and outputs header information; a checksum judging unit that calculates and judges a checksum of the frame; a buffer unit that stores a data portion of the frame; a reading unit that reads connection information corresponding to the header information from a second storage unit; an identifying unit that identifies a write location for the data portion based on the connection information; a data writing unit that reads data from the buffer unit and starts writing the data to the identified write location in a first storage unit before the checksum is judged; and a writing unit that, if the judgment result is “pass,” writes the connection information updated based on the header information to the second storage unit while the data writing unit is writing.

Abstract: An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p?1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

Abstract: A method of programming a tire pressure monitor sensor utilizes a programming tool that transmits LF data frames to the TPMS sensor that includes a cyclic redundancy check (CRC) code with each data frame. The starting point for the subsequent data frame will then start with the CRC code received from the previous frame and will end with a new CRC code. Accordingly, the CRC code received from the previous frame will be used to ensure that the next data frame matches that CRC code as the starting point for that frame. This will ensure that the data frames cannot get out of sequence and will allow the ability to quickly identify where the data frames have gone out of sync and allow the programming tool to quickly react.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: An embodiment of the invention relates to a contactless switching system and an embodiment relates to a method for encoding same with at least one sensor and at least one signal generator, where the signal generator sends at least one data sequence and the sensor receives the data sequence. In at least one embodiment, an aim is to specify a technical teaching for encoding a contactless switching system inexpensively and in a versatile fashion. To this end, at least one embodiment of the invention proposes anchoring user-implementable encoding in the checksum of the data sequence or the checksum computation code, so that the checksum which the data sequence contains is used to check the quality of the data transmission and at the same time to implement the encoding.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination.

Abstract: An automotive sensor reads from memory previously stored back-calculated diagnostic-code values for which a fixed cyclic-redundancy-check (“CRC”) value is valid and transmits the previously stored back-calculated diagnostic-code values read from memory each paired together with the fixed CRC value.

Abstract: A method and an apparatus for speech signal processing are provided. The method includes: receiving an encoded speech signal sent by a user equipment, where the encoded speech signal includes a first substream, a second substream, and a third substream, and the first substream is attached with a cyclic redundancy check (CRC); performing decoding processing on the first substream, the second substream, and the third substream by adopting a decoding algorithm, where a decoding algorithm that is based on an auxiliary decision of the CRC is adopted to perform decoding processing on the first substream; and sending decoding results of the first substream, the second substream, and the third substream to a base station controller, where the decoding result of the first substream includes a decoded bit stream and a CRC result. Decoding performance of the first substream is improved, and users' higher requirements for the speech quality are met.

Abstract: A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive unit (WTRU) identity (ID) and a generator matrix with a maximum minimum Hamming distance. For part 2 data encoding, cyclic redundancy check (CRC) bits are generated based on part 1 data and part 2 data. The number of CRC bits is less than the WTRU ID. The CRC bits and/or the part 2 data are masked with a mask. The mask may be a WTRU ID or a punctured WTRU ID of length equal to the CRC bits. The mask may be generated using the WTRU ID and a generator matrix with a maximum minimum Hamming distance. The masking may be performed after encoding or rate matching.

Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates.

Abstract: A device and method for attaching a CRC code to a transport block and turbo encoding the CRC attached transport block, where the transport block has a predetermined size.

Abstract: The present disclosure provides an apparatus and a method for checking decoded data, an apparatus and a method for decoding, and a receiving terminal. The apparatus for checking decoded data includes: an arithmetic unit to perform a check computation on decoded bits output from decoders in every clock cycle to obtain a computation result, where the check computation is performed by: denoting each decoded bit as a polynomial, computing the sum of the polynomials and performing polynomial modular arithmetic on the sum; and an output unit configured to output a check result, where the check result is the sum of the computation results in all the clock cycles during a decoding process. A real-time check computation of decoded data may be realized, so that power consumption may be saved.

Abstract: Methods and systems for improving the quality of transmitted data are described. Multiple distinct communication channels are used to transmit segments representing the same pre-transmission block of a data packet. Upon receipt of these segments, a system identifies differences between the segments for those segments that meet a quality threshold. The system selects one of segments for subsequent transmission or re-assembly into a data packet based on the prior performance of the communication channels used to transmit the segments.

Abstract: The present invention discloses a method for fast cyclic redundancy check (CRC) encoding, and includes: mapping a CRC encoding generator polynomial to generate an (r+1)-order transfer matrix J; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix; forming a r×1 column matrix by first columns of 2nd to r+1th rows of said (r+1)-order transfer matrix; obtaining a zero input transfer matrix and a zero state transfer matrix of CRC encoding by the r-order transfer matrix and the r×1 column matrix; adding dummy bits before an input bit stream; and obtaining a CRC encoding check sequence according to the zero input transfer matrix, the zero state transfer matrix and the input bit stream after adding the dummy bits. The present invention further discloses an apparatus for fast cyclic redundancy check encoding.

Abstract: The present disclosure describes methods and apparatuses for improved transport block decoding in devices capable of wireless communication, which may include user equipment and network entities. For example, the present disclosure presents methods and apparatuses for decoding a code block from a plurality of code blocks corresponding to a transport block, obtaining a reliability indicator that identifies a reliability of the decoding of the code block, comparing the reliability indicator to a reliability threshold, and determining whether to decode a subsequent code block from the plurality of code blocks based on the comparing. Furthermore, these methods and apparatuses may include determining not to decode at least one subsequent code block of the transport block where the comparing indicates that the reliability indicator is less than the reliability threshold. As such, device power is not unnecessarily consumed by decoding likely superfluous code blocks.

Abstract: A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.

Abstract: An apparatus and method for fault tolerant Firmware-Over-The-Air (FOTA) update are provided. The method includes computing a checksum for each sector of a partially updated firmware, for each sector of the partially updated firmware, determining a last instruction in an update package that was applied to that sector, based on checksums included in the update package and the computed checksums of the sectors of the partially updated firmware, determining a last instruction of the update package that was applied to the partially updated firmware prior to the interruption based on the last instruction applied to each sector, and resuming the update procedure starting from an instruction immediately following the last applied instruction.

Abstract: A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with a different codeword in a different group.

Abstract: An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: The present disclosure includes methods, devices and systems for establishing a connection between a medical device and a remote computing device, receiving an upgrade command at the medical device, storing a current version of persistent data and a current version of executable code in a first storage area of the medical device, transmitting at least the current version of the persistent data to the remote computing device, receiving a second format of the current version of the persistent data and an upgraded version of executable code at the medical device, storing the second format of the current version of the persistent data and the upgraded version of the executable code in a second storage area of the medical device, and executing the upgraded version of the executable code with the second format of the current version of the persistent data.

Abstract: Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

Abstract: Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

Abstract: Methods and apparatus for compressing data for network transport in support of continuous availability of applications are described. One computer-implemented method of compressing data includes receiving a current instance of data in an input buffer. A candidate chunk of data is selected from the input buffer. A signature hash is computed from a signature length range of data within the candidate chunk. A matching dictionary entry having a matching signature hash from a multi-tiered dictionary is identified. The matching dictionary entry prospectively identifies a location of a prior occurrence of a selected range of consecutive symbols including the signature length range of data within at least one of the current instance of data and a prior instance of data in the input buffer. A dedupe processed representation of the instance of data is formed wherein a dedupe item is substituted for the selected range of consecutive symbols if the selected range is verified as recurring.

Abstract: The subject matter disclosed herein provides an outer coding framework for minimizing the error rate of packets. In one aspect, the method may include determining, based on a cyclic redundancy check, a first erasure table including zero or more erasures; determining a second erasure table; using the first erasure table to locate errors in a frame of packets, when the zero or more erasures of the first erasure table do not exceed a threshold of erasures; and using the second erasure table to locate errors in the frame of packets, when the one or more erasures of the first erasure table do exceed the threshold of erasures. The frame may include the one or more rows encoded using the outer code. The block that is read may be provided to enable an inner code to encode the block before transmission. Related systems, apparatus, methods, and/or articles are also described.

Abstract: A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: A transmitter generates an encrypted data by processing a specific data according to a specific transmission mode, generates a verification code according to the specific transmission mode, and provides a protocol data unit according to the encrypted data and the verification code. After transmission, a receiver decodes the protocol data unit and determines whether the decrypted data of the protocol data unit matches the verification code, thereby providing error detection for wireless transmission.