Abstract: A data processing method for a non-volatile memory device is provided. The non-volatile memory device includes a controller and a NAND flash memory. First, a target command and a corresponding target address are serially transmitted from the controller to the NAND flash memory. Then, the NAND flash memory calculates a first value according to the target address. Moreover, a cyclic redundancy check code corresponding to the target address is transmitted from the controller transmits to the NAND flash memory. Next, the NAND flash memory determines whether a transmission error has occurred by performing a cyclic redundancy check according to the first value and the cyclic redundancy check code. When the transmission error has occurred, a status register is set to inform the controller to re-transmit the target command and the corresponding target address.

Abstract: A memory device and a method of controlling the memory device are provided, comprising: generating commands at a memory controller; counting a number of commands in response to a clock signal; storing the commands and the count numbers corresponding to the commands; transmitting to a memory device the commands, the count number of the commands, and data; receiving at the memory device the commands, the count number of the commands, and data sent from the memory controller; counting at the memory device the number of commands received in response to the clock signal; storing at the memory device the count number of commands received; and transmitting the count number of the commands received to the memory controller, wherein said transmitting the count number of the command to the memory controller is performed upon indication of an error condition.

Abstract: A semiconductor test apparatus sorts addresses corresponding to memory cells in memory provided in a device under test, as well as failure data obtained as a result of testing the memory cells, and stores the sorted addresses and failure data in acquisition memory using burst access. The semiconductor test apparatus is provided with: an address generator configured to generate a burst target signal, which indicates that the addresses and failure data are target data for burst access; and a sort circuit configured to sort the addresses and failure data in order of continuous addresses suitable for burst access, on the basis of the burst target signal.

Abstract: During initial access in which a control unit 8 accesses a disk device 3 for a first time following execution of a command, the control unit 8 waits for an access response from the disk device 3 until a first timeout value, which is set at a time for completing access to the disk device 3, is counted, and during an access retry subsequent to the initial access, the control unit 8 waits for an access response from the disk device 3 until a second timeout value, which is larger than the first timeout value and set at a time required to specify a source of an access error, is counted.

Abstract: In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.

Abstract: In a controller of a disk array device, when recovery from a power failure is detected, the controller instructs a reading section to transfer data in a burst mode using a large prefetch amount. When an error is detected, the controller causes the data to be transferred again for an area where the error is detected. Further, the controller designates different access ports for the reading section and an erasing section, and causes these sections to operate in parallel. The reading section reads cache data from a flash memory and stores the cache data in a cache memory. The erasing section uses the access port different from the access port of the reading section, to erase data that is stored in the flash memory and has been transferred by the reading section.

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

Abstract: Provided are a method, system, and article of manufacture for providing removable storage management services using removable storage error information. Read/write error information is obtained for at least one removable storage by interfacing with the removable storage manager. The obtained read/write error information for the at least one removable storage is processed to determine read/write error rates for the at least one removable storage. A determination is made as to whether the determined read/write error rates for the at least one removable storage exceed at least one read/write error threshold. At least one message is sent to the removable storage manager to replace the at least one removable storage having read/write error rates that exceed the at least one read/write error threshold.

Abstract: An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Abstract: A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given.

Abstract: A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.

Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.

Abstract: A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.

Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.

Abstract: A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.

Abstract: According to the embodiments, a cache system includes a cache-data storing unit and a failure detecting unit. The failure detecting unit detects failure in units of cache line by determining whether instruction data prefetched from a lower layer memory matches cache data read out from the cache-data storing unit. A cache line in which failure is detected is invalidated.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.

Abstract: The memory controller writes and reads data in and from a nonvolatile memory. The nonvolatile memory has a plurality of memory cell blocks, each memory cell block includes a plurality of multi-level cells each capable of storing m-bit data (m is a natural number of two or more), a first page to a m-th page are allocated to the respective m bits of the multi-level cell, the memory controller sequentially writes the data to the memory cells from the first page in ascending order, and comprises a backup unit, and when a write command is received from the outside of the memory controller, in a case where a data write destination of the data in the nonvolatile memory is a n-th (n is a natural number of two to m) page of the multi-level cell, and data is already written in the first to (n-1)th pages, the backup unit copies the already written data to a nonvolatile storable backup region.

Abstract: Unrecoverable electronic correction code (ECC) errors in memory storage devices are usually preceded by recoverable ECC errors. A memory storage device controller is provided notice of the recoverable errors and associated information. The memory storage device controller can cause the data having the recoverable information to be rewritten on the memory storage device. Rewriting the data on the memory storage device (often in a different location) normally reduces the probability of encountering data with unrecoverable data errors.

Abstract: When a failure occurs in an LPAR on a physical computer under an SAN environment, a destination LPAR is set in another physical computer to enable migrating of the LPAR and setting change of a security function on the RAID apparatus side is not necessary. When a failure occurs in an LPAR generated on a physical computer under an SAN environment, configuration information including a unique ID (WWN) of the LPAR where the failure occurs is read, a destination LPAR is generated on another physical computer, and the read configuration information of the LPAR is set to the destination LPAR, thereby enabling migrating of the LPAR when the failure occurs, under the control of a management server.

Abstract: In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package.

Abstract: The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.

Abstract: A memory system that can efficiently relieve a large number of defective bits with a small number of redundant bits is provided in a Flash-EEPROM nonvolatile memory. A memory system according to an embodiment of the present invention comprises a Flash-EEPROM memory in which a plurality of memory 5 having a floating gate or a charge trapping layer and capable of electrically erasing and writing data are arranged; a control circuit that controls a cache memory and the Flash-EEPROM memory; and an interface circuit that communicates with outside, wherein a plurality of group data and a plurality of flag data for storing presence of inversion of all bits of respective group data are stored in a memory area of the Flash-EEPROM memory.

Abstract: An embodiment discloses a flash memory controller comprising a flash memory interface controller, a host interface controller, a random-access memory (RAM) interface controller, an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The flash memory interface controller is configured to store information data, ECC segments, and linked-lists to a flash memory and read information data, ECC segments, and the linked-lists from the flash memory. The host interface controller is configured to forward information data to a host and to receive information data from the host. The RAM interface controller is configured to store the linked-lists to a RAM device and read the linked-lists from the RAM device. The ECC encoder is configured to receive a write information datum from the host interface controller and generate an ECC datum, of which the length is variable, in response to the write information datum to be stored in the flash memory when operated in a write mode.

Abstract: A method of storing write data in flash memory incorporated in a storage device, the method includes; receiving write data and a logical block address (LBA) for the flash memory, determining whether the LBA exists in the cache memory, if the LBA exists in the cache memory, comparing the write data with cache data stored in the cache memory at a location associated with the LBA, and if the write data and the cache data are the same, terminating operation of the storage device without programming the write data to the flash memory, else updating an error detection information lookup table entry associated with the LBA and programming the write data to the flash memory, and if the LBA does not exist in the cache memory, updating the error detection information lookup table entry associated with the LBA and programming the write data to the flash memory.

Abstract: A method and apparatus to read information from an information storage medium using a read channel, where that read channel includes a data cache. The invention generates an analog waveform comprising the information, and provides that analog waveform to a read channel, and generates a digital signal from that analog waveform using one or more first operating parameters. The method error corrects that digital signal at an actual error correction rate, and determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, and provides those one or more second operating parameters to the read channel.

Abstract: Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

Abstract: According to one embodiment, a memory device includes: a driving module configured to store therein data on a sector-by-sector basis; a first verifying module configured to verify, during a reading operation, sector data from the driving module; a partitioning module configured to partition the sector data into sets of subsector data, a size of each set of subsector data being smaller than a size of the sector data; an appending module configured to append an error detecting code to each set of subsector data; a second verifying module configured to store, in a predetermined memory, the sets of subsector data retrieved from a buffer, and to verify the sets of subsector data using respective error detecting codes; and a sending module configured to send, from the memory, the verified sets of subsector data to the host with a transfer size.

Abstract: Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.

Abstract: Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.

Abstract: A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item.

Abstract: A system and method are herein disclosed for managing memory defects in an information handling system. More particularly, a system and method are described for generating a usable memory map which excludes memory locations containing defect memory elements. In an information handling system, a memory defect map, which contains information about the location of defective memory elements, is coupled to the memory device. As a map of memory usable by the system is created, usable memory regions containing defective memory elements are excluded from the memory map. The memory map is passed to the operating system, which uses only those regions of memory designated as usable and non-defective.

Abstract: A flash memory controller having a flash memory testing functions is provided, in which the flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit and a memory cell testing unit. The flash memory interface unit is configured for connecting a plurality of flash memory chips, where each flash memory chip has a plurality of flash memory dies and each flash memory die has a plurality of physical blocks. The host interface unit is configured for connecting a host system. The memory cell testing unit is configured for determining whether the physical blocks can be normally written, read and erased. Accordingly, the flash memory controller can perform a flash memory testing under a command of the host system and all the physical blocks of the flash memory chip can be tested during the flash memory testing.

Abstract: A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a separate integrated circuit to provide access signals, including read and write signals suitable for binary or multi-level accesses.

Abstract: A solid state disk device comprises a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are electrically connected to a plurality of channels, respectively. The controller controls storing, erasing and reading operations of the nonvolatile memories. The controller divides input data into a number of units corresponding to a number of the plurality of channels and stores the divided input data in the nonvolatile memories through the plurality of channels.

Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology).

Abstract: A device includes: non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to move data from a volatile memory to the non-volatile memory upon a loss of power of a primary power source of the volatile memory; and a backup power supply providing temporary power to the controller and the volatile memory upon the loss of power of the primary power source, including: a capacitor bank with an output terminal; a connection to a voltage source that charges the capacitor bank to a normal operating voltage; and a state-of-health monitor that is programmed to generate a failure signal based on a voltage at the output terminal of the capacitor bank.

Abstract: A storage system includes a storage device for storing data, a pair of adapters connected with the storage device, each of the adapters transmitting and receiving the data to and from the storage device respectively. The storage system includes a controller, connected with the adapters, for collecting performance information indicating performance of each of the adapters, comparing the collected performance information of the adapters with each other, and detecting a suspected adapter that is suspected of having a performance failure on the basis of a result of the comparison.

Abstract: A method for data storage includes performing an erasure operation on a group of analog memory cells (32). One or more of the memory cells in the group, which failed the erasure operation, are identified as erase-failed cells. A storage configuration that is used for programming the analog memory cells in the group is modified responsively to the identified erase-failed cells. Data is stored in the group of the analog memory cells using the modified storage configuration.

Abstract: A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unit and to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator.

Abstract: Provided is a backup line allocation apparatus that determines which fail lines, in a memory provided with a plurality of backup lines, to allocate the backup up lines to, comprising a bit counting section that, for each fail bit contained in each fail line, counts a number of orthogonal fail bits, which is a number of fail bits in a fail line that includes the each fail bit and has an orientation that differs from the orientation of the each fail line, and stores the number of orthogonal fail bits associated with the each fail bit; a weight calculating section that calculates a weighting coefficient for each fail line based on the number of orthogonal fail bits of the fail bits contained in the each fail line, and stores the weighting of the each fail line; and an allocating section that determines which of the fail lines to allocate the backup lines to, based on the relative sizes of the weighting coefficients calculated by the weight calculating section.

Abstract: The count data recording device includes: a storage unit that includes N memory areas storing the count data pieces; a data writing unit that writes a count data piece to the storage unit; a data reading unit that reads the count data piece from the storage unit; and a data restoring unit that detects a corruption in the count data pieces stored in the storage unit and restores the corruption, wherein the data writing unit records the count data piece using the memory area included in the range of the minor loop according to the predetermined order and shifts the range of the minor loop backward after recording the count data piece using a last memory area within the minor loop, and wherein the data restoring unit: derives a sorted count data sequence so that values of the count data pieces vary monotonously; derives a count data difference value sequence; and detects and restores the corruption in the count data pieces based on the sorted count data sequence and the count data difference value sequence.

Abstract: A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register to hold an index address that indicates a faulty cache line and a part in which the fault has occurred in the faulty cache line; an alternation way register to hold information of a way including the part having a fault; an address match circuit comparing, when an access is performed to the data holding unit, an index address and the index address held by the alternation address register; and a way match circuit comparing, when an access is performed to the data holding unit, way information used for the access and way information held by the alternation way register.

Abstract: A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.

Abstract: A data transfer method includes reading data from a NAND flash memory in pages into a first buffer, transferring a parity in the data read into the first buffer to a second buffer, after transferring the parity to the second buffer, transferring a main data in the data read into the first buffer to the second buffer, on the basis of the parity, correcting an error in the main data transferred to the second buffer, and transferring an error-corrected main data to a third buffer.

Abstract: A data processing apparatus includes a memory which receives and outputs data with a predetermined data width, an operation circuit which outputs a read command or a write command to access the memory, and an access control circuit which replaces a part of first read data read from the memory with a partial data, and outputs partially replaced data as write data to the memory when receiving the write command and the partial data with a data width smaller than the predetermined data width associated with the write command, from the operation circuit. The access control circuit replaces a part of second read data which has been acquired in response to the read command outputted before, instead of the first read data, with the partial data, and outputs replaced partially data as the write data if the write command has been outputted in connection with a read command outputted before the write command.

Abstract: Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.

Abstract: According to one embodiment, an information processing apparatus includes a main body and a memory drive which is accommodated in the main body. The main body includes a main control module which receives information including errors and error correction codes for correcting the errors from the memory drive, corrects the errors by using the error correction codes, and returns corrected information to the memory drive. The memory drive includes a memory control module which controls execution of first error correction processing which corrects errors for each sector and second error correction processing which corrects errors for each cluster, transmits information including the errors and error correction codes for correcting the errors to the main body when errors which cannot be corrected by the first and the second error correction processing have occurred, and updates the information including the errors in the corrected information returned from the main body.

Abstract: A method of performing recovery in conjunction with programming an array of NVM cells. First, erasing the array cells and loading an SRAM with user data. When programming the cells, flip bits in the SRAM which are successfully programmed (pass PV). If programming is not successful, read the failed data from the array, and if the SRAM bits were not successfully programmed, do not change them. Write the other bits (not programmed or successfully programmed) from the array to the SRAM. Before reading the failed data, the SRAM may be copied to a second SRAM. If the restore did not work, an ED mechanism may be applied, and if the ED bits to not align with the data, move a read reference (RD), copy the second SRAM to the original SRAM, and attempt reading again, until the data is successfully recovered.

Abstract: According to one embodiment, a control module of a nonvolatile semiconductor memory drive has a first erase mode in which an address management table, which is indicative of a correspondency between logical block addresses and physical addresses of a nonvolatile semiconductor memory, is initialized to set the memory area of the nonvolatile semiconductor memory in a state in which no user data is written, a second erase mode in which the address management table is initialized to set the memory area in a state in which no user data is written, and the blocks, other than a defective block, which are included in the memory area, are erased, and a third erase mode in which the address management table is initialized to set the memory area in a state in which no user data is written, and the blocks, including the defective block, which are included in the memory area, are erased.