Abstract: A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: A method is designed for controlling a total mixing system including a first mixing system and a second mixing system, which are operated in a linked manner. In the method, the first mixing system stores first scene data specifying contents of a mixing process matching a scene. The second mixing system stores second scene data specifying contents of a mixing process matching a scene. The first mixing system transmits a scene recall request to the second mixing system when a recall event of the first scene data occurs. The second mixing system transmits back a recall enabling response to the first mixing system after receipt of the scene recall request. The first mixing system reconstructs the contents of the mixing process on the basis of the first scene data after the reception of the recall enabling response. The second mixing system reconstructs the contents of the mixing process on the basis of the second scene data after the transmission of the recall enabling response.

Abstract: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in combination with a stored record of known flaws, errors, or questionable data bits of a read memory row or block to allow for more efficient processing and correction of these errors. An embodiment of the present invention utilizes an erasure pointer that can store the location of N bad or questionable bits in the memory segment that is currently being read, where for each bit stored by the erasure pointer the embodiment also contains 2N ECC generators to allow the read data to be quickly checked with the know bad bits in each possible state. This allows the read data to then be easily corrected on the fly before it is transferred by selecting the bad bit state indicated by the ECC generator detecting an uncorrupted read.

Abstract: In accordance with aspects of the present invention, there is provided a repair method of a multi-chip that comprises a plurality of memory chips, each of the memory chips storing information with respect to remaining redundancy cells after repairing at a chip level. The repair method includes testing one of the plurality of memory chips; when the tested memory chip is judged to be defective, checking whether the tested memory chip is repairable, based on the stored information of the remaining redundancy cells; and when the tested memory chip is judged to be repairable, repairing the tested memory chip.

Abstract: A method and apparatus for repairing defective cells for each section word line. The repairing apparatus includes an address comparison unit and a repairing unit. The address comparison unit compares a main address of a defective address, indicating the location of a defective cell, to a main address of an external address. The address comparison unit determines when a redundancy main word line corresponding to the main address of the external address is activated. The repairing unit activates a redundancy section word line corresponding to a section address of the external address from among a plurality of redundancy section word lines connected to the redundancy main word line in order to repair the defective cell. Accordingly, defective cells are repaired for each section word line while minimizing the area of the repairing apparatus. Randomly generated defective cells can be efficiently repaired.