Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Abstract: A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media.

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract: A method for determining installation locations of a plurality of fault indicators in a power network includes a database retrieving step, an installation location setting step, a fault analyzing step, a communication quality analyzing step, a successful probability determination step and an installation location updating step. An apparatus for determining installation locations of a plurality of fault indicators in a power network includes a database, a processor, a fault analyzing module and a communication analyzing module. The processor retrieves graphical information, communication quality information, and fault rate information of feed lines of the power network from the database. The fault analyzing module generates a plurality of fault points in different zones of the power network.

Abstract: A computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. The configuration of rooms may include a tree-structure for the rooms. The room constraints may include a common symmetry line for a first room and a second room. The device constraints may include a self-symmetry constraint for a first device about a symmetry line in a first room. The device constraints may include a symmetry constraint for a first device and a second device about a symmetry line in a first room. The devices may include analog or RF (radio frequency) devices.

Abstract: An improved method, system, user interface, and computer program product is disclosed for performing graphical analysis of coverage. According to some approaches, a graphical user interface uses treemaps to provide analysis of verification coverage. This allows the user to efficiently obtain the overall and/or complete picture of the coverage space, as well as the relative size of nodes in terms of number of coverage elements contained in them. Moreover, the present treemap approach provides relative comparison of coverage of the nodes and allows the user to identify whether there is any missing coverage, and if so, whether the missing coverage evenly balanced. This information is very useful for the decision made by the user regarding overall coverage and steps to be taken to improve the coverage.

Abstract: An integrated circuit device layout is created based on charge carrier mobility characteristics of the device's non-functional cells. The charge carrier mobility of the non-functional cells can alter behavioral characteristics such as the hold time, setup time, or leakage current of nearby functional logic cells. Accordingly, a layout tool creates the layout for the integrated circuit device by selecting and placing non-functional cells having different mobility so as to selectively alter the characteristics of nearby logic cells.

Abstract: A method of generating a representation of an electronic circuit across a plurality of design entry tools includes extracting a first partial circuit including a first plurality of first electronic components from a first partition, extracting a second partial circuit including a second plurality of second electronic components from a second partition, generating a simulation block in the first design entry tool including an interface between the first and second partitions, exporting a first netlist representing the interconnection of the first electronic components in the first partial circuit, populating the simulation block in the second design entry tool to include a second netlist representing the interconnection of the second electronic components in the second partial circuit and the interface between the first and second partitions, and exporting the second netlist to stitch the extracted first and second partial circuits using the interface between the first and second partitions.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Abstract: Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.

Abstract: A computer-based method and a computing device for checking stub lengths of via stubs of a printed circuit board (PCB) layout are provided. The computing device displays a check interface, selects signal transmission line from a currently run PCB layout through the check interface, receives a reference stub length input through the check interface, and determines the actual stub length of each via stub of each via each selected signal transmission line connected to. The computing device further determines that a design of one via stub satisfies the design standards, if the actual stub length of the one stub via is less than or equal to the reference length, and determines that a design of one via stub does not satisfy the design standards if the actual stub length of the one via stub is greater than the reference stub length.

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.

Abstract: Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.

Abstract: An automated system, and method of operating the same, for assisting the layout of components and the routing of conductors in a layout of an integrated circuit. An asymmetric zoom command is provided, by way of which the user can magnify the current view of a portion of the layout in one dimension while maintaining the original magnification in the orthogonal dimension. The commands can be conveyed by keystrokes, or by a command in combination with a drawn rectangle indicating the extent of the asymmetric zoom magnification. Both asymmetric zoom-in and asymmetric zoom-out are supported.

Abstract: A through-hole layout apparatus and method for reducing differences in layout density of through-holes. The through-hole layout apparatus includes an extractor, which extracts an existing through-hole from design data for a semiconductor integrated circuit, a calculator, which calculates a layout density of through-holes in a predetermined region for each through-hole extracted by the extractor, a selector, which selects a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor and a through-hole adder, which determines a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added for each target through-hole selected by the selector.

Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

Abstract: A system and method are provided for configuring a programmable integrated circuit including a number of function blocks. In one embodiment, the system includes a programmable integrated circuit including a number of function blocks, and a host computing device to configure the number of function blocks to perform a number of functions. The host computing device utilizes a graphical user interface to provide specification of configuration parameters of the function blocks, and the graphical user interface updates a given configuration parameter if a value of the given configuration parameter is affected by a value specified for another configuration parameter. Other embodiments are also provided.

Abstract: A system is disclosed for displaying circuitry interconnections as flightlines between a component specified as the local component and the foreign components connecting to the local component. Upon obtaining data of the circuit components and interconnections, a user can designate the local component from among all of the circuit components. The system determines the foreign components connected to that local component, retrieves the flightline appearance display settings for the computer display, and renders a view of the specified local component and its foreign components with flightlines representing each interconnection connection. The flightlines can be color coded to indicate inputs, outputs or other characteristics of interest to the user.

Abstract: Approaches for estimating power consumption of a circuit based on a circuit design. For one or more modules of the design, data are input that indicate measured power consumption and circuit resources used by the one or more modules. For one or more other parts of the design, values of parameters are input that specify an operating speed and a resource count. Process-corner, voltage, and temperature values are input. An estimated level of power consumption is determined as a function of the measured power consumption, the values of the parameters, and the values of the process-corner, voltage, and temperature. Data indicative of the estimated level of power consumption are output.

Abstract: A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

Abstract: A user device receives a request to perform an automatic clock insertion operation for an integrated circuit; retrieves location information regarding a group of components, of the integrated circuit, that use a clock signal; deploys a clock mesh based on the location information regarding the group of components; and inserts drop points into the clock mesh; deploys a particular buffer for a particular drop point; maps a component, of the group of components, to the particular buffer; generates a clock box for the particular buffer, where dimensions of the clock box are based on a location of the component; deploys an H-tree for the clock box, where dimensions of the H-tree are proportional to the clock box dimensions; connects the H-tree to the component; and displays or stores clock mesh information, information regarding the group of buffers, information regarding the H-tree, and the location information regarding the group of components.

Abstract: A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to remain as a step difference of a predetermined amount or more in a case where a planarization process is performed on a planarizing film on a pattern by a quantitative calculation by using at least one of a density of patterns, a pattern width, and a peripheral length of a range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain as a step difference, and making a correction to a layout in which a step difference of a predetermined amount or more does not remain.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: Protocol related data generated by a simulation application are captured. One or more protocol objects are displayed in a window on a display device based on the protocol related data. The protocol objects represent events associated with the interface protocol. In at least some embodiments, a location of the protocol objects on the display device is correlated to a simulation time. In at least some embodiments, protocol-related data are grouped according to an abstraction level of the interface protocol, and the protocol objects are displayed on the display device based on grouping. The protocol objects displayed on the display device can be associated with concurrent, interleaved protocol events, or both.

Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.

Abstract: A method of designing an integrated circuit (IC) includes simulating aging evolution of the IC by providing a standard cells library, and a device activity file of device electrical activity in the standard cells as a function of electrical activity at the pins of the standard cells, taking into account Hot Carrier Injection, Negative Bias Temperature Instability, and gate oxide breakdown. A standard cell evolution file is provided that stores electrical characteristic aging data of standard cells. An instance activity file is provided of simulated electrical activity at the pins of individual instances of the cells in the IC. The instance activity file and the device activity file are used to analyze device activity and consequent aging evolution of the devices, and then generate data for consequent aging evolution of the IC. The IC design can then be modified to account for the aging evolution.

Abstract: A computer aided design system comprises a storage module, an interface creating module, and a calculating module. The storage module stores a contact list, one or more programs, and coordinates of each net which is being composed of a plurality of cline segments. The interface module creates a parameter setting interface on the screen of the device to display a design with a plurality of to-be-calculated nets and select at least one net in response to the user's operation. The calculating module calculates the length of each branch of the selected nets.

Abstract: An automated system, and method of operating the same, for editing the floorplan, placement, and toplevel wiring routing in a layout of an integrated circuit. Components in the layout of the integrated circuit, such components including functional blocks or subchips, and also wire segments of the toplevel wiring, are associated with horizontal reference frames and vertical reference frames. Each reference frame has its position, in the orthogonal direction, specified by a position of a reference line. The positions of subchips and wire segments within the reference frame are expressed as offsets from the reference line. Movement of components is accomplished by moving the reference frame in the orthogonal direction, and updating the reference line position while maintaining the offset values constant.

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a power line is selected from a layout diagram of the PCB. The method searches for one or more signal lines which are overlapping with the selected power line from the layout diagram of the PCB. The method further locates attribute data of the searched signal lines and the selected power line in the layout diagram of the PCB, and displays the attribute data of the searched signal lines and the selected power line on a display device of the electronic device.

Abstract: A computer aided design system comprises a dividing module, a storage, an interface creating module, a selecting module, and a display module. The dividing module divides the names into groups according to a predetermined rule. The group comprises a plurality of the targets set on the different layers. The storage records the relationship between the groups and the targets. The interface creating module creates a user interface base on the groups and selects at least one group in the same user interface from the operation of the user. The selecting module selects targets according to the selected groups. The display module displays the selected targets.

Abstract: A method for IC modification is disclosed. The method recognizes an original HDL file prescribing an original logic, an original netlist incorporating the original logic, and a new HDL file prescribing a new logic. The new logic comprises desired logic changes relative to the original logic. If a signal is different between the new HDL file and the original HDL file the method adds a user hint to both the original HDL file and the new HDL file. Using the original HDL file, the original netlist, the new HDL file, and the user hints, the method synthesizes a delta netlist for inserting into the original netlist, whereupon this insertion the original netlist will incorporate the new logic.

Abstract: A system and method for identifying circuit components of an integrated circuit includes a processor identifying geometric characteristics of an integrated circuit and sorting the geometric characteristics by order of occurrence of each geometric characteristic. Co-occurring arrangements of the geometric characteristics are then identified and used to identify a standard cell. The geometric characteristics of the standard cell may then be compared to the geometric characteristics of a known cell. Each electrically significant geometric characteristic of the standard cell can be compared to the electrically significant geometric characteristics of the known cell. If the standard cell matches the known cell an instance of the standard cell can be placed in a layout. Once placing the standard cell in the layout a netlist can be extracted.

Abstract: A method, system, and computer program product for machine learning approach for detecting and correcting lithographic hot-spots in an integrated circuit (IC) design are provided in the illustrative embodiments. A layout corresponding to the IC design is received at a machine learning model (ML model). At the ML model using a hardware component, a set of input objects is identified corresponding to a target shape in the layout. A retargeting value is predicted for the target shape using the set of input objects, such that applying the retargeting value to the target shape in the layout causes the target shape to be modified into a modified target shape, wherein printing the modified target shape instead of the target shape eliminates a lithographic hot-spot that would otherwise occur from printing the target shape in a printed circuit corresponding to the IC design.

Abstract: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.

Abstract: A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.

Abstract: Technique assesses the impact of physical circuit variations, specification parameter variation, or process variations on clock, signal, and power network performance and through a hierarchical modeling and hierarchical Monte Carlo simulation method.

Abstract: Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.

Abstract: Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications.

Abstract: An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.

Abstract: The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters of volume resistance and circuit speed, which are correlated therewith, and whose electrical parameters can be described as a function of the geometrical gate electrode design. Here, both discrete and integrated vertical transistors may be concerned.

Abstract: A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.

Abstract: Disclosed is a development support apparatus of a semiconductor device that makes it possible to easily develop the semiconductor device, a development support method, and a program product. A design evaluation apparatus is a design evaluation apparatus having an analog front-end unit for inputting a measurement signal of a sensor and an MCU unit, which has a GUI processing unit for displaying a GUI corresponding to a circuit configuration of the analog front-end unit and a register setting unit that generates setting information for setting up the circuit configuration and a circuit characteristic of the analog front-end unit based on an operation of the GUI by a user, and sets the generated setting information in the analog front-end unit through the MCU unit.

Abstract: A program calling system includes a memory, an interface establishing unit, a detecting unit, and a calling unit. The memory stores functions for PCB layout design. Each function corresponds to a path and a name, and can be accessed via the corresponding path and name. The interface establishing unit establishes a user interface. The user interface includes a first area for displaying the names of the functions. A one to one relationship exists between the names and the paths of the functions. The detecting unit detects whether a calling signal is generated, and obtains a name of a to-be-called function when the calling signal is generated. The calling unit responds to the calling signal to obtain a path of the to-be-called function according to the name of the to-be-called function and the one to one relationship, and call the to-be-called function according to the obtained path and name.

Abstract: A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.

Abstract: A method for designing a system to be implemented on a target device includes computing slack potential of paths between components on the target device after timing analysis. A graphical representation of the slack potential and slack for the paths is generated. The graphical representation identifies that a design change is required for a first portion of the system associated with a first path and that a change in placement is required for a second portion of the system associated with the second path.

Abstract: A method for reordering scan chain segments of scan chains in an electronic circuit design includes identifying congestion areas on a congestion map. A routing preference for each congestion area is determined. Scan cells associated with each congestion area are formed into the scan chain segments and then the scan chain segments are re-ordered based on the routing preference of the corresponding congestion area.

Abstract: A word processing or spreadsheet application is augmented by a plug-in and templates for computer aided design of electronic hardware entities. The plug-in utilizes the application programming interface to provide a menu system and executable code which inserts templates, reads and validates data entered into the template, computes addresses, annotates addresses and error messages back to a word processing document for display in the editor of the word processing document, and upon selection and request, generates output files for target simulators or synthesis tools.

Abstract: Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask.