Abstract: A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length.

Abstract: A method is disclosed for structuring a function plan into function plan sections. The function plan includes function modules. Individual function modules are connected to at least one other function module of at least one function module connection. If the function plan exceeds the predefined area of the function plan section, a first determination of the arising function module external connections in an assignment of the individual function modules to the individual function plan sections occurs for each function plan variant, and the individual function modules are assigned to the function plan sections according to the function plan variant having the least possible number of function module external connections.

Abstract: According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.

Abstract: Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system obtains a set of parameters associated with parameterized connections in a hierarchy of the design and a set of net assignments to the parameters. Next, the system displays the parameters and the net assignments to a user of the EDA application through a graphical user interface (GUI) associated with the EDA application. Finally, the system enables modifications to the net assignments by the user through the GUI.

Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image on a display device with or more shapes, and causing a display of multiple labels on the display device. Each of the labels is associated with a different one of the displayed shapes, and the labels are derived from stored connectivity information for the one or more shapes describing the connections of the shapes.

Abstract: The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Abstract: Differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit can be determined by comparing an image of pins of a partitioned logic block in a first floorplan of the integrated circuit with an image of pins of the partitioned logic block in a second floorplan of the integrated circuit. The second floorplan can represent a new floorplan design resulting from a change to an integrated circuit design represented by the first floorplan. If no differences exist between pins of the partitioned logic block in the first and second floorplans, information representing the partitioned logic block in the second floorplan can be substituted with information representing the partitioned logic block in the first floorplan.

Abstract: A method of automating circuit design is provided and includes storing one or more circuit design schematics in a memory, providing, by way of an interface, a plurality of search parameters for searching for nets of the schematics in the memory, searching for nets of the schematics in the memory in accordance with search parameters input into the interface and presenting, by way of the interface, information associated with a net matching the received search parameters.

Abstract: The present invention relates to the field of semiconductor manufacturing, and particularly to a method of making Optical Proximity Correction to an original gate photomask pattern based on different substrate areas. The present invention discloses a method of making OPC to an original gate photomask pattern based on different substrate areas, which makes correction to gate photomask pattern dimension on the AA and to gate photomask pattern dimension on the STI respectively by creating two different optical proximity effect models of the gate, so as to control the finally imaged gate photomask pattern dimensions more accurately; moreover, the error of the correction result of the gate spacing dimension on the STI can be reduced by 4% by separating the patterns and using the gate model based on the STI, so as to avoid the spacing dimension error when the photolithography exposure conditions vary.

Abstract: A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time.

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract: A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement method can be used, for example, in the fabrication of an integrated circuit having at least two complementary portions for which relatively tight circuit-matching requirements need to be met.

Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

Abstract: The present disclosure is directed to a technique that can be applied to a situation in which a single product is designed by multiple designers using a CAD. During a modification operation of feature data, portions that are referenced to are accumulated in a referenced portion accumulation unit. A portion that has been modified is obtained from new and old feature data, and a determination is made as to whether a reference to the modified portion has been made, based on the information accumulated in the referenced portion accumulation unit. Information about the modified portion that is determined as having been referenced to is displayed on a display.

Abstract: A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved.

Abstract: Methods and systems are provided to reduce the complexity of sequential digital circuitry including cells of unknown function by grouping and defining like instance of combinational circuitry cells. The system groups together cells that feed into the same combination of one or more state cells. The groups of cells are then replaced by clouds which are defined in the netlist for the sequential digital circuitry to produce a simpler representation of the circuitry for analysis purposes and to aid in determining the function of those cells for which the function is unknown.

Abstract: Embodiments of a computer system, a method, a graphical user interface and a computer-program product (i.e., software) for use with the computer system are described. A chip designer may use these devices and techniques to configure and monitor the execution of tasks in a user-configurable electronic-design-automation (EDA) flow associated with a circuit or chip design. In particular, using an intuitive and interactive graphical user interface in EDA software, the chip designer can configure and initiate execution of the EDA flow. Then, during execution of EDA tasks in the EDA flow, an execution monitor in the graphical user interface may provide a graphical representation of real-time execution status information for the EDA tasks. Moreover, using the EDA software, the chip designer can debug the circuit or chip design if any errors or problems occur.

Abstract: A computing device reads a printed circuit board (PCB) layout file from a storage device. The PCB layout file includes arrangement information of signal lines, power lines, and power through-holes arranged on a PCB. Furthermore, the computing device sets a reference distance between a selected power through-hole and a neighboring signal line, and searches for one or more line segments of one or more signal lines where the a distance between each of the one or more line segment and the selected power through-hole is less than the reference distance.

Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.

Abstract: A computer-implemented method for component arrangement in a PCB layout device is provided. The device includes wiring diagrams. First, generates a PCB encapsulation diagram corresponding to the selected wiring diagram. Then, obtains the coordinates of each electronic component in the selected wiring diagram. Next, generates a prompt to prompt the user to select a reference point in the PCB encapsulation diagram. Then, obtains the coordinates of the reference point. Next, determines an abscissa difference and an ordinate difference between one component in the wiring diagram and the reference point. Then, determines the coordinates of each encapsulated component in the PCB encapsulation diagram according to the abscissa difference, the ordinate difference, and the coordinates of each electronic component in the wiring diagram. And last, moves each encapsulated component to the determined corresponding coordinates of each encapsulated component in the PCB encapsulation diagram.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: A design support apparatus that supports designing of a circuit and is connected to a display unit, the design support apparatus includes a storage unit that stores logical connection information of the circuit and cell information of a plurality of cells included in the circuit, a selection unit that selects target cell information of a cell to be placed out of the cell information stored in the storage unit, a placement unit that provisionally places the cell corresponding to the selected target cell information based on inputted positional information, a determination unit that determines whether a wiring mode is set, a wiring unit that provisionally arranges wiring connected to the provisionally placed cell when the determination unit determines that the wiring mode is set, and a finalization unit that finalizes a position of the wiring provisionally arranged based on finalization of a position of the cell provisionally placed.

Abstract: Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking.

Abstract: A system includes an automated place and route tool to generate a layout of an integrated circuit (IC) die based on a gate level circuit description. A machine readable persistent storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second IC dies, respectively, and a second portion encoded with a second gate level description of the plurality of circuit patterns received from the tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented verification module is provided for comparing the first and second gate level descriptions and outputting an error report if the second gate level description has an error. The verification module outputs a verified second gate-level description of the first and second circuit patterns.

Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer executing tentative wiring processing between a first terminal group and a second terminal group in a tentative wiring area to execute a process. The process includes detecting unwired nets occurring in the tentative wiring area consequent to the tentative wiring processing; updating the tentative wiring area by expanding the tentative wiring area according to the number of unwired nets, if any unwired nets are detected at the detecting; controlling to execute the tentative wiring processing and the subsequent detecting with respect to the tentative wiring area updated at the updating; and determining the tentative wiring area to be a wiring area if no unwired nets are detected at the detecting.

Abstract: In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.

Abstract: Method and apparatus for generating an implementation of a program language circuit description for a programmable logic device (PLD) is described. In one example, the program language circuit description is analyzed to identify constructs indicative of dynamic function re-assignment. A hardware description of the program language circuit description is generated. The hardware description includes a plurality of implementations responsive to the identified constructs. Physical implementation data is generated from the hardware description. The physical implementation includes a plurality of partial configurations for the PLD based on the respective plurality of implementations in the hardware description.

Abstract: A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces.

Abstract: A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels.

Abstract: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present.

Abstract: Embodiments of the present invention include systems and methods for performing design automation on a mobile computer system. In one example embodiment the present invention includes a computer-implemented method comprising storing design automation data on a mobile device, displaying a plurality of design automation process steps to a user, the plurality of design automation process steps guiding the user through a design automation process for a project, receiving design automation input data from the user in the mobile device for a plurality of the design automation process steps, executing one or more data processing algorithms specific to at least one of the design automation process steps, and generating output data for the design project.

Abstract: A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout is displayed.

Abstract: Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

Abstract: Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.

Abstract: Methods and systems for viewing and debugging HDL designs having SystemVerilog interface constructs are provided. An HDL design code is received, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct. A first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct are displayed in a schematic view. The interface object is disposed between the first and second objects, and a shape of the interface object is different from that of the first and second objects. The interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.

Abstract: A computer-implemented method identifies at least one proprietary geometric figure from a plurality of geometric figures within a design data layout format file. The proprietary geometric figure in the design data layout format file may be replaced with a placeholder geometric figure. Cell names and connection names associated with the proprietary geometric figure are renamed from a netlist file that defines electrical connections between the geometric figures with obfuscating names. A modified design data layout format file may be generated that includes the placeholder geometric figure and a modified netlist file including the obfuscating names. The modified file enables IC designers to complete their design and checking activities, but inhibits reverse-engineering of the proprietary geometric & netlist data.

Abstract: A method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based on the physical layout, and obtaining a wiring not meeting a specification having the signal delay previously set therein; and setting a portion into which a repeater is to be inserted based on at least one result of results obtained from the information on the graphic and calculation for the transferred image, respectively, with respect to the wiring not meeting the specification.

Abstract: The Intelligent Graphics Plug Map System automatically converts plug maps into Intelligent Graphics with intelligent behaviors. The electronic trouble shooting system enables users to easily navigate large quantities of interrelated data and accurately analyze how each plug is used. The system automatically integrates additional information such as the function of each contact, what signals are connected to the contact, and what tools and processes are required to repair or test electrical circuitry. The system provides an Intelligent Plug Map Recognizer that associates a correct contact label for each contact associated with a plug map file defining a plug map; an HTML Generator that generates an HTML file for the plug map; a CGM4 File Builder that generates an intelligent plug map file from the plug map file; and a technical data system application that synchronizes plug map views when a contact associated with the plug map is identified.

Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.

Abstract: A system and method for graphically displaying modules and resources within a chip design software application. The system and method provide a data driven model for matching the hardware resource requirements for an associated user module and the available hardware resources on an underlying chip. Databases are utilized to describe the hardware resource requirements which are dictated by the particular user module and the available hardware resources of a particular chip. The user module descriptive database can be updated in response to additional user modules being added or changes to the hardware resource requirements of existing user modules. The hardware description database can be updated in response to additional chips being added. Further, the graphical interface relates both a user module and the possible hardware resource.

Abstract: A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.

Abstract: In one embodiment, a method of generating a circuit design is provided. For each data terminal connecting a plurality of components in a circuit design, a respective list of dimensions of data used by the data terminal are determined. A plurality of exchange orderings are generated that each indicate an order in which dimensions are exchanged between the lists. For each exchange ordering, dimensions are exchanged between the lists according to the exchange ordering to produce a set of supplemented lists of dimensions. A set of buffers for buffering data between the data terminals are determined based on the supplemented lists of dimensions. Memory requirements are determined for each of the set of buffers. The circuit design is modified to include the one of the determined sets of buffers having a lowest memory requirement.

Abstract: A circuit design assisting apparatus for assisting a layout tool in designing an integrated circuit that includes a circuit module having plural cells achieving a prescribed function. A cell connection information acquiring device is provided to acquire cell connection information that specifies connection counterparts to the plural cells and is used when auto layout is executed by the layout tool. A terminal designating device is provided to designate a terminal of the circuit module. A terminal connection information generation device is provided to generate terminal connection information that specifies connecting counterparts to the terminal. A buffer circuit addition determining device is provided to determine one of if a buffer circuit is additionally connected between the terminal and the counterpart and if the buffer circuit already connected to the terminal is replaced in accordance with the terminal connection information.

Abstract: An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counter(s). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data.

Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Abstract: An embodiment of a method for enabling a high level modeling system for implementing a circuit design in an integrated circuit device includes: receiving a high-level characterization of the circuit design; receiving a portable location constraint associated with elements of the circuit design; and generating, by a computer, a low-level characterization of the circuit design based upon the high-level characterization and the portable location constraint.