Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing a size of the candidate pattern thereby revising the layout diagram.

Abstract: A method includes providing attributes of a manufacturing process and an image of a product associated with the manufacturing process to a trained machine learning model. The method further includes obtaining, from the trained machine learning model, predictive data. The method further includes determining, based on the predictive data, image measurements of the image of the product associated with the manufacturing process. Manufacturing parameters of the manufacturing process are to be updated based on the image measurements.

Abstract: The present disclosure relates to embodiments for collaborative electronic design. Embodiments may include receiving a baseline model at a computing device associated with each of a plurality of geographically dispersed electronic design teams. Embodiments may further include applying environmental data from each of the plurality of geographically dispersed electronic design teams to the baseline model. Embodiments may also include generating a plurality of training changes, based upon, at least in part, the applied environmental data from each of the plurality of geographically dispersed electronic design teams. Embodiments may also include encrypting the plurality of training changes to create a plurality of encrypted training changes. Embodiments may further include providing the plurality of encrypted training changes to a centralized host configured to aggregate the plurality of encrypted training changes.

Abstract: Systems and methods for optimal electron beam metrology guidance are disclosed. According to certain embodiments, the method may include receiving an acquired image of a sample, determining a set of image parameters based on an analysis of the acquired image, determining a set of model parameters based on the set of image parameters, generating a set of simulated images based on the set of model parameters. The method may further comprise performing measurement of critical dimensions on the set of simulated images and comparing critical dimension measurements with the set of model parameters to provide a set of guidance parameters based on comparison of information from the set of simulated images and the set of model parameters. The method may further comprise receiving auxiliary information associated with target parameters including critical dimension uniformity.

Abstract: An example operation may include one or more of scanning, by a mobile node, a physical object to generate a scan data, extracting, by the mobile node, a set of features from the scan data, generating, by the mobile node, a feature vector based on the set of the features, applying, by the mobile node, a cryptographic hash function to the feature vector to produce a hash value, encrypting, by the mobile node, the set of the features with the hash value, and executing a smart contract to store the encrypted set of the features on a blockchain.

Abstract: A lithographic apparatus and associated method of controlling a lithographic process. The lithographic apparatus has a controller configured to define a control grid associated with positioning of a substrate within the lithographic apparatus. The control grid is based on a device layout, associated with a patterning device, defining a device pattern which is to be, and/or has been, applied to the substrate in a lithographic process.

Abstract: Systems and methods for validation of photonics device layout designs. A method includes receiving, by a computer system, a rule deck and a layout design. The layout design includes silicon photonics (SiP) structures. The method includes performing a verification process to produce verification results. The verification results include violations and the violations include SiP violations. The method includes performing SiP spacing filtering to filter the SiP violations into true SiP violations and false SiP violations. The method includes storing the true SiP violations in a result database.

Abstract: An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

Abstract: An integrated circuit including standard cells, a method and a computing system for designing and fabricating the same are provided. A computer-implemented method involves placing, based on a standard cell library, standard cells of an integrated circuit to be fabricated, and routing the placed standard cells. A position of a first wiring of a placed cell among the placed standard cells may be adjusted based on a position of a second wiring used for the routing. The first wiring is provided from at least one standard cell, formed in a same layer as that of the second wiring, and spaced from the second wiring in a first direction. An integrated circuit layout having the adjusted position of the first wiring, is produced.

Abstract: A method of determining a relationship between a stochastic variation of a characteristic of an aerial image or a resist image and one or more design variables, the method including: measuring values of the characteristic from a plurality of aerial images and/or resist images for each of a plurality of sets of values of the design variables; determining a value of the stochastic variation, for each of the plurality of sets of values of the design variables, from a distribution of the values of the characteristic for that set of values of the design variables; and determining the relationship by fitting one or more parameters from the values of the stochastic variation and the plurality of sets of values of the design variables.

Abstract: An analytic system provides direct functional principal component analysis. (A) A next group variable value is selected from values of a group variable. (B) Explanatory variable values of observations having the selected next group variable value are sorted in ascending order. (C) The response variable value associated with each sorted explanatory variable value is stored in a next row of a data matrix. (D) (A) through (C) are repeated. (E) An eigenfunction index is incremented. (F) An FPCA is performed using the data matrix to define an eigenfunction for the eigenfunction index. (G) (E) and (F) are repeated. (H) FPCA results from the performed FPCA are presented within a window of a display. The FPCA results include an eigenvalue and an eigenfunction associated with the eigenvalue for each functional principal component identified from the performed FPCA in (F).

Abstract: A method of determining overlay of a patterning process, the method including: obtaining a detected representation of radiation redirected by one or more physical instances of a unit cell, wherein the unit cell has geometric symmetry at a nominal value of overlay and wherein the detected representation of the radiation was obtained by illuminating a substrate with a radiation beam such that a beam spot on the substrate was filled with the one or more physical instances of the unit cell; and determining, from optical characteristic values from the detected radiation representation, a value of a first overlay for the unit cell separately from a second overlay for the unit cell that is also obtainable from the same optical characteristic values, wherein the first overlay is in a different direction than the second overlay or between a different combination of parts of the unit cell than the second overlay.

Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.

Abstract: An image acquisition device compresses a media signal representative of a scene based on a sensing matrix that is a determined by a sensing matrix template and a set of template parameters. The image acquisition device provides the compressed media signal to a receiver and selectively provides a specification of a subset of the set of template parameters to the receiver. The receiver extracts one or more scene descriptors representative of one or more portions of the scene from the compressed media signal using the sensing matrix template without knowledge of the template parameters that are not included in the subset. The template parameters that are not included in the subset are not received by the receiver.

Abstract: A method including obtaining (i) measurements of a parameter of the feature, (ii) data related to a process variable of a patterning process, (iii) a functional behavior of the parameter defined as a function of the process variable based on the measurements of the parameter and the data related to the process variable, (iv) measurements of a failure rate of the feature, and (v) a probability density function of the process variable for a setting of the process variable, converting the probability density function of the process variable to a probability density function of the parameter based on a conversion function, where the conversion function is determined based on the function of the process variable, and determining a parameter limit of the parameter based on the probability density function of the parameter and the measurements of the failure rate.

Abstract: A defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method including: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.

Abstract: A method and system for calculating probability of success or failure for a lithographic process due to stochastic variations of the lithographic process are disclosed. Lithography is a process that uses light to transfer a geometric pattern from a photomask, based on a layout design, to a resist on a substrate. The lithographic process is subject to random stochastic phenomena, such as photon shot noise and stochastic phenomena in the resist process and resist development, with the resulting stochastic randomness potentially becoming a major challenge. The stochastic phenomena are modeled using a stochastic model, such as a random field model, that models stochastic randomness the exposure and resist process. The stochastic model inputs light exposure and resist parameters and definitions of success of success or failure as to the lithographic process, and outputs a probability distribution function of deprotection concentration indicative of success or failure probability of the lithographic process.

Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include receiving a first circuit design pattern including a DRC violation and generating a first pattern matrix based on the first circuit design pattern, and updating the first circuit design pattern, based on the first pattern matrix, to fix the DRC violation. The operations may also include determining a possibility of a DRC violation-free first circuit design pattern corresponding to the first pattern matrix, and generating a first target label specifying the fixability corresponding to the first pattern matrix based on the determined possibility of the DRC violation-free first circuit design pattern. The first pattern matrix and the first target label may be used as training data to train a machine-learning model to predict fixability of the DRC violation.

Abstract: A method including: obtaining information regarding a patterning error in a patterning process involving a patterning device; determining a nonlinearity over a period of time introduced by modifying the patterning error by a modification apparatus according to the patterning error information; and determining a patterning error offset for use with the modification apparatus based on the determined nonlinearity.

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

Abstract: Techniques and systems for capturing and using routing intent in an integrated circuit (IC) design are described. Some embodiments use a graphical user interface (GUI) to capture routing intent for a net, wherein the routing intent includes a set of circuit objects associated with the net, a routing pattern, and optionally a set of user-provided attribute values. Next, the embodiments provide the routing intent to a router, wherein the router uses the routing intent to route the net.

Abstract: A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.

Abstract: This application discloses a computing system implementing an optical proximity correction model calibration tool to determine parameters for gauges describing features of an integrated circuit. The gauges include values corresponding to measurements collected for a set of the features. The optical proximity correction model calibration tool can ascertain densities of the gauges based on the measurements associated with the parameters for the gauges, and set weights for the gauges based, at least in part, on the densities. The optical proximity correction model calibration tool can calibrate an optical proximity correction (OPC) model using the weights for the gauges. The OPC model calibrated with the weights of the gauges can be utilized to predict of a printed image on a substrate described by a mask layout design corresponding to the integrated circuit.

Abstract: A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including; determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.

Abstract: Systems and methods for layout analysis using unit cell properties. A method includes receiving a layout design and analyzing the layout design to identify unit cells in the layout design. The method includes designating points of interest each corresponding to a respective one of the unit cells and classifying the unit cells into a plurality of classifications using the points of interest and the corresponding properties. The method includes identifying unique patterns of the unit cells, and producing a reduced layout including the unique patterns of unit cells. The method includes performing layout processing on the reduced layout and propagating the process results from each of the unique patterns of unit cells in the reduced layout to other unit cells of the layout design having the same classification.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: One illustrative system includes a processor and memory storing instructions that, when executed by the processor, cause the system to receive a device layout including a curvilinear feature, define a plurality of vertices for the curvilinear feature, determine a radius of curvature between a selected vertex in the plurality of vertices and a neighboring vertex in the plurality of vertices, and identify a design rule violation for the curvilinear feature responsive to the radius of curvature being less than a predetermined threshold.

Abstract: Described herein is a framework for outdoor localization. In accordance with one aspect of the framework, a set of hotspot labels are received from one or more user devices connected to an outdoor wireless local area network. Manifold learning may be performed based on the set of hotspot labels to construct one or more manifolds. Using the one or more constructed manifolds, the framework may then estimate a location of a particular user device associated with a query record received from during an online location query.

Abstract: A method to determine a mask pattern for a patterning device. The method includes obtaining a target pattern to be printed on a substrate, an initial continuous tone image corresponding to the target pattern, a binarization function (e.g., a sigmoid, an arctan, a step function, etc.) configured to transform the initial continuous tone image, and a process model configured to predict a pattern on the substrate from an output of the binarization function; and generating a binarized image having a mask pattern corresponding to the initial continuous tone image by iteratively updating the initial continuous tone image based on a cost function such that the cost function is reduced. The cost function (e.g., EPE) determines a difference between a predicted pattern determined by the process model and the target pattern.

Abstract: Methods, systems, and non-transitory computer readable medium are described for automated image measurement for process development and optimization. A method includes receiving original images including a first original image. Each original image is of a corresponding product associated with a manufacturing process. The method further includes performing, based on process information about the manufacturing process, feature extraction to identify features of the first original image that are expected to change based on manufacturing parameters of the manufacturing process. The method further includes generating a first synthetic image of synthetic images by performing targeted deformation of one or more of the features of the first original image.

Abstract: Graphical interactive model selection is provided. A basis function is fit to each plurality of observation vectors defined for each value of a group variable. Basis results are presented within a first sub-window of a first window of a display. Functional principal component analysis (FPCA) is automatically performed on each basis function. FPCA results are presented within a second sub-window of the first window. An indicator of a request to perform functional analysis using the FPCA results based on a predefined factor variable is received in association with the first window. A model is trained using an eigenvalue and an eigenfunction computed as a result of the FPCA for each plurality of observation vectors using the factor variable value as a model effect. (G) Trained model results are presented within a third sub-window of the first window of the display.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: A method for setting parameters in design of a printed circuit board (PCB) includes obtaining multiple combinations of layout parameters of a PCB and inputting the multiple combinations of layout parameters into a predetermined PCB layout simulation software to obtain multiple interference parameter combinations. The multiple combinations of layout parameters and the multiple interference parameter combinations are defined as training samples, and a predetermined network model is trained through the training samples to obtain a first prediction model. The first prediction model is trained and tested to obtain an impedance prediction model. When the multiple combinations of layout parameters are inputted to the impedance prediction model, only an average predetermined error is allowed between impedance values predicted by the impedance prediction model and impedance values calculated by the predetermined PCB layout simulation software, to enable acceptance of that combination.

Abstract: A method for converting a circuit in a format of a first circuit simulation program to format of a second circuit simulation program includes identifying components in the circuit that are recognized by the second simulation program. Characteristics for components that are not recognized by the second simulation program are created. Connections in the circuit are formatted to a format that is recognized by the second simulation program. The components, characteristics, and connections are stored in a single computer-readable file.

Abstract: Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size. A method includes generating an initial set of integrated circuit (IC) design layout clips as a current set of IC design layout clips. The method includes removing any of IC design layout clips from the current set of IC design layout clips that do not meet the one or more usefulness criteria. The method includes, while a size of the IC design layout clips is less than a desired clip size, generating a new set of IC design layout clips from the current set of IC design layout clips according to every combination of pairs of the design layout clips in the current set of IC design layout clips, and repeating the removing process.

Abstract: A method of compensating for degradation of an optical source includes in part, generating a first model of the optical source at a first point in time, generating a second model of the optical source at a second point in time occurring after the first point in time, determining the difference between the first and second models, and varying a dose of the optical source if the determined difference is greater than a first threshold value. The compensation method optionally includes, in part, varying a focus distance of the optical source if the determined difference is greater than the first threshold value. The generation of the first model optionally includes, in part, generating wafer data from the optical source, and generating an optical proximity correction (OPC) model from the wafer data. The optical source may be an extreme ultraviolet optical source.

Abstract: A method for operating a data processing system that causes the data processing system to test the consistency between a schematic description of an electronic circuit and a physical implementation of that circuit includes a master device having a plurality of component devices connected by a network of conductors is disclosed. Each of the component devices has a plurality of package pins that connect the component device to the network of conductors. Information specifying a schematic netlist generated from the schematic description and specifying a layout description of the physical implementation is received by the data processing system. The layout description specifies the network of conductors. The data processing system determines any package shorts in the component devices and generates a layout netlist from the layout description. The layout netlist is compared with the schematic netlist.

Abstract: A method of generating an integrated circuit includes: receiving, by a processor, a first IC design layout; replacing, by the processor, a specific region in the first IC design layout with a first difference region; performing, by the processor, an inverse lithography technology process upon a junction region between the first difference region and the first IC design layout to generate a mask data; and causing the IC to be fabricated according to the mask data.

Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.

Abstract: A system may include an image clustering engine and a cluster provision engine. The image clustering image may be configured to access a set of circuit images and cluster the circuit images into different groups via an unsupervised learning process, wherein clustering by the unsupervised learning process is invariant to each invariant property of an invariant property set. A given invariant property in the invariant property set may correspond to a given image transformation, the invariant properties in the invariant property set may be discrete, and the total number of invariant properties in the invariant property set may be finite. The cluster provision engine may be configured to provide the clustered circuit images for further processing or analysis by an electronic design automation (EDA) application.

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.

Abstract: A method for manufacturing a photomask is provided. The method includes generating a plurality of virtual layouts; calculating a score for each of the plurality of virtual layouts in accordance with a total overlay area; comparing the scores of the plurality of virtual layouts and determining a modified layout having a target score out of the plurality of virtual layouts; and outputting the modified layout to a photomask. Each of the virtual layouts includes a plurality of the shifted features. A semiconductor manufacturing method is also provided.

Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.

Abstract: A system may include a quantum model engine configured to generate (e.g., load or instantiate) a quantum computing model to represent an electronic design automation (EDA) process for a circuit design. The EDA process may be a multi-patterning process to assign colors to geometric elements of the circuit design. The quantum computing model may include quantum particle types that may be defined to prohibit non-physical states in the quantum computing model from occurring. The quantum model engine may also be configured to generate a color assignment for the geometric elements of the circuit design through the quantum computing model. The system may also include a manufacture support engine configured to use the color assignment to support manufacture of circuit layers of the circuit design through multiple manufacturing steps.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.

Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.