Abstract: Method and system configured to reduce or even nullify the degradation of images created by the projector tool turns on the optimization of the pattern-imaging by adjusting parameters and hardware of the projector to judiciously impact the placement of various image edges at different locations in the image field. Adjustments to the projector (exposure tool) include a change of a setup parameter of the exposure tool and/or scanning synchronization and/or a change of a signature of the optical system of the exposure tool determined as a result of minimizing the pre-determined cost function(s) that are parts of a comprehensive edge-placement error model.

Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.

Abstract: Methods and systems are disclosed for determining a yield of a circuit in semiconductor manufacturing. In one embodiment, a computer implemented method includes performing a first pass of Monte Carlo simulations of the circuit to identify a plurality of failed sampling points in a high sigma region of a statistical distribution, partitioning the plurality of failed sampling points into a plurality of clusters based on angular separation of the plurality of failed sampling points, determining a boundary of each cluster in the plurality of clusters, performing sensitivity analysis from the boundary of the each cluster to identify an estimated closest failed sampling point associated with the each cluster, and performing a second pass of Monte Carlo simulations of the circuit to determine the yield of the circuit using the estimated closest failed sampling point associated with the each cluster and the boundary of each cluster in the plurality of clusters.

Abstract: Systems and techniques for facilitating layout of an integrated circuit (IC) design are described. A distinct color pattern can be assigned to a set of shapes in a layout of the IC design that correspond to a net. Next, the layout of the IC design can be displayed in a graphical user interface (GUI) of the IC design tool. Some embodiments can move a diffusion region of a multigate device with respect to the location of the device contacts so that the diffusion region is aligned with respect to a set of fin tracks, wherein each fin of each multigate device is located on a fin track.

Abstract: A method for optical proximity correction includes inputting a physical design having a plurality of shapes. Each shape has a plurality of corners, and the physical design is to be exposed on a surface of a substrate. A set of sub-resolution assist features (SRAFs) for the physical design is determined, where a plurality of SRAFs in the set of SRAFs interact. The plurality of SRAFs together provide better dimensional control of one corner of one shape in the plurality of shapes, when exposed on the substrate, compared to using a single SRAF to control a dimension of the one corner. The plurality of SRAFs includes a positive SRAF and a negative SRAF. A modified physical design is output, where the modified physical design comprises the physical design, as modified by the set of SRAFs.

Abstract: Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire images at different imaging configurations from each of a plurality of pattern areas of a test reticle. A reticle near field for each of the pattern areas of the test reticle is recovered based on the acquired images from each pattern area of the test reticle. A lithography model is applied to the reticle near field for the test reticle to simulate a plurality of test wafer images, and the simulated test wafer images are analyzed to determine whether the test reticle will likely result in an unstable or defective wafer.

Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Abstract: A memory stores layout data of a semiconductor circuit. A processor searches for a plurality of wiring routes on the basis of a plurality of cost calculating formulas that respectively represent a plurality of design rules, and on the basis of the layout data, wherein the plurality of wiring routes are a plurality of candidates for a wiring route that corresponds to a processing target net that is connection information that needs to be changed in the semiconductor circuit, and respectively satisfy the plurality of design rules. Then, the processor generates display information that displays the plurality of wiring routes obtained by the search.

Abstract: A mask includes a plurality of line patterns provided on a substrate, the plurality of line patterns each including a line comprising a plurality of first layers and a plurality of second layers alternately stacked on the substrate. The lines of the plurality of line patterns extend in a first direction and the lines of the plurality of line patterns are spaced in a second direction crossing the first direction. A line of one of the plurality of line patterns has a first portion and a second portion on a side of the first portion in the first direction, the first portion wider than the second portion in the second direction.

Abstract: A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether ?1<?1, wherein ?1 represents model vs. exposure difference and ?1 represents predetermined criteria. The technique further includes completing the model when ?1<?1.

Abstract: A method of manufacture comprises a mask process correction (MPC) and verifying MPC accuracy. MPC may be performed on mask tape-out (MTO) data describing a mask pattern to obtain mask process corrected data. MPC may be performed to address a deviation between the MTO data and a mask to be manufactured. Verification of the MPC may be performed by generating a two-dimensional (2D) contour of mask pattern elements based on the mask process corrected data. When MPC has been verified, the mask process corrected data may be used to manufacture a mask and a semiconductor device.

Abstract: A layout file for an integrated circuit has drawn geometries. Variable fill geometries are added to local areas based on densities of the drawn geometries in windows associated with the local areas and on the global density of all the drawn geometries in the layout file. Each window has a separate local area associated with it. The densities of the variable fill geometries in the local areas are not all equal. Densities of the fill geometries are higher in local areas associated with windows having lower densities of the drawn geometries, and for lower values of the global density. The layout file is stored in a computer-readable medium which may be used to produce a photomask for manufacturing an integrated circuit.

Abstract: A method for transferring a fractured pattern decomposed into elementary shapes, onto a substrate by direct writing by a particle or photon beam, comprises a step of identifying at least one elementary shape of the fractured pattern, called removable elementary shape, whose removal induces modifications of the transferred pattern within a preset tolerance envelope; a step of removing the removable shape or shapes from the fractured pattern to obtain a modified fractured pattern; and an exposure step, comprising exposing the substrate to a plurality of shots of a shaped particle or photon beam, each shot corresponding to an elementary shape of the modified fractured pattern. A computer program product for carrying out such a method is provided.

Abstract: Systems, methods, media, and other such embodiments described herein relate to trimming cell lists prior to generation of a routing tree for a circuit design. One embodiment involves accessing a cell library including cell data and a cell list for a plurality of cells. Specialized delay cells are removed from the cell list, and remaining cells are analyzed to identify a set of cell characteristics. Cells are then trimmed from the cell list based on comparisons between the cell characteristics of the remaining cells. If certain cells are sufficiently similar, secondary characteristics can be used to further trim the cell list. The trimmed cell list can then be used to generate a routing tree for the circuit design according to associated design criteria.

Abstract: A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.

Abstract: A method includes receiving an input that is in an electronic file format and that includes information associated with an integrated circuit (IC) layout, selecting a non EM rule compliant metal line of the IC layout that is in violation of an EM rule from the input, obtaining a current of the non EM rule compliant metal line from the input, comparing the current with a threshold current, and determining whether the EM rule violation is negligible based on the result of comparison. As such, a semiconductor device may be fabricated from the IC layout when it is determined that the EM rule violation is negligible.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: Disclosed are methods and apparatus for providing feature classification for inspection of a photolithographic mask. A design database for fabrication of a mask includes polygons that are each defined by a set of vertices. Any of the polygons that abut each other are grouped together. Any grouped polygons are healed so as to eliminate interior edges of each set of grouped polygons to obtain a polygon corresponding to a covering region of such set of grouped polygons. Geometric constraints that specify requirements for detecting a plurality of feature classes are provided and used for detecting a plurality of feature classes in the polygons of the design database. The detected features classes are used to detect defects in the mask.

Abstract: A method of determining a process window for a lithographic process, the process window describing a degree of acceptable variation in at least one processing parameter during the lithographic process. The method includes obtaining a set of output parameter values derived from measurements performed at a plurality of locations on a substrate, following pattern transfer to the substrate using a lithographic process, and obtaining a corresponding set of actual processing parameter values that includes an actual value of a processing parameter of the lithographic process during the pattern transfer at each of the plurality of locations. The process window is determined from the output parameter values and the actual processing parameter values. This process window may be used to improve the selection of the processing parameter at which a subsequent lithographic process is performed.

Abstract: A method for reference image contour generation includes generating a mask pattern based on design target information, generating a reference image based on a simulation of photolithographic effects on the mask pattern, generating a reference image contour pattern based on edge detection in the reference image, and generating a scanned image contour pattern as a function of the reference image contour pattern and a scanned image of an integrated circuit.

Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.

Abstract: The present disclosure provides a method of performing optical proximity correction (OPC). An integrated circuit (IC) design layout is received. The design layout contains a plurality of IC layout patterns. Two or more of the plurality of IC layout patterns are grouped together. The grouped IC layout patterns are dissected, or target points are set for the grouped IC layout patterns. Thereafter, an OPC process is performed based on the grouped IC layout patterns.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: Method for minimization of degradation of images created by the projector tool turns on the optimization of the pattern-imaging by adjusting parameters and hardware of the projector to judiciously impact the placement of various image edges at different locations in the image field. Adjustments to the projector (exposure tool) include a change of a setup parameter of the exposure tool and/or scanning synchronization and/or a change of a signature of the optical system of the exposure tool determined as a result of minimizing the pre-determined cost function(s) that are parts of a comprehensive edge-placement error model.

Abstract: An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.

Abstract: Computer-implemented systems and methods for generating a multiple patterning lithography (MPL) compliant integrated circuit layout are provided. A plurality of integrated circuit (IC) cells are assembled to form an IC layout. The IC layout includes at least two IC cells that abut one another. After the assembling of the IC cells, a decomposition algorithm is executed to assign multiple colors to design shapes within the IC layout. Multiple patterning coloring conflicts are detected in the IC layout after the assigning of the colors to the design shapes. A fixing algorithm is executed, under which a conflict present in two abutting IC cells is fixed by flipping or shifting at least one of the abutting IC cells.

Abstract: Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process.

Abstract: Diffraction models and scatterometry are used to reconstruct a model of a microscopic structure on a substrate. A plurality of candidate structures are defined, each represented by a plurality of parameters (p1, p2, etc.)). A plurality of model diffraction signals are calculated by simulating illumination of each of the candidate structures. The structure is reconstructed by fitting one or more of the model diffraction signals to a signal detected from the structure. In the generation of the candidate structures, a model recipe is used in which parameters are designated as either fixed or variable. Among the variable parameters, certain parameters are constrained to vary together in accordance with certain constraints, such as linear constraints. An optimized set of constraints, and therefore an optimized model recipe, is determined by reference to a user input designating one or more parameters of interest for a measurement, and by simulating the reconstruction process reconstruction.

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

Abstract: Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first pattern positioned adjacent to a second pattern, wherein an OPC modeling rule of the IC design layout prohibits the first pattern from being adjusted, and wherein the second pattern does not reduce a printability metric of the first pattern; adjusting the design of the second pattern to reduce at least one printing error in the first pattern, wherein a functionality of the second pattern in the IC design layout is unchanged after the adjusting; and implementing OPC on the IC design layout including the target region with the adjusted second pattern therein.

Abstract: A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied.

Abstract: A method for wafer point by point analysis includes receiving first recipe parameters for a first process recipe, second recipe parameters for a second process recipe, a first plurality of measurements of a plurality of locations on a first wafer processed using the first process recipe, and a second plurality of measurements of the plurality of locations on a second wafer processed using the second process recipe. A plurality of sensitivity values are calculated using the first and second values for the plurality of recipe parameters and the first and second plurality of measurements, each of the plurality of sensitivity values corresponding to one of the plurality of locations and representing a sensitivity to one of the plurality of recipe parameters. A graphical representation of a wafer is then provided that shows at least a subset of the first plurality of sensitivity values for the plurality of locations.

Abstract: Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.

Abstract: A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.

Abstract: A restricted region transform method and a restricted region transform device are disclosed. The method includes following steps: reading out bare board information of a printed circuit board and layout information of a plurality of components, wherein the layout information of the plurality of components corresponds to a plurality of physical restricted regions; setting a first region according to edge information in the bare board information; setting a plurality of second regions according to projections of the plurality of physical restricted regions on a surface of the printed circuit board; selecting every two second regions, which overlap each other, among the plurality of second regions, and the selected second regions constituting a restriction conflict set; and selectively amending the second regions in the restriction conflict set to remove one or more overlaps from the second regions in the restriction conflict set.

Abstract: Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations.

Abstract: Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate certain layout instances or “cell views” as “transparent.” The instances are indicated as transparent using various layout editor commands or layout designer markers. Unlike conventional solutions, a binder within the layout editor of the EDA is not required to bind layout transparent instances to corresponding instances in a related schematic design file or records. Instead, the EDA may identify non-transparent instances at a lower-level of the layout design's hierarchy to bind, because the systems and methods described herein provide for a transparent instance container at a hierarchically higher-level.

Abstract: A measurement target for a semiconductor device is designed. The semiconductor device includes a structure to be measured that has a spectrum response that is comparable to or below system noise level for an optical critical dimension measurement device to be used to measure the structure. The measurement target is designed by obtaining a process window and design rules for the semiconductor device and determining prospective pitches through modeling to identify pitches that produce a spectrum response from the structures that is at least 10 times greater than a system noise level for the optical critical dimension measurement device. A resonance window for each prospective pitch is determined and robustness of the resonance window is determined through modeling. Pitches of the array are selected based on the prospective pitches, resonance windows, and robustness. The target design may accordingly be produced and used to generate a measurement target.

Abstract: Various aspects of the disclosed technology relate to techniques of retargeting layout features. A process window simulation on a layout design is performed to generate process window information that comprises predicted print positions of layout features computed under various process conditions. Retargeted print positions for a plurality of edge fragments in the layout design are then determined based on minimizing a combined change of targeted print positions for the plurality of edge fragments under constraints represented based on the process window information and specification limits for printed layout features. Based on the retargeted print positions, positions of the plurality of edge fragments are adjusted for optical proximity correction.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

Abstract: A process for the manufacture of custom freeform optical elements utilizing parameterized modelling. A system for the automatic manufacture of a custom optical element is also described with the manufacturing being by laser micro-machining. The process and system allow customers to specify and order via a web interface and so reduce engineering time, overhead and cost.

Abstract: A computer-implemented method for validating a design is disclosed. The method includes receiving, with the computer, the design, where the design is printable using a multiple-patterning process when the computer is invoked, and where the design includes a plurality of shapes and at least one conflict preventing decomposition of the design into a plurality of multiple-patterning masks. The method also includes forming a subset of the shapes, the subset including the shapes associated with the at least one conflict, categorizing each of the shapes of the subset into one of a plurality of topology types generating one or more stitch candidate solutions for each of the plurality of topology types, and decomposing the design into a plurality of masks.

Abstract: In one embodiment, a data generating apparatus generates data including an irradiation amount of a beam in each pixel for an energy beam writing apparatus. The data generating apparatus includes a target irradiation amount calculating section configured to calculate a first irradiation amount in each pixel, an irradiation amount rounding section configured to round the first irradiation amount based on an irradiation amount control unit and calculate a second irradiation amount, a difference calculating section configured to calculate a first difference between the first irradiation amount and the second irradiation amount, a difference sum calculating section configured to calculate a sum of the first differences in a first group of a plurality of adjacent pixels, and an allocating section configured to allocate an irradiation amount based on the irradiation amount control unit and the sum to a pixel in the first group.

Abstract: Improving semiconductor device fabrication by enabling the identification and modeling of pattern dependent effects of fabrication processes is discussed. In one embodiment a local mask is generated from a 3-D model of a semiconductor device structure that was created in a 3-D virtual semiconductor fabrication environment from 2-D design layout data and a fabrication process sequence. The local mask is combined with a global mask based on the original design layout data to create a combined mask. The combined mask is convolved with at least one proximity function to generate a loading map which may be used to modify the behavior of one or more processes in the process sequence. This behavior modification enables the 3-D virtual semiconductor fabrication environment to deliver more accurate 3-D models that better predict the 3-D device structure when performing the virtual semiconductor device fabrication that serves as a prelude to physical fabrication.

Abstract: A circuit layout data has a start value of a first-axis pitch and a start value of a second-axis pitch, the second axis pitch being transverse to the first-axis pitch. The start value of the first axis pitch and the start value of the second axis pitch correspond to single pattern lithography. The first axis pitch is scaled to a first axis single pattern-to-double pattern pitch transition threshold, and then additionally scaled until reaching a first axis double pattern resolution limit. Scaling the first axis pitch to the first axis double pattern resolution limit utilizes routing spaces parallel to the second axis pitch.

Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.

Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: A system includes a critical signature library for storing critical signature databases of chip design layouts in semiconductor manufacturing and a statistical model creator for creating statistical models based on the known problematic circuit patterns stored in the critical signature databases and a target specification based on deviation between physical measurement and simulation data or design data associated with the known problematic circuit patterns. The system further has a statistical model based predictor for predicting and discovering unknown problematic circuit patterns by applying the statistical models to a large number of candidate circuit patterns generated from a random layout generator, or extracted from the chip design layout based on hot spot sites determined by extended lithographic process check on the chip design layout or inspecting wafers manufactured with the chip design layout with an aggressive sensitivity setting.