Optical Proximity Correction (including Ret) Patents (Class 716/53)
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Patent number: 8806389Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.Type: GrantFiled: October 19, 2012Date of Patent: August 12, 2014Assignee: ASML Netherlands B.V.Inventors: Taihui Liu, Been-Der Chen, Yen-Wen Lu
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Patent number: 8806388Abstract: A method of computational lithography includes collecting a critical dimension (CD) data set including CD data from printing a test structure including a set of gratings which provide a plurality of feature types including different ratios of line width to space width, where the printing includes a range of different focus values. The CD data is weighted to form a weighted CD data set using a weighting algorithm (WA) that assigns cost weights to the CD data based its feature type and its magnitude of CD variation with respect to a CD value for its feature type at a nominal focus (nominal CD). The WA algorithm reduces a value of the cost weight as the magnitude of variation increases. At least one imaging parameter is extracted from the weighted CD data set. A computational lithography model is automatically calibrated using the imaging parameter(s).Type: GrantFiled: March 22, 2013Date of Patent: August 12, 2014Assignee: Texas Instruments IncorporatedInventor: Ashesh Parikh
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Patent number: 8806387Abstract: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.Type: GrantFiled: May 29, 2009Date of Patent: August 12, 2014Assignee: ASML Netherlands B.V.Inventors: Yu Cao, Wenjin Shao, Ronaldus Johannes Gijsbertus Goossens, Jun Ye, James Patrick Koonmen
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Patent number: 8806391Abstract: A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask.Type: GrantFiled: July 31, 2012Date of Patent: August 12, 2014Assignee: United Microelectronics Corp.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Shih-Ming Kuo, Jing-Yi Lee
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Patent number: 8806390Abstract: An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edge segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments are assigned a priority such that the correction of a lower priority edge does not hinder a desired OPC correction of a higher priority edge.Type: GrantFiled: December 17, 2010Date of Patent: August 12, 2014Assignee: Mentor Graphics CorporationInventor: George P. Lippincott
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Patent number: 8806396Abstract: Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).Type: GrantFiled: June 23, 2009Date of Patent: August 12, 2014Assignee: Cadence Design Systems, Inc.Inventors: Ming Liu, JenPin Weng, Taber Smith
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Patent number: 8806394Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).Type: GrantFiled: October 4, 2013Date of Patent: August 12, 2014Assignee: ASML Netherlands B.V.Inventors: Hanying Feng, Yu Cao, Jun Ye
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Publication number: 20140223393Abstract: A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.Type: ApplicationFiled: December 13, 2013Publication date: August 7, 2014Applicant: D2S, Inc.Inventors: Akira Fujimura, Kazuyuki Hagiwara, Stephen F. Meier, Ingo Bork
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Publication number: 20140220786Abstract: A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.Type: ApplicationFiled: February 1, 2013Publication date: August 7, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Todd Lukanc, Christopher Heinz Clifford, Tamer Coskun
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Publication number: 20140223392Abstract: An approach for providing a fragmentation scheme for lithographic fills is provided. In a typical embodiment, a plurality of shapes in a lithographic (e.g., dummy) fill will be grouped/classified into a first set of shapes (e.g., a representative set of shapes) and a second set of shapes (e.g., a similar set of shapes). A set of points will be identified along the edges of the first set of shapes (e.g., at corners of the edges and at positions along the edges that are in alignment with corners of adjacent shapes) to yield an initial mask output. This initial mask output will be copied to the second set of shapes to yield a final mask output which may then be outputted using such an optimized fragmentation scheme.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Pavan Bashaboina, Sarah McGowan
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Patent number: 8799832Abstract: Aspects of the invention relate to techniques of optical simulation for topographically non-uniform substrates. A layout design is simulated to generate an aerial image based on optical models for different types of substrates and for transition regions, along with models for one or more categories of light signals. The one or more categories of light signals comprise trench side-wall reflection signals, trench radiation signals, and trench corner diffraction signals. The one or more categories of light signals may further comprise gate scattering signals and interconnect scattering signals. The models for the one or more categories of light signals may be calibrated with experimental data.Type: GrantFiled: February 8, 2013Date of Patent: August 5, 2014Assignee: Mentor Graphics CorporationInventors: Yuri Granik, Uwe Hollerbach, Konstantinos Adam
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Patent number: 8799833Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.Type: GrantFiled: March 9, 2012Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh
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Patent number: 8799834Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. The initial design layout comprises a first pattern, such as a mandrel pattern, and a second pattern, such as a passive fill pattern. An initial cut pattern is generated for the initial design layout. Responsive to identifying a design rule violation associated with the initial cut pattern, the initial design layout is modified to generate a modified initial design layout. An updated cut pattern, not resulting in the design rule violation, is generated based upon the modified initial design layout. The updated cut pattern is applied to the modified initial design layout to generate a final design layout. The final design layout can be verified as self-aligned multiple patterning (SAMP) compliant.Type: GrantFiled: January 30, 2013Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Huang-Yu Chen, Li-Chun Tien, Ken-Hsien Hsieh, Jhih-Jian Wang, Chin-Chang Hsu, Chin-Hsiung Hsu, Pin-Dai Sue, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20140215417Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.Type: ApplicationFiled: April 1, 2014Publication date: July 31, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Howard S. LANDIS
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Publication number: 20140215416Abstract: Aspects of the invention relate to techniques for integrating optical proximity correction and mask data preparation. First mask writer instructions for a layout design are simulated to generate a mask contour. Based on the generated mask contour, first layout data for the layout design are adjusted for optical proximity correction to generate second layout data. Using the generated second layout data as mask target, the first mask writer instructions are adjusted to generate second mask writer instructions. The above process may be iterated until an end condition is met.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: MENTOR GRAPHICS CORPORATIONInventor: Emile Y. Sahouria
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Publication number: 20140215415Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Lynn WANG, Vito Dai, Luigi Capodieci
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Patent number: 8792147Abstract: A method of determining calibration test patterns to be utilized to calibrate a model for simulating the imaging performance of an optical imaging system. The method includes the steps of defining a model equation representing the imaging performance of the optical imaging system; transforming the model equation into a plurality of discrete functions; identifying a calibration pattern for each of the plurality of discrete functions, where each calibration pattern corresponding to one of the plurality of discrete functions being operative for manipulating the one of the plurality of discrete functions during a calibration process; and storing the calibration test patterns identified as corresponding to the plurality of discrete functions. The calibration test patterns are then utilized to calibrate the model for simulating the imaging performance of an optical imaging system.Type: GrantFiled: August 14, 2007Date of Patent: July 29, 2014Assignee: ASML Netherlands B.V.Inventor: Edita Tejnil
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Publication number: 20140208278Abstract: The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.Type: ApplicationFiled: April 7, 2014Publication date: July 24, 2014Applicant: ASML NETHERLANDS B.V.Inventors: Yu CAO, Wenjin SHAO, Jun YE, Ronaldus Johannes Gljsbertus GOOSSENS
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Patent number: 8788981Abstract: In a method and apparatus for quantitatively evaluating two-dimensional patterns, a reference coordinate system is set in order to convert pattern edge information (one-dimensional data) acquired by measurement using an existing critical dimension machine into coordinate data. Thus, a pattern is converted into coordinate information. Next, a function formula is determined from this coordinate information by approximate calculation and a pattern is represented by the mathematical expression y=f(x). Integrating y=f(x) in the reference coordinate used when calculating the coordinate data gives the area of the pattern, whereby it is possible to convert the coordinate data to two-dimensional data.Type: GrantFiled: April 3, 2008Date of Patent: July 22, 2014Assignee: Hitachi High-Technologies CorporationInventors: Mihoko Kijima, Kyoungmo Yang, Shigeki Sukegawa, Takumichi Sutani
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Patent number: 8788983Abstract: A method for correcting layout pattern and a mask having the corrected layout pattern thereon are provided. In an exemplary method, a first layout pattern including a plurality of first hole patterns can be provided to form an auxiliary pattern in each first hole pattern and to obtain a second layout pattern. The auxiliary pattern can have a dimension smaller than an exposure resolution in a photolithography process. The second layout pattern can then be processed by an optical proximity correction (OPC) to obtain a first modified layout pattern. The first modified layout pattern can include a plurality of modified first hole patterns modified by the OPC. The first modified layout pattern can be simulated to obtain an actual layout pattern such that the actual layout pattern and the first layout pattern have an edge placement error (EPE) within a predetermined range.Type: GrantFiled: March 18, 2013Date of Patent: July 22, 2014Assignee: Semiconductor Manufacturing International CorpInventor: Jasmine Zhang
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Patent number: 8788982Abstract: Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, transition and visible portions. An inverse lithography process is then performed on the core and transition portions of the re-correction region while taking into account effects from the visible portion to generate a modified re-correction region. The transition portion is processed based on distance from boundary between the transition portion and the core portion such that layout features near the boundary between the transition portion and the core portion are adjusted more than layout features farther away from the boundary.Type: GrantFiled: January 14, 2013Date of Patent: July 22, 2014Assignee: Mentor Graphics CorporationInventors: George Lippincott, Yuri Granik, Sergey Kobelkov
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Patent number: 8782569Abstract: An inspection method for a photo-mask in a semiconductor process is provided. First, a first photo-mask with a first wafer anchor point (1st wafer FAM) is provided. Then, Dmax and Dmin are calculated according to the 1st wafer FAM. A second photo-mask and a second mask anchor point (2nd mask FAM) of the second photo-mask are provided. A CD average, and a CD range of the second photo-mask are measured. Finally, the second photo-mask is inspected by using equation A and/or equation B: CD average?2nd mask FAM<Dmax?CD range/2??(equation A) 2nd mask FAM?CD average<Dmin?CD range/2??(equation B).Type: GrantFiled: March 14, 2013Date of Patent: July 15, 2014Assignee: United Microelectronics Corp.Inventors: Chain-Ting Huang, Yung-Feng Cheng, Ming-Jui Chen
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Patent number: 8782572Abstract: A method of optical proximity correction (OPC) includes the following steps. First, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into a first sub-layout pattern and a second sub-layout pattern. Then, an OPC calculation based on a first OPC model is performed on the first sub-layout pattern so as to form a corrected first sub-layout pattern and an OPC calculation based on a second OPC model is performed on the second sub-layout pattern so as to form a corrected second sub-layout pattern. Afterward, the corrected first sub-layout pattern and the corrected second sub-layout pattern are output from the computer system into a photomask.Type: GrantFiled: March 13, 2013Date of Patent: July 15, 2014Assignee: United Microelectronics Corp.Inventors: Sheng-Yuan Huang, Chia-Wei Huang, Ming-Jui Chen
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Patent number: 8782571Abstract: One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.Type: GrantFiled: March 8, 2012Date of Patent: July 15, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuyang Sun, Norman S. Chen, Jian Liu
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Patent number: 8775983Abstract: Some embodiments of the invention provide a method for identifying and displaying odd loops and hints for resolution of the odd loops in an IC design layout for printing on multiple masks. The method of some embodiments identifies the hints by evaluating the effectiveness and feasibility of different potential resolutions, ensuring that hints do not create additional odd loops. The method of some embodiments also displays indications of the odd loops and the hints which a user can use to troubleshoot an odd loop violation. The method of some embodiments also prioritizes or scores the resolution hints to facilitate efficient troubleshooting of odd loop violations.Type: GrantFiled: December 21, 2012Date of Patent: July 8, 2014Assignee: Cadence Design Systems, Inc.Inventor: Xiaojun Wang
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Patent number: 8775978Abstract: A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with greater fidelity by an illumination pattern used in the multiple exposure printing system.Type: GrantFiled: June 14, 2011Date of Patent: July 8, 2014Assignee: Mentor Graphics CorporationInventor: Jea-Woo Park
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Patent number: 8775981Abstract: A method includes receiving a layout file for a reticle used to pattern a first die location in a computing apparatus, the layout file defining a plurality of kerf features. A flare map calculation area for the first die location covering at least a portion of a kerf region surrounding the first die location is defined in the computing apparatus. Features in the layout file into the region corresponding to the flare map calculation area that are associated with the patterning of die locations neighboring the first die location are copied in the computing apparatus to generate a modified layout file. A flare map of the portion of the kerf region included in the flare map calculation area based on the modified layout file is calculated in the computing apparatus.Type: GrantFiled: February 19, 2013Date of Patent: July 8, 2014Assignee: GLOBALFOUNDRIES Inc.Inventor: Christopher H. Clifford
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Patent number: 8771906Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, in which the union of shots from one of a plurality of exposure passes is different than the union of shots from a different exposure pass. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, in which the union of shots from one of a plurality of charged particle beam exposure passes is different than the union of shots from a different exposure pass.Type: GrantFiled: July 22, 2013Date of Patent: July 8, 2014Assignee: D2S, Inc.Inventors: Harold Robert Zable, Akira Fujimura
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Patent number: 8775982Abstract: The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.Type: GrantFiled: June 25, 2013Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mei-Hsuan Lin, Chih-Chan Lu, Chih-Hsun Lin, Chih-Kang Chao, Ling-Sung Wang, Jen-Pan Wang
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Publication number: 20140189614Abstract: A method comprises: (a) transforming a layout of a layer of an integrated circuit (IC) or micro electro-mechanical system (MEMS) to a curvilinear mask layout; (b) replacing at least one pattern of the curvilinear mask layout with a previously stored fracturing template having approximately the same shape as the pattern, to form a fractured IC or MEMS layout; and (c) storing, in a non-transitory storage medium, an e-beam generation file including a representation of the fractured IC or MEMS layout, to be used for fabricating a photomask.Type: ApplicationFiled: January 2, 2013Publication date: July 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Gun LIU, Wen-Hao CHENG, Chih-Chiang TU, Shuo-Yen CHOU
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Patent number: 8769445Abstract: A method and system arrangement for controlling and determining mask operation activities. Upon obtaining chip physical layout design data and running resolution enhancement technology on the chip physical layout design to generate mask features which may include any sub-resolution assist features, a placement sensitivity metric is determined for each of the generated mask features or edge fragments. In one alternative embodiment an edge placement sensitivity metric is determined for each edge of the generated mask features or edge fragments. The determined sensitivity metrics for each feature are classified and applied to subsequent mask operational activities such as post processing, write exposure and mask repair.Type: GrantFiled: September 22, 2010Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Emily E. Gallagher, Jed H. Rankin, Alan E. Rosenbluth
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Patent number: 8762901Abstract: A method for process proximity correction may include obtaining a point spread function (PSF) from test patterns, the test patterns including an etching process performed thereon, generating a target layout with polygonal patterns, dividing the target layout into grid cells, generating a density map including long-range layout densities, each of the long-range layout densities being obtained from the polygonal patterns located within a corresponding one of the grid cells, performing a convolution of the long-range layout densities with the PSF to obtain long-range etch skews for the grid cells, and generating an etch bias model including short-range etch skews and the long-range etch skews, each of the short-range etch skews being obtained from a neighboring region of a target pattern selected from the polygonal patterns in each of the grid cells.Type: GrantFiled: September 25, 2012Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: WonChan Lee, Seong-Bo Shim, Sunghoon Jang, Gun Huh
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Patent number: 8762899Abstract: A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask.Type: GrantFiled: January 16, 2013Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Burn Jeng Lin, Tsai-Sheng Gau, Ru-Gun Liu, Wen-Chun Huang
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Patent number: 8762900Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.Type: GrantFiled: June 27, 2012Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jaw-Jung Shin, Shy-Jay Lin, Hua-Tai Lin, Burn Jeng Lin
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Patent number: 8759799Abstract: A charged particle beam writing apparatus according to an embodiment, includes a dose coefficient calculation unit to calculate an n-th dose correction coefficient in iterative calculation of a charged particle beam to be shot in a small region concerned by the iterative calculation, for each small region of small regions made by virtually dividing into mesh-like regions, a change rate calculation unit to calculate, for each small region, a rate of change from an (n-1)th dose correction coefficient to the n-th dose correction coefficient calculated in the iterative calculation, as an n-th change rate, a correction calculation unit to correct, for each small region, the n-th dose correction coefficient by using the n-th change rate, and a dose calculation unit to calculate, for each small region, a dose of a charged particle beam to be shot in a small region concerned by using the n-th dose correction coefficient corrected.Type: GrantFiled: November 6, 2012Date of Patent: June 24, 2014Assignee: NuFlare Technology, Inc.Inventor: Hironobu Matsumoto
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Patent number: 8756550Abstract: An integrated circuit with standard cells with top and bottom metal-1 and metal-2 power rails and with lateral standard cell borders that lie between an outermost vertical dummy poly lead from one standard cell and an adjacent standard cell. A DPT compatible standard cell design rule set. A method of forming an integrated circuit with standard cells constructed using a DPT compatible standard cell design rule set. A method of forming DPT compatible standard cells.Type: GrantFiled: September 19, 2012Date of Patent: June 17, 2014Assignee: Texas Instruments IncorporatedInventor: James Walter Blatchford
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Patent number: 8756536Abstract: The present invention provides a generation method of generating data for a mask pattern to be used for an exposure apparatus including a projection optical system for projecting a mask pattern including a main pattern and auxiliary pattern onto a substrate, including a step of setting a generation condition under which the auxiliary pattern is generated, and a step of determining whether a value of an evaluation function describing an index which indicates a quality of an image of the mask pattern calculated, wherein if it is determined that the value of the evaluation function falls outside a tolerance range, the generation condition is changed to set a new generation condition.Type: GrantFiled: March 1, 2013Date of Patent: June 17, 2014Assignee: Canon Kabushiki KaishaInventor: Tadashi Arai
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Patent number: 8751978Abstract: Among other things, one or more techniques for balancing mask loading are provided herein. In some embodiments, a dummy mask assignment is assigned to a dummy within a mask layout based on an area of a polygon within the mask layout. In some embodiments, the dummy mask comprising the dummy mask assignment is inserted in the mask layout. In some embodiments, a window is created such that dummies within the window receive dummy mask assignments. In some embodiments, a halo is created such that the area of the polygon is determined based on the halo. Additionally, in some examples, the window and halo are shifted around the mask layout. In this manner, balanced mask loading is provided, thus enhancing a yield associated with the mask layout, for example.Type: GrantFiled: October 19, 2012Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: HungLung Lin, Chin-Chang Hsu, Wen-Ju Yang, C. R. Hsu
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Patent number: 8751976Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.Type: GrantFiled: June 27, 2012Date of Patent: June 10, 2014Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8751975Abstract: A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.Type: GrantFiled: May 23, 2012Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8745550Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.Type: GrantFiled: July 9, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nian-Fuh Cheng, Yu-Po Tang, Chien-Fu Lee, Sheng-Wen Lin, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8741507Abstract: A method for separating photomask pattern, including the following steps: first, a layout pattern is provided, wherein the layout pattern is defined to have at least one critical pattern and at least one non-critical pattern. Then, a first split process is performed to separate the critical pattern into a plurality of first patterns and a plurality of second patterns. A second split process is performed to separate the non-critical pattern into a plurality of third patterns and a plurality of fourth patterns. Finally, the first patterns and the third patterns are output to a first photomask, and the second patterns and the fourth patterns are output to a second photomask.Type: GrantFiled: January 16, 2013Date of Patent: June 3, 2014Assignee: United Microelectronics Corp.Inventors: Chun-Hsien Huang, Ming-Jui Chen, Chia-Wei Huang, Ting-Cheng Tseng
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Patent number: 8745549Abstract: A method for fracturing or mask data preparation or proximity effect correction or optical proximity correction or mask process correction is disclosed in which a set of charged particle beam shots is determined that is capable of forming a pattern on a surface, wherein critical dimension (CD) split is reduced through the use of overlapping shots.Type: GrantFiled: February 5, 2012Date of Patent: June 3, 2014Assignee: D2S, Inc.Inventors: Akira Fujimura, Robert C. Pack
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Patent number: 8745556Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.Type: GrantFiled: June 28, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Tsong-Hua Ou, Ken-Hsien Hsieh, Chin-Hsiung Hsu
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Patent number: 8745545Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.Type: GrantFiled: September 25, 2013Date of Patent: June 3, 2014Assignee: Micron Technology, Inc.Inventors: Ming-Chuan Yang, Jung H. Woo
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Patent number: 8739078Abstract: Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.Type: GrantFiled: January 18, 2012Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventor: Howard S. Landis
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Patent number: 8739080Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.Type: GrantFiled: October 4, 2012Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8739076Abstract: A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the photolithographic process. Critical dimension data of the photolithographic process are predicted at a second process combination of a second dose and a second defocus in the photolithographic process.Type: GrantFiled: September 11, 2012Date of Patent: May 27, 2014Assignee: Synopsys, Inc.Inventor: Artak Isoyan
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Patent number: 8739077Abstract: Methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, and methods for fabricating an integrated circuit, are provided. In an embodiment, a method includes providing a circuit design layout that has a plurality of element patterns. A first library of problematic sections is provided. An initial circuit section and an additional circuit section within the circuit design layout are determined to match problematic sections in the first library, and the initial and additional circuit sections have overlapping peripheral boundaries. A second library of replacement sections is provided. The replacement sections correspond to the problematic sections. The circuit sections that match the problematic sections are replaced with a replacement section that corresponds to the respective problematic sections to form the final circuit layout. Boundary characteristics of the replacement sections are substantially the same as the circuit sections replaced thereby.Type: GrantFiled: March 1, 2013Date of Patent: May 27, 2014Assignee: Globalfoundries, Inc.Inventors: Piyush Pathak, Piyush Verma, Sarah N. McGowan
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Patent number: 8739075Abstract: A method of making pattern data of a photomask pattern includes: the processes of adding, to each of first cells, information of the first cell higher than the first cell on the basis of a hierarchical structure; selecting, from the first cells included in one level of the hierarchical structure, the first cell identical to one of the first cells included in a level higher than the one level and the first cell placed inside two or more of the first cells included in a level immediately higher than the one level, and forming a cell group with the selected first cells; making pattern data of the first cells not included in the cell group in consideration of the optical proximity effect and forming a fourth cell group with second cells including the pattern data; and replacing the first cells with the corresponding second cells in input data.Type: GrantFiled: March 17, 2009Date of Patent: May 27, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Muneto Saito, Koichi Suzuki, Mitsuo Sakurai, Norimasa Nagase