Abstract: The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.

Abstract: A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask.

Abstract: A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.

Abstract: A method for decomposing a target circuit pattern containing features to be imaged into multiple patterns. The process includes the steps of separating the features to be printed into a first pattern and a second pattern; performing a first optical proximity correction process on the first pattern and the second pattern; determining an imaging performance of the first pattern and the second pattern; determining a first error between the first pattern and the imaging performance of the first pattern, and a second error between the second pattern and the imaging performance of said second pattern; utilizing the first error to adjust the first pattern to generate a modified first pattern; utilizing the second error to adjust the second pattern to generate a modified second pattern; and applying a second optical proximity correction process to the modified first pattern and the modified second pattern.

Abstract: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design.

Abstract: Numerical calculation of electromagnetic scattering properties and structural parameters of periodic structures is disclosed. A reflection coefficient has a representation as a bilinear or sesquilinear form. Computations of reflection coefficients and their derivatives for a single outgoing direction can benefit from an adjoint-state variable. Because the linear operator is identical for all angles of incidence that contribute to the same outgoing wave direction, there exists a single adjoint-state variable that generates all reflection coefficients from all incident waves that contribute to the outgoing wave. This adjoint-state variable can be obtained by numerically solving a single linear system, whereas one otherwise would need to solve a number of linear systems equal to the number of angles of incidence.

Abstract: A method of manufacturing a semiconductor device is provided which includes forming a target layout; producing a skewed layout that includes retargeting the target layout; detecting an envelope of the skewed layout; generating a jog-free layout according to the detected envelope; fragmenting the jog-free layout; acquiring a layout that converges towards the skewed layout by performing an optical proximity correction on the fragmented jog-free layout; and patterning a material for forming the semiconductor device using the acquired layout.

Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.

Abstract: A method for manufacturing a semiconductor device is disclosed, wherein during the physical design process, a curvilinear path is designed to represent an interconnecting wire on the fabricated semiconductor device. A method for fracturing or mask data preparation (MDP) is also disclosed in which a manhattan path which is part of the physical design of an integrated circuit is modified to create a curvilinear pattern, and where a set of charged particle beam shots is generated, where the set of shots is capable of forming the curvilinear pattern on a resist-coated surface.

Abstract: There is provided a computer-implemented method of creating a recipe for a manufacturing tool and a system thereof. The method comprises: upon obtaining data characterizing periodical sub-arrays in one or more dies, generating candidate stitches; identifying one or more candidate stitches characterized by periodicity characteristics satisfying, at least, a periodicity criterion, thereby identifying periodical stitches among the candidate stitches; and aggregating the identified periodical stitches and the periodical sub-arrays into periodical arrays, said periodical arrays to be used for automated recipe creation.

Abstract: A method of generating complementary masks for use in a dark field double dipole imaging process. The method includes the steps of identifying a target pattern having a plurality of features, including horizontal and vertical features; generating a horizontal mask based on the target pattern, where the horizontal mask includes low contrast vertical features. The generation of the horizontal mask includes the steps of optimizing the bias of the low contrast vertical features contained in the horizontal mask; and applying assist features to the horizontal mask. The method further includes generating a vertical mask based on the target pattern, where the vertical mask contains low contrast horizontal features. The generation of the vertical mask includes the steps of optimizing the bias of low contrast horizontal features contained in the vertical mask; and applying assist features to the vertical mask.

Abstract: A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout is displayed.

Abstract: Branching of the data-flow in a mask data preparation processes is described herein. In various implementations, the output stream from a first mask data processing operation is branched. Subsequently, the branched output stream may be connected to the input stream of a first independent mask data preparation operation and a second independent mask data preparation operation. This provides that the first and the second independent mask data preparation operations may operate in parallel. Furthermore, this provides that the first and the second independent mask data preparation operations may operate upon discrete “portions” of the data processed by the first mask data preparation operation.

Abstract: Obtaining a function by convoluting a function representing a light intensity distribution formed by an illumination apparatus on a pupil plane of a projection optical system and a pupil function of the projection optical system. Calculating a Fourier transformed function by Fourier transforming the product of the obtained function and a diffracted light distribution from a pattern on an object plane of the projection optical system. Producing data of the pattern of the mask based on the Fourier transformed function.

Abstract: A target pattern is provided including a first pattern in a first region. A sensor pattern is inserted in the target pattern in the first region. A flare intensity of the sensor pattern in the first region is determined. A pattern bias is determined based on the flare intensity.

Abstract: A method may be for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set may include first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method may include a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region.

Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points. The method further includes reassigning the target points to the segments of the pattern based on the first simulated contour of the pattern; producing a second simulated contour of the pattern based on the reassigned target points, and after producing the second simulated contour of the pattern, producing a modified IC design layout.

Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.

Abstract: Various embodiments of the present invention relate to particle beam writing to fabricate an integrated circuit on a wafer. In various embodiments, cell projection (CP) cell library information is stored in the form of a data structure. Subsequently, the CP cell library information is referenced by a writing system. The patterns are written on the wafer depending on the referenced CP cell library.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a plurality of IC regions each including an IC pattern; performing a dissection process to the IC design layout; and performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect. The correction process includes performing a first correction step to a first IC region of the IC regions, resulting in a first corrected IC pattern in the first IC region; and performing a second correction step to a second IC region of the IC regions, starting with the first corrected IC pattern, resulting in a second corrected IC pattern.

Abstract: Methods for integrated electronic and photonic design include laying out electronic and photonic design components in a design environment; adjusting photonic components according to photonic design requirements using a processor; checking design rules for electronic and photonic components according to manufacturing requirements; and adjusting component positioning and size to reconcile conflicts between electronic and photonic components.

Abstract: A method for making a photomask layout is provided. A first graphic data of a photomask is provided, wherein the first graphic data includes a first line with a first line end target, a second line with a second line end target and a hole, the first line is aligned with the second line, and the first line, the second line and the hole partially overlap with each other. Thereafter, a retarget step is performed to the first graphic data to obtain a second graphic data, wherein the retarget step includes moving the first line end target and the second line end target in opposite directions away from each other.

Abstract: A mask blank is provided by forming a plurality of films, including at least a thin film to be a transfer pattern, on a board. At the time of patterning a resist film of the mask blank according to pattern data, film information to check with a pattern is obtained for each of a plurality of the films.

Abstract: A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.

Abstract: Methods and systems for designing a binary spatial filter based on data indicative of a desired exposure condition to be emulated by an inspection system, and for implementing the binary spatial filter in an optical path of the inspection system, thereby enabling emulation of the desired exposure condition by interacting a light beam of the inspection system with the binary spatial filter. The present method and systems enable on-the-fly and on-demand design and implementation/generation of spatial filters for use in inspection systems.

Abstract: In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.

Abstract: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps.

Abstract: A method of electron beam lithography for producing wafers and masks. To reduce the impacts of the disturbing proximity effect, an expanded correction algorithm that enables a more accurate correction is used to control the electron beam. To create an improved correction method by means of which the contrast and the feature width (CD) of all figures of a pattern can be optimally controlled additional contrast frames (KR) and remaining figures (R) are produced using a geometric method for the purpose of contrast control with respect to all figures (F). Then smaller figures (KRsize-S and Rsize-S) are produced from the contrast frame figures (KR) and remaining figures (R) by means of a negative sizing operation, and subsequently figures (KRsize-S and Rsize-S) are transferred to the proximity correction algorithm with the condition that the resist threshold is reached at the edges of the figures (KR, R) by the dose assignment.

Abstract: A method and system for optical proximity correction or fracturing or mask data preparation or mask process correction or proximity effect correction for charged particle beam lithography are disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on the surface, where the set of shots includes shots for a plurality of exposure passes, and where the determination of the shots includes increasing the dose margin of the pattern by adding a shot in a single exposure pass.

Abstract: A method for fracturing or mask data preparation for shaped beam charged particle beam lithography is disclosed, in which a square or nearly-square contact or via pattern is input, and a set of charged particle beam shots is determined which will form a circular or nearly-circular pattern on a surface, where the area of the circular or nearly-circular pattern is within a pre-determined tolerance of the area of the input square or nearly-square contact or via pattern. Methods for forming a pattern on a surface and for manufacturing a semiconductor device are also disclosed.

Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Abstract: Methods, computer program products and apparatuses for optimizing design rules for producing a mask are disclosed, while keeping the optical conditions (including but not limited to illumination shape, projection optics numerical aperture (NA) etc.) fixed. A cross-correlation function is created by multiplying the diffraction order functions of the mask patterns with the eigenfunctions from singular value decomposition (SVD) of a TCC matrix. The diffraction order functions are calculated for the original design rule set, i.e., using the unperturbed condition. ILS is calculated at an edge of a calculated image of a critical polygon using the cross-correlation results and using translation properties of a Fourier transform. The use of the calculated cross-correlation of the mask and the optical system, and the translation property of the Fourier transform for perturbing the design reduces the computation time needed for determining required changes in the design rules.

Abstract: A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An example of such a rule of correction is to elongate at least one of the two neighbors. The computer may perform optical rule checking (ORC) in any order relative to application of the rules, e.g. ORC can be performed between detection rules and correction rules i.e. performed individually on each identified region prior to correction.

Abstract: Techniques for model calibration and alignment of measurement contours of printed layout features with simulation contours obtained with a model are disclosed. With various implementations of the invention, contour point errors are determined. Based on the contour point errors and a cost function, values of alignment parameters may be determined. The values of alignment parameters may be used to realign the measurement contours for model calibration. The alignment may be conducted concurrently with model calibration.

Abstract: A system and method for modifying an integrated circuit (IC) layout includes performing a correction process, such as an optical proximity correction (OPC) process, only on regions within designated blocks that are defined around respective modified structures. An IC layout can be compared to a modified version of the IC layout to detect modified structures. One or more large blocks can then be defined around respective modified structures. A correction process can then be performed on only the one or more large blocks. Small blocks within respective large blocks can then be extracted from the modified IC layout and merged with the original IC layout to generate a final modified and corrected IC layout.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points. The method further includes reassigning the target points to the segments of the pattern based on the first simulated contour of the pattern; producing a second simulated contour of the pattern based on the reassigned target points, and after producing the second simulated contour of the pattern, producing a modified IC design layout.

Abstract: Provided is a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.

Abstract: In one embodiment, a spacing is determined for each edge of a number of features in a photolithographic design. The edges have at least a partially predictable layout. Based on the spacing and the predictable layout, a bridge structure is generated. Each bridge of the bridge structure connects one of the edges to an edge of a neighboring feature. Then, the features and the bridge structure are provided for a phase assignment. The phase assignment assigns features at opposite ends of each bridge in the bridge structure to opposite phases. In another embodiment, a sub-resolution assist feature (SRAF) is introduced for an edge of a feature and a bridge is generated from the feature to the SRAF. Then, the feature and the SRAF are assigned to opposite phases based on the relationship defined by the bridge.

Abstract: Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model.

Abstract: Methods of fabricating a photo mask are provided. The method includes collecting sample data, setting a preliminary mask layout, performing an optical proximity correction using the sample data and a preliminary mask layout to obtain an optimized preliminary mask layout, verifying the optimized preliminary mask layout to obtain a final mask layout, and fabricating the photo mask using the final mask layout. Verification of the optimized preliminary mask layout includes operating a verification simulator using the sample data and the optimized preliminary mask layout as input data to obtain verification image data. The verification image data includes a plurality of contours of a pattern at different vertical positions.

Abstract: A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.

Abstract: In the field of semiconductor device production, a method and system for fracturing or mask data preparation or optical proximity correction are disclosed, in which a target maximum dosage for a surface is input, and where a plurality of variable shaped beam (VSB) shots is determined that will form a pattern on the surface, where at least two of the shots partially overlap, and where the plurality of shots are determined so that the maximum dosage produced on the surface is less than the target dosage. A similar method is disclosed for manufacturing an integrated circuit.

Abstract: Methods and systems for lithographic simulation and verification comprising a process in the frequency domain or in the spatial domain of calculating intensity at a location (x, y) for a number of defocus values. In addition, evaluating the intensity calculation result to determine if the intensity level will result in the mask pattern being written onto a wafer. The verification process may be calculated in the spatial domain or in the frequency domain. The calculations may be done such that full focus window calculations may be obtained by isolating the defocus parameter “z” in the calculations.

Abstract: The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein base dosages for a plurality of exposure passes are different from each other. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, wherein a plurality of charged particle beam exposure passes are used, with base dosage levels being different for different exposure passes.

Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a plurality of exposure passes are used, and where the sum of the base dosage levels for all of the exposure passes does not equal a normal dosage. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, wherein a plurality of charged particle beam exposure passes are used, and where the sum of the base dosage levels for all of the exposure passes is different than a normal dosage.

Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, in which the union of shots from one of a plurality of exposure passes is different than the union of shots from a different exposure pass. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, in which the union of shots from one of a plurality of charged particle beam exposure passes is different than the union of shots from a different exposure pass.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction.