Abstract: In a graphical modeling environment, one of a selection of transformation operations is performed on a graphical object by first selecting the graphical object. A user may select a particular transformation operation to be executed on the graphical object from a list of transformation operations displayed to the user. A transformed graphical object derived from the selected graphical object may be then automatically created without retrieving the transformed graphical object from a library or other source.

Abstract: An apparatus for simulating the internal configuration of industry standard ROM and EPROM-type chips using other types of storage technologies, while still operating transparently with interfaces and mechanisms such as authentication devices adapted to EPROM-type media. The invention includes: an EPROM connector interface, a data presentation program; user access log display program; a user login/registration program; a software/data library; software/data selection program; and software/data loader program. These components work in conjunction to securely retrieve software images resident in mass storage media and to present them to an authentication device as if the images were resident in EPROM type media. The invention is particularly adapted to use in the gaming industry where regulation and fraud detection are performed using EPROM authentication techniques.

Abstract: An emulation technique adjusts the execution timing of instructions included in an application to be emulated. An emulator executes an instruction stream consisting of a plurality of instructions included in the application for an apparatus to be emulated to perform the object AP. This emulator performs successively the instructions included in the instruction stream at a predetermined period, and includes a speed controller for adjusting the emulation speed by intermittently inserting a wait into the instruction stream to emulate execution of the instruction stream. Preferably, this emulator includes a clock generator (145), in which the speed controller counts the clock input from the clock generator (145).

Abstract: A target graphics document containing graphics data may be used as a starting point to automatically generate one or more test cases as a sequence of test events to re-create the appearance of the target graphics document. The target document may be examined to determine the layers, graphics data within each layer, and the attributes of the graphics data. Based on the determined data, a sequence of input device actions may be generated to create a test document having graphics data based at least in part on the target document. In some cases, the generated input device actions may create a test document containing graphics data identical to that of the target document. In some cases, some user randomness may be applied to the generated input device actions to simulate ‘real-world’ user inaccuracy. In some cases, typical user manipulation of an input device may be applied to simulate ‘real-world’ usage.

Abstract: An apparatus, circuit arrangement and method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

Abstract: A method for emulating a system call includes making the system call by a first process in a first operating system (OS) for interacting with a second process, wherein the first OS is emulated in a second OS, spawning an agent process, wherein the agent process is a child process of the first process, implementing a functionality of the system call using a general mechanism in the second OS between the agent process and the second process, passing a result associated with the system call from the second process to the agent process using the general mechanism, and relaying the result from the agent process to the first process using a system call in the second OS, wherein the result is stored by the first process.

Abstract: A system comprising: a server; a computer terminal coupled remotely to the server via a network and installed with a web browser; and an external test platform, connected externally to the computer terminal, the test platform comprising a programmable target device and interface circuitry operable to communicate between the computer terminal and the target device. The server hosts a development tool available for download to the web browser via the network. The development tool comprises: one or more applets to be run by the web browser, and one or more web pages for display by the web browser to provide a user-interface for the development tool including to provide access to the one or more applets. The one or more applets at least comprise code-analysis applet software programmed so as when run by the web browser to operate said interface circuitry to: load code to be tested from the computer terminal onto the target device for test operation.

Abstract: A circuit emulation system and method are provided, the system including at least one trace chain and a trace memory in signal communication with the at least one trace chain for sequentially receiving values and feeding them back through the chain to their original storage unit positions; and the method including modeling the circuit, providing at least one storage unit in the model, emulating the circuit with the model, extracting a state of the at least one storage unit during emulation, storing the extracted state, and restoring the stored state through a feedback loop.

Abstract: Computer system and method automatically generates a test source code for checking validity of an application written in an object oriented language. The application includes objects accessible through an interface implementing programming rules and object behavior rules. For each object, the invention extracts object methods and attributes of the object interface which are impacted by the object behavior rules and extracts the object identification. The invention fills the variable fields of a source code template with the extracted information. The template non variable source code is in conformance with the programming rules and implements a scenario for checking a set of object behavior rules; thus the filled template forms a generated test source code. For distributed applications, the specifications may be EJB or CORBA and the Test Generator uses templates for checking the life-cycle (creation, persistency, removal) of deployed objects.

Abstract: Multiple versions of a runtime system, such as a software emulation application that emulates a legacy hardware architecture, are allowed to co-exist in the memory of a new hardware architecture. The operating system software of the new hardware architecture reads configuration data from a database or table to decide which version of the runtime system is desirable for an application program or game that is being loaded or is currently running, and, if a match is found, only that runtime system is invoked. To reduce storage footprint, the different versions of the runtime system may be stored using “differential patching” techniques. In this configuration, the operating system will always launch the same basic runtime system binary, but it will select a different differential patch to apply at run-time based on the title as determined during the database lookup.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary hardware systems of powerful older computers. High performance is typically a key requirement for a system even when built using emulation software. In a hardware design many special cases and conditions which may cause exceptions are detected by logic operating in parallel with the instruction execution. In software these checks can cost extra cycles of processor time during emulation of each instruction and be a significant detriment to performance. Avoiding some of these checks by relying upon the underlying hardware checks of the host system and then using a signal handler and special software to recover from these signals is a way to improve the performance and simplify the coding of the software emulation system.

Abstract: A check system aims at checking at least one of a control model in which requested specifications for controlling a target are described and a control program generated based on the control model. The system has a first establishing unit configured to establish a first monitor section at a first location in the one of the control model and the control program. The system has a first identifying unit configured to automatically identify a second location in the other of the control model and the control program to establish a second monitor section at the second location in the other thereof. The second location corresponds to the first location of the first monitor section in the one of the control model and the control program.

Abstract: Systems and methods are disclosed herein to provide communication testing for wireless or wired packet data communication devices, systems, and networks. In accordance with one embodiment of the present invention, a test system containing a multilevel scheduler is disclosed that includes cascaded schedulers, a software interface, and specific media protocol feedback to accurately emulate multiple clients on a network, with possibly numerous traffic flows per client. Such a test system may offer capabilities such as a more accurate emulation of client contention and collisions, a more accurate emulation of bandwidth sharing between clients, and a more accurate emulation of traffic flow multiplexing between flows.

Abstract: A method for tracing an instrumented program involves triggering a probe in the instrumented program, obtaining an original instruction associated with the probe, storing the original instruction into a scratch space, storing a jump instruction for an architecture that supports pc-relative addressing into the scratch space, wherein the jump instruction includes a next program counter value, executing the original instruction in the scratch space using a thread, and executing the jump instruction in the scratch space using the thread.

Abstract: The majority of such software attacks exploit software vulnerabilities or flaws to write data to unintended locations. For example, control-data attacks exploit buffer overflows or other vulnerabilities to overwrite a return address in the stack, a function pointer, or some other piece of control data. Non-control-data attacks exploit similar vulnerabilities to overwrite security critical data without subverting the intended control flow in the program. We describe a method for securing software against both control-data and non-control-data attacks. A static analysis is carried out to determine data flow information for a software program. Data-flow tracking instructions are formed in order to track data flow during execution or emulation of that software. Also, checking instructions are formed to check the tracked data flow against the static analysis results and thereby identify potential attacks or errors. Optional optimisations are described to reduce the resulting additional overheads.

Abstract: A system for evaluating a simulation includes a reference simulator configured to execute a simulation image to obtain golden data, a test simulator configured to execute the simulation image to obtain test data, and a comparator configured to generate a comparison result by comparing a portion of the golden data to a portion of the test data before the execution of the simulation image on the test simulator has completed.

Abstract: A method and apparatus for sharing data between processors within first and second discrete clusters of processors. The method comprises supplying a first amount of data from a first data array in a first discrete cluster of processors to selector logic. A second amount of data from a second data array in a second discrete cluster of processors is also supplied to the selector logic. The first or second amount of data is then selected using the selector logic, and supplied to a shared input port on a processor in the first discrete cluster of processors. The apparatus comprises selector logic for selecting between input data supplied by a first data array and a second data array. The data arrays are located within different discrete clusters of processors. The selected data is then supplied to a shared input port on a processor.

Abstract: Techniques and tools for achieving improved test coverage in a finite program state space are described, such as a technique for selecting a set of predicates, calculating a set of possible predicate values, calculating a subset of the set of possible predicate values, and generating a test for the computer program based at least in part on the subset. The subset comprises an approximation (e.g., an under-approximation) of reachable states in the program. A superset of the set of possible predicate values also can be calculated; the superset comprises an over-approximation of the reachable states in the program. In another aspect, a Boolean abstraction of a program is generated, reachability analysis is performed based at least in part on the Boolean abstraction, and symbolic execution is performed to generate test data. The reachability analysis can include computing lower and/or upper bounds of reachable observable states.

Abstract: A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time interrupt during an emulation halt. An Interrupt During Suspend bit is set in foreground modes and transmitted in the trace data stream to distinguish the trace data streams between background mode and foreground mode.

Abstract: A microprocessor to provide software development debugging capabilities while providing security for confidential and/or sensitive information. The processor may operate in one of an open, a secure entry, and a secure mode. In open mode, security measures may prevent access to certain registry bits and access to a private memory area. Secure entry mode may be entered upon receipt of a request to run secure code and/or access the private memory area. The secure code may be authenticated in secure entry mode. Authentication may be performed using digital signatures. Secure mode may be entered if authentication is successful. Authenticate code may be executed in the secure mode environment. The private memory area may be accessible in secure mode.

Abstract: In accordance with one embodiment of the present invention, a technique for supporting dynamically typed languages in typed assembly languages is provided. According to one embodiment, a new bytecode instruction, “invokedynamic,” supplements “invokevirtual.” Prior to the execution of a typed assembly language program, it is determined whether a particular method-invoking instruction is a particular kind of instruction. If the instruction is of the particular kind, then the verifier refrains from performing the usual pre-execution type checking of the arguments that will be on the operand stack when the instruction is executed. Consequently, the bytecode instruction may be used to represent the invocation of a method that might not indicate formal parameter types. Because the verifier performs less stringent type checking in response to such an instruction, the JVM can execute assembly language programs that were generated based on source code that was written in a dynamically typed language.

Abstract: Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This invention further generally relates to a technology facilitating the interoperability of native and non-native program modules within a native computing platform. More specifically, this technology involves an emulation of the kernel of the non-native operating system. Instead of interacting with the native kernel of the native computing platform, the non-native program modules interact with a non-native kernel emulator. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: The present invention is directed to an extensible console emulator for Hyperion Performance Suite interaction. An emulator system in accordance with an embodiment of the present invention includes: a Hyperion Performance Suite (HPS) console emulator for receiving commands from a source and for performing actions based on the commands; and an HPS Software Development Kit (SDK) for receiving output from the HPS console emulator and for interacting with the HPS; wherein the HPS console emulator provides an interface that allows a user to interact with the HPS via the HPS SDK.

Abstract: The present invention compensates for the shortcomings in x86 processor architectures by providing a set of “synthetic instructions” that cause a trap and thereby provide an opportunity for the virtual machine (VM) to process the instructions safely. By using instructions that are “illegal” to the x86 architecture, but which are nonetheless understandable by a virtual machine, the method of using these synthetic instructions to perform well-defined actions in the virtual machine that are otherwise problematic when performed by traditional instructions to an x86 processor but provide much-improved processor virtualization for x86 processor systems.

Abstract: Code handling, such as interpreting language instructions or performing “just-in-time” compilation, uses a heterogeneous processing environment that shares a common memory. In a heterogeneous processing environment that includes a plurality of processors, one of the processors is programmed to perform a dedicated code-handling task, such as perform just-in-time compilation or interpretation of interpreted language instructions, such as Java. The other processors request code handling processing that is performed by the dedicated processor. Speed is achieved using a shared memory map so that the dedicated processor can quickly retrieve data provided by one of the other processors.

Abstract: A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.

Abstract: A system and method for a desk checker includes a partial state representation, a simulator controller to access the partial state representation and to continue a simulation without state information, and a desk checking component controlled by the simulator controller. The desk checking component includes any of a user interface, a static analysis engine, a partial execution component, and an analyzer. The system and method for desk checking includes simulating code execution on a computing device with partial state information and requesting user input to supplement the partial state information.

Abstract: A method for tracing an instrumented program on a processor having an x86 architecture, including triggering a probe in the instrumented program, obtaining an original instruction associated with the probe, loading the original instruction into a scratch space, loading a jump instruction for the x86 architecture into the scratch space wherein the jump instruction includes a next program counter value, executing the original instruction in the scratch space using a thread, and executing the jump instruction in the scratch space using the thread.

Abstract: A method for analyzing and presenting application results, said method comprising the steps of creating at least one log file representing a result file of an application; tagging the at least one log file with at least one file tag representing a location of the result file of the application; tagging the at least one log file with at least one return code tag; tagging the at least one log file with at least one application configuration tag representing a graphical representation of the result file of the application; parsing the at least one log file tag; parsing the at least one return code tag; parsing the at least one application configuration tag; generating a summary report file from the at least one log file by using the parsed at least one file tag, the at least one return code tag, and the at least one application configuration tag; translating the summary report file into the graphical representation wherein the graphical representation comprises hyperlinks for navigation between the at least one

Abstract: An embodiment of the invention is a technique for enabling an emulator that emulates an e-mode program to utilize stored data items whose values are stored in native data format in native memory. The emulator fetches an item referenced by the e-mode program. The referenced item comprises a tag field and a data field. The emulator determines whether the tag field of the referenced item indicates that the referenced item is an external reference word (ERW). If the tag field of the referenced item indicates that the referenced item is an ERW, the emulator decodes the ERW to obtain a data type and a pointer. The pointer corresponds to a location of a stored data item in native memory.

Abstract: A debugger attaches to a parallel process that is executing simultaneously at various nodes of a computing cluster. Using a shim, executing at each node, to monitor each of the processes, the parallel process is debugged such that neither the process or the particular message passing system implemented on the cluster, needs to know of the existence or details regarding the debugger.

Abstract: Code coverage questions are addressed by a code coverage method that instruments an electronic module source design file with coverage probes and gives hierarchical names to the probes, then provides therefrom an instrumented gate level netlist. The instrumented netlist is run on a hardware emulator, executing reset trigger scripts to reset the branch and statement probes, and then a fully initialized design is driven in emulation on a simulated testbench from which the probe values are retrieved. These values can then be evaluated to determine the extent of code coverage. Various forms of coverage are supported including branch, statement, reset trigger and toggle coverage.

Abstract: An apparatus, circuit arrangement and method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

Abstract: It is possible to provide a semiconductor test program debug device capable of reducing the unnecessary facilities when using a semiconductor test device or a semiconductor test program of different specification.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: A method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

Abstract: Various technologies and techniques are disclosed for testing intermediate language operations. A debugger harness is provided that instruments an intermediate language stream to replace intermediate language operations with equivalent virtual intermediate language operations. A particular intermediate language operation is intercepted from the intermediate language stream and the equivalent virtual intermediate language operation is determined. The virtual machine runs under a debugger harness so that one or more managed applications are executed using the equivalent virtual intermediate language operations. This allows a functionality of the debugger to be tested.

Abstract: A method of separating a function of the business logic of an application from a user interface of the application where the business logic and user interface of the application are intermingled is provided. The method includes providing a wrapper interface for the application. The method also includes providing a function of the business logic of the application separated from the user interface of the application through the wrapper interface.

Abstract: A manipulation tool (e.g., “the XABLE tool”) provides a user interface (UI) automation library that allows a tool user to find existing UI objects and then perform a UI action on such UI objects. In one exemplary application, the manipulation tool can be used by script writers to automatically drive the UI of an application under test. A plurality of selectable search strategies are provided for searching for UI objects. Further, an event handling object is provided for monitoring the firing of UI objects.

Abstract: A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from multiple stimulation results. Each of these extracted building block events or “tags” are created from a slice of a graphical stimulation view, which slice is converted into a coded stimulus written in a high-level language code that represents the condition(s) that created the graphical simulation view. These coded stimuli (representing the tags) are stored in a library. To create a corner case scenario or sequence in the DUT, a user utilizes a graphical interface to select the different extracted tags from the library and combines them together.

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract: A system for generating a set of robot commands uses user entry events in a user interface. Such a system may include an event queue to which the events are sent from the user interface and a RobotCreator tool for receiving the events as those events are submitted to the event queue. The event queue is configured to allow receipt of the events by the RobotCreator. The RobotCreator tool converts the events into robot commands.

Abstract: A system, method, computer program product, and carrier are described for obtaining data from a first emulator and from a first emulation environment hosting software and signaling a decision whether to transfer any of the data to a second emulator at least partly as a result of the first emulation environment hosting the software.

Abstract: A system for debugging targets using various techniques, some of which are particularly useful in a multithread environment. These techniques include implementing breakpoints using out-of-line instruction emulation so that an instruction replaced with a breakpoint instruction does not need to be returned to its original location for single-step execution, executing a debugger nub for each target as part of the target task but using a nub task thread for the nub execution that is separate from the target task threads, providing immunity from breakpoints for specified threads such as the nub thread via specialized breakpoint handlers used by those threads, and virtualizing the debugger nub such that a shared root nub provides a uniform interface between the debugger and the target while specialized nubs provide differing functionality based on the type of target being debugged.

Abstract: A computer-implemented method, system, and computer-readable medium for emulating web service operations are presented. In a preferred embodiment, the computer-implemented method includes the steps of: collecting Web Services Description Language (WSDL) based descriptors of selected web service operations; receiving range and diversity descriptors for the selected web service operations; and inputting the WSDL based descriptors, range and diversity descriptors into an Automatic Web Service Emulator Generator (AWSEG) to generate a web service emulation of the selected web service operations.

Abstract: A method provides a demonstration capability for a plurality of network coupled users by which many users can watch a primary user interact with an application. The method includes providing an application to a primary user from an application server over a network and translating output from the application into a broadcast protocol. The broadcast protocol is then translated into a browser protocol transmitted over a network for rendering by browsers at a plurality of network attached computers.

Abstract: Methods, data processing systems, and program products supporting the insertion of clone latches within a digital design are disclosed. According to one method, a parent latch within the digital design is specified in an HDL statement in one of the HDL files representing a digital design. In addition, a clone latch is specified within the digital design utilizing an HDL clone latch declaration. An HDL attribute-value pair is associated with the HDL clone latch declaration to indicate a relationship between the clone latch and the parent latch according to which the clone latch is automatically set to a same value as the parent latch when the parent latch is set. Thereafter, when a configuration compiler receives one or more design intermediate files containing the clone latch declaration, the configuration compiler creates at least one data structure in a configuration database representing the clone latch and the relationship between the clone latch and the parent latch.

Abstract: A method and system for enforcing version control is provided. An embodiment of the method comprises receiving a command to execute code. Code is retrieved from a code management storage and loaded into a controlled storage. The code may comprise test and program components. The code is executed and the results of the executed code are recorded and logged, and the code is removed from the controlled storage. The system includes an interface for receiving the execute code command and is coupled to the controlled storage. A code loader for loading code into the controlled storage may also be provided.

Abstract: A system performance prediction mechanism based on software component performance measurements. The system performance prediction of the present invention is performed in the following procedure: (1) determine operating conditions, under which individual software components operate, from the software components and requests constituting a processing content of the transaction to be processed by the system; (2) determine system resource utilizations by searching a performance database 10 using each software component and operating conditions as keys; (3) combine results of searching for the system resource utilizations of all software components involved in processing of a transaction important in the system performance and predict the system resource utilization of the transaction; and (4) predict a system resource utilization of the entire system by combining the results obtained in the above (3) and inputting them into a system performance prediction model.