Abstract: An automated analysis system identifies the presence of malicious P-code or N-code programs in a manner that limits the possibility of the malicious code infecting a target computer. The target computer system initializes an analytical virtual P-code engine (AVPE). As initialized, the AVPE comprises software simulating the functionality of a P-code or intermediate language engine as well as machine language facilities simulating the P-code library routines that allow the execution of N-code programs. The AVPE executes a target program so that the target program does not interact with the target computer. The AVPE analyzes the behavior of the target program to identify occurrence of malicious code behavior and to indicate in a behavior pattern the occurrence of malicious code behavior. The AVPE is terminated at the end of the analysis process, thereby removing from the computer system the copy of the target program that was contained within the AVPE.

Abstract: One implementation provides a computer system that is capable of processing task requests from front-end software applications. The computer system is programmed to receive a task request from a front-end software application. The task request includes input values and a task name that is associated with an analytical task of a particular type to be executed. The computer system is also programmed to use the task request to select a subset of the input values needed for execution of the analytical task of the particular type, create a task invocation request that includes the selected input values, and send the task invocation request to an analytical engine.

Abstract: A developer is provided with an emulation tool, which approximates speed conditions of an application executing on a target device, for example a MIDlet executing on a mobile information device, by matching network operations of a development platform to the lesser performance capabilities of the target device. The developer is thereby enabled to optimize an application's network usage early in its development. The time required to perform communications operations in the development environment is increased sufficiently to permit an application developer to more accurately emulate the target device.

Abstract: A synthetic benchmark for a computer program and a method and computer program product for creating a synthetic benchmark for a computer program. The synthetic benchmark is created using statistical information that is collected about an executing program, and some hints about the machine on which the benchmark will be run. When executed, the synthetic benchmark exhibits behavior similar to the computer program to permit computer performance to be accurately measured.

Abstract: A real time data exchange on demand system for transferring real time data between a host processor and a target processor is described. The target processor includes a real time target exchange library and API library interface to a target application. The host processor includes a target server, a real time data exchange API interface to a host data exchange application and a real time data exchange dynamic link library. An interconnection data link is coupled between said real time target exchange library on said target processor and said real time data exchange dynamic link library on said host processor. The host processor includes a user interface for programming real time data exchange transfer points for data exchange into the target processor that are passed down to the target processor via the interconnection data link. The target processor has programmable triggers that are programmed by the transfer points that call an appropriate real time data exchange routine to do the data transfer.

Abstract: A Java application is debugged in a Java micro device by selectively loading from a host computer into the device, a subset of Java classes and/or Java resource files that is used during the debugging the Java application in the device, that is automatically selected from a set of Java classes and/or Java resource files in the host computer. Thus, the need to load a potentially huge Java ARchive (JAR) file that contains all classes and/or resources, at the start of debugging, can be reduced or eliminated. The invention also may be used to load modules that are used during debugging an application on a device from a host computer.

Abstract: A method for testing operation of a computer application. An emulator is provided to run on a development platform subject to limitations of multiple different target devices, the emulator including a set of emulator APIs corresponding to target Application Program Interfaces (APIs) available on the different target devices. A subset of the target APIs that are supported by one of the target devices is specified. Access by the emulator to the emulator APIs that correspond to one or more of the target APIs that are not in the specified subset is blocked. The application is run on the emulator subject to the blocked access.

Abstract: A low-cost micro-controller debugging system with a ROM or RAM emulator is disclosed. The system includes a target microcontroller (MCU) and at least one ROM connected together, with a debugger unit which debugs that target MCU. A ROM/RAM emulator is connected to the target MCU and the debugger unit for emulating the ROM.

Abstract: A system and method for emulating or monitoring the communications behavior of any system component connected to a data bus. These functions are accomplished through the implementation of software component emulators (SCE) that encode and decode message data for any system component automatically. The present invention includes a means for development of an interface specification based on information contained in an Interface Control Document (ICD), and enables the user to create the ICD file without having to worry about formatting considerations, and view and define message data in a meaningful, human-readable format. The information in the ICD is automatically reduced to an application that combines the user-friendly, time-efficient aspects of a traditional SCE with the flexibility and universality of a bus monitor.

Abstract: The invention relates to managing registers during a binary translation mode in a virtual computing system. A set of registers is saved to memory before beginning to execute a series of blocks of translated code, and the contents of the set of registers are restored from memory later. A status register is maintained for tracking the status of each register within the set, the status indicating whether the contents are valid and whether the contents are saved in memory. Before the execution of each block, a determination is made as to whether the actions taken within the block relative to the registers are compatible with the current status of the registers. If the actions are not compatible, additional registers are saved to memory or restored from memory, so that the translation block can be executed.

Abstract: A method of monitoring processor resources. To monitor a processor resource, first a set of needed resources is determined at the beginning of a block of code. A test is then performed to determine if the set of needed resources is available at the start of the block of code. An error is signaled if the needed resources are not available at the beginning of the block of code.

Abstract: Method and apparatus for providing a user interface application programming interface (API) for providing extended access to the database by third-party and user software products. In accordance with one embodiment, a method for accessing a business database includes instantiating a company object as an instance of a company class conforming to a component object model standard, setting a server property of the company object to a database server name, setting a company database name property of the company object to the name of a company, setting a user name property of the company object to the name of a user, setting a password property of the company object to a password of the user, setting a language property of the company object to a desired language of the user; and invoking a connect method within the company object, the connect method opening a software connection to a database identified by the company database name property.

Abstract: A device for modeling an integrated enterprise includes a first tool for constructing a model of the integrated enterprise and a second tool which validates compliance of documents constructed by the first tool with a set of standards. The documents which may be constructed by the first tool include an analysis interface control document (“ICD”) and a design ICD document. The second tool may then be used to selectively compare either the analysis ICD or the design ICD with selected ICD standards and generate an analysis ICD document standards exception report and a design ICD document standards exception report, respectively, which lists each variation of the analysis and design ICD documents from the selected ICD standards. The analysis and/or design ICD standards exception reports may subsequently be used as guides to correct errors in the analysis and/or design ICD documents causing the exceptions.

Abstract: A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein the set name API entry point includes program instructions for naming a simulation control program in association with testcase execution of the HDL model. A create event API entry point is called, wherein the create event API entry point includes an event identifier input parameter which identifies a testcase execution event with respect to the named simulation control program. In response to executing a testcase simulation cycle, signal values are retrieved from the HDL model into an instrumentation code block, wherein the instrumentation code block includes program instructions for processing the retrieved signals to detect whether the testcase execution event has occurred during the testcase simulation cycle.

Abstract: A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs. The simulation control program sums count values of the first and second count event registers in accordance with the correlation data structure and outputs a count event data packet containing the aggregate count value.

Abstract: Embodiments of the present invention effectuate a method and system for debugging a device such as a microcontroller in a distributed architectural scheme, where the device may operate at speeds much faster than the debugger program is run, with limited debugging resources physically incorporated into the device itself, and with relatively limited computational capacity, vis-à-vis the platform deploying the debugging software. The embodiments place relatively modest, uncomplicated demands on the debugger software, and the ICE may also be relatively simple. Further, debugging methods and systems according to these embodiments are flexible and adaptable to a variety of different devices that must undergo debugging, yet remain effective, simple, and inexpensive.

Abstract: The invention relates to a software system and method for automatically verifying the correct execution of an application ported from one instruction set architecture (ISA) to another ISA. In this method, versions of the application are prepared for the two ISAs. Each version is then executed in a simulator or emulator for the appropriate ISA and the results of any change in memory made during the execution are compared. If each memory change made during the execution of the target version of the application is found to be equivalent to a memory change made during the execution of the source version of the application, the execution of the target (or ported) application is verifiably correct.

Abstract: A method and system of monitoring code as it is executed by a target processor is provided for debugging, etc. Standardized software code function preamble and postamble instructions are dynamically replaced with instructions that will generate a predetermined exception. The exception generates a branch to a conventional exception vector table. An exception routine is inserted into the vector table, and includes instruction(s) to disable the data and/or address caches. Subsequent instructions in the vector table execute the replaced preamble instruction and, with or without re-enabling the cache, branch back to the address of the program code immediately following the faulted preamble address. Instructions of the function executed while cache is disabled are executed on the bus where they are visible, as opposed to within cache.

Abstract: The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is used to determine if a valid effective address is available for each instruction. If a valid effective address for an instruction is not available, it is computed if possible.

Abstract: An apparatus for facilitating development of an application for a wireless-connected device including a module have a plurality of development tools for use in the creation of the application and an emulator of the wireless-connected device integrated with the module. An additional emulator for an additional wireless-connected device is also included. The module may be included in an Integrated Development Environment.

Abstract: A core file derived from an application crash is created. The application belongs to a source platform and is run on a target platform. The application is emulated on the target platform. In response to the crash occurring, detecting whether the crash corresponds to the failure of a process corresponding to the emulated application. The crash process is mediated by intercepting information relating to the failure of the emulated application and writing a core file corresponding to the failure of the emulated application running on the source platform. A dynamic binary translator performs the steps and debugs an emulated application as if it had crashed and dumped a core file on its native platform.

Abstract: A real time functional replicator (10) of a specific integrated circuit comprised of a processing unit and peripherals in order to perform specific digital and/or analog functions controlled by specific software, this specific integrated circuit being designed to be incorporated into a specified application board.

Abstract: A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time interrupt during an emulation halt. An Interrupt During Suspend bit is set in foreground modes and transmitted in the trace data stream to distinguish the trace data streams between background mode and foreground mode.

Abstract: In response to an automatic baseline input, a default control template for a site in a telecommunications network is translated into monitoring and simulation templates. Current end-to-end application and component information are translated into operational modes for monitoring and simulation modules according to the monitoring and simulation templates. Operational controls are established for controlling the monitoring and simulation modules for controlling, in real time, the transmission of network management and simulation traffic.

Abstract: A system and method for intelligently generating computer code. The system being comprised of a local computer, which is connected to a remote computer via a network system or the Internet and which is capable of exchanging files with the remote computer. The local computer is further comprised of a document manager for transferring files between the local computer and the remote computer and for providing enhanced file management functions. The document manager works in connection with the server module, the site manager and the connectivity layer to connect to remote computers, to transparently exchange files with the remote computer and to manage server profiles and connection information that is related to remote computers and transferred files. Once the file is transferred to the local computer, the editor can modify the code associated with the file; the editor is also capable of creating new files.

Abstract: Communications between a device and a debugging system are effectuated by programming an ICE with a first logic set, which enables the ICE to establish communications with the device and determine a unique identifier thereof. The ICE communicates the device's unique identifier back to a host computer. The host computer matches the unique identifier to a second logic set and a plug-in module. The host computer then programs the ICE with the second logic set and activates the plug-in module. The second logic set allow the ICE and the device to execute program instructions downloaded with the second logic set in lock-step fashion. The plug-in module allows the host computer to interact in the debugging process as necessary. This achieves flexibility, because any ICE may be programmed to communicate with any device.

Abstract: A method is disclosed for providing mobile code software applications to users via an application service provider (ASP). The ASP receives a mobile code application, such as a Java application, from a provider, along with a security specification. The security specification defines access privileges requested to execute the application, including privileges to execute functions performed by the application and privileges to access local resources of the ASP. The ASP receives a subscription to the application from a user. The subscription includes subscription information granting or denying privileges, and specifying parameters for the privileges, requested in the security specification. The ASP executes the application at runtime by determining for each executable function whether the user has authorized the requested privilege. Those functions authorized by the user are executed in one embodiment.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. Legacy instructions are translated into translated instructions. If the particular legacy instruction is an operand-setting instruction for storing a value of a precedent operand, a corresponding flag is set when the value of the precedent operand has not been determined. If the particular legacy instruction is an operand-using instruction for using the precedent operand, a check is made to determine if the corresponding flag is set.

Abstract: A software driven emulator in which the stored emulation program for a processor module is compiled to include a code bit or bits in the emulation instruction step sequence that is decoded as main data memory disable command. Thus, once in each emulation program cycle, the memory controller disables the main data memories on the module, and allows the maintenance bus to read or write data to these memories.

Abstract: To provide a technique for connection from a conventional personal computer having no terminal ID to a service site for mobile phone terminals. A simulation server 4 is set as the proxy server for a personal computer 5 or 9. In the proxy server (simulation server 4), terminal ID's suitable for the format are generated, and a cookie is generated for each personal computer or session. The terminal ID's and cookies are related and stored as a hash table 10. In the proxy server 4, a terminal ID is appended to a request from the personal computer 5 or 9, and the request is transferred to an i-mode server 3 along with the terminal ID.

Abstract: A method for testing server machine performance is described. A client-emulating server machine has a collection of live data maps for a plurality of transactions for a chosen computing application. A server is in communication with the workstation. The workstation transmits a processing load, including a plurality of the maps for the plurality of transactions, to the server as it executes the computing load. The server measures one or more performance criteria as it executes the load. The performance criteria can include the average response time for a transaction within a load, and the proportion of server CPU time taken by each transaction of the load. By varying the processing load generated by the workstation and assessing the measured performance criteria, it is possible to determine whether the server has satisfactory capacity.

Abstract: A system where a production microcontroller is partially copied in a FPGA of an ICE to form a virtual microcontroller. The virtual microcontroller and the production microcontroller simultaneously and independently run a microcontroller code to be debugged at a high frequency. The debugging logic can substantially reside in the ICE and the ICE can perform all debugging functions. The debug interface, residing in the production microcontroller, can enable the production microcontroller to communicate with the ICE in low frequencies. The production microcontroller may request the ICE to lower its frequency when the production microcontroller encounters a halt due to outside events. A user may command resumption of the operation of both the production microcontroller and the virtual microcontroller when debugging of the codes is completed.

Abstract: To test the functionality of a computer system, automated testing may use an automation testing tool that emulates user interactions. A database may store words each having a colloquial meaning that is understood by a general population. For each of these words, the database may store associated computer instructions that can be executed to cause a computer to perform the function that is related to the meaning of the word. During testing, a word may be received having a colloquial meaning that is understood by a general population. The database may be queried for the received word and the set of computer instructions may be returned by the database. The automated testing tool may then perform the function returned to the colloquial meaning of the word. The words stored in the database may be in English or another language.

Abstract: One embodiment of the present invention provides a system for emulating computer viruses and/or malicious software that operates by patching additional program instructions into an emulator in order to aid in detecting a computer virus and/or malicious software within suspect code. During operation, the system loads a first emulator extension into the emulator. This first emulator extension includes program instructions that aid in the process of emulating the suspect code in order to detect a computer virus and/or malicious software. The system also loads the suspect code into an emulator buffer. Next, the system performs an emulation using the first emulator extension and the suspect code. This emulation is performed within an insulated environment in a computer system so that the computer system is insulated from malicious actions of the suspect code. During this emulation, the system determines whether the suspect code is likely to exhibit malicious behavior.

Abstract: A method and a apparatus for testing a software emulator while executing the software emulator on a target machine architecture are disclosed. The method may include the steps of executing a test program on a target machine architecture, with a test program producing a first output, executing an emulator on the target machine architecture, and the emulator executing the test program under emulation, with the test program producing a second output.

Abstract: A system and method for facilitating and simplifying testing and debugging of computer programs. is described A computer program is broken down to smaller components, such as, classes, functions, or objects, and then those smaller components are tested individually. Accordingly, specific aspects of the computer program can be effectively tested. The user can automatically perform a range of tests on a class or method when the class or method is compiled without integrating the class or method into a larger project.

Abstract: The present invention provides a data processing apparatus and method for testing power management instructions. The data processing apparatus comprises a processor for executing data processing instructions including power management instructions, at least one of the power management instructions being a command power management instruction. A power management controller is also provided for receiving command data from the processor when a command power management instruction is executed by the processor, and to control power management logic to perform an associated set of power management functions dependent on the command data. The data processing apparatus includes first power management logic controllable by the power management controller, with the power management controller also having an interface to enable communication with additional power management logic.

Abstract: The present invention relates to a system and method for emulating a greater range of behavior of a peripheral device connected to a host device or host computer than was available in the prior art. The emulation of a greater range of activity of the peripheral device provides an opportunity to more fully test the interaction of a host device with the emulated peripheral device. More specifically, the present invention preferably adds control data line and power data line connections to user data line connections between the host device and an intelligent emulator so that variations in control settings and power levels may be exercised in addition to manipulation of transmissions along a user data line, thereby more fully exercising host device interaction with an emulated device.

Abstract: Pipeline activity information associated with all stages of execution of an instruction in an instruction pipeline of a data processor is presented to an event detector in timewise aligned format. This permits events in the pipeline to be presented to the event detector in a sequence that is consistent with the context in which a programmer of the event detector would normally think of those events, thereby simplifying programmation of the event detector.

Abstract: A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured.

Abstract: Techniques for testing subsystems on a platform for a software application are provided. A test application receives instructions for calling platform dependent subsystems directly. The instructions can be designed to fully test the capabilities of the subsystems. Once the instructions are executed, the results of the subsystems can be analyzed for platform certification, performance, reliability, and/or characteristics.

Abstract: A packet core network (PCN) includes a plurality of interconnected routers. An emulator is provided along with at least one of the routers and operates to control transmission of Internet Protocol (IP) datagrams there through in order to simulate the effects of having one of the non-radio inter-router connections fictionally comprise a wireless cellular radio link. The emulator responds to user input specifying wireless cellular radio link conditions to determine a time delay to be applied by the router against the transmission of each datagram. This time delay is set roughly equivalent to the delay introduced, under the user specified wireless cellular radio link conditions, by emulated radio link operation to erase uncorrectable frames to obtain retransmission. The emulator further sets a data rate for router handling of datagrams based on the user input to simulate congestion on the radio link due to the presence of other, competing users.

Abstract: A method and apparatus for verifying program code conversion performed by an emulator. A first emulator configured in a same-to-same (X-X) mode converts subject code into target code for execution by a subject processor. Execution of the subject code natively by the subject processor is compared against execution through the first emulator, to verify that program code conversion. Optionally, the first emulator is then used to incrementally validate program code conversion (i.e. optimisation and/or translation) performed by a second emulator, such as a this-to-that (X-Y) mode emulator running on a target processor.

Abstract: An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing units includes a memory controller and a bus trace macro (BTM) module. The memory controller is coupled to an interconnect for the symmetric multiprocessor system, and the BTM module is connected between the interconnect and the memory controller via two multiplexors. A subset of the BTM modules within the symmetric multiprocessor system is enabled for performing tracing is operations such that address transactions on the interconnect are divided among the subset of the BTM modules to be selectively and separately intercepted by each BTM module within the subset of the BTM modules.

Abstract: A method and structure for emulating on a single display platform an application's user interface as it would appear on each of a number of target devices, given a set of device characteristics for any device to be emulated and a formal description of one or more applications to be emulated. The method includes combining a selected one or more of the device characteristics and a selected one of the application formal descriptions and providing a simultaneous and consistent display representation for the selected application, so as to provide a stylized rendering of the selected application's interface in a uniform appearance and in which the selected application's interface for more than one target device can be simultaneously viewed. The method also synchronizes the display representation, so that a simultaneous update to all of the selected target device representations is updated when information in a device-independent portion of the formal description is changed.

Abstract: A CD (compact disc) system is provided in a software form, by which a virtual CD-R (compact disc recordable) can be formed on a computer, and an actual CD-R can be easily and quickly formed from this formed virtual CD-R. While original data is processed, a virtual CD-R is formed in accordance with a structural requirement of a CD into a storage means employed in the computer. Furthermore, an actual CD-R is formed from the above-explained CD-R.

Abstract: A debugging method is used for the keyboard controller code. Through the breakpoints set at the testing end and loaded debugging program, the keyboard controller code sends state data to the testing end at the breakpoints in accord with the debugging program. The testing end returns commands according to the received state data to trace the execution state of the code, thereby debugging the code procedure.

Abstract: A method is provided for prototyping, testing, stimulating and verifying software embedded in a microprocessor without modifications to the underlying source code. The method includes: presenting an software program having a plurality of machine instructions of a finite number of fixed lengths in an executable form; searching through the machine instructions of the executable and finding at least one appropriate instruction to replace; and defining a replacement instruction for identified machine instructions in the software program; and replacing identified machine instructions in the executable form of the software program with the replacement instruction. The replacement instruction may be further defined as a branch instruction that references an address outside an address space for the software program.

Abstract: A method for compiling a logic design includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.

Abstract: When a DEBUG HALT signal is generated in a target processor during a test procedure, a debug halt sync marker is generated in a program counter trace stream. The debug halt sync marker includes a plurality of packets, the packets identifying that the sync marker is the result of a DEBUG HALT signal. The packets also identify the program counter address at the time of the generation of the DEBUG HALT signal and relate the debug halt sync marker to a timing trace stream.