Abstract: The various aspects leverage the novel observation that the number of call sites in code is directly correlated with the code's compile time and provide methods implemented by a compiler operating on a computing device (e.g., a smartphone) for performing inline throttling based on a projected number of call sites in the code that would exist after performing inline expansion. The various aspects enable the compiler to improve the performance of the generated code by aggressive inlining while carefully managing increases in compile time, thereby decreasing the power required to compile the code while increasing performance of the computing device. Thus, by inlining enough call sites to reduce the costs of handling calls while accounting for the costs of inlining, the various aspects provide for an effective balance of short compile times and effective code performance.

Abstract: A method for analyzing data reordering operations in Single Issue Multiple Data source code and generating executable code therefrom is provided. Input is received. One or more data reordering operations in the input are identified and each data reordering operation in the input is abstracted into a corresponding virtual shuffle operation so that each virtual shuffle operation forms part of an expression tree. One or more virtual shuffle trees are collapsed by combining virtual shuffle operations within at least one of the one or more virtual shuffle trees to form one or more combined virtual shuffle operations, wherein each virtual shuffle tree is a subtree of the expression tree that only contains virtual shuffle operations. Then code is generated for the one or more combined virtual shuffle operations.

Abstract: Particular embodiments optimize a C++ function comprising one or more loops for symbolic execution, comprising for each loop, if there is a branching condition within the loop, then rewrite the loop to move the branching condition outside the loop. Particular embodiments may further optimize the C++ function through simplified symbolic expressions and adding constructs forcing delayed interpretation of symbolic expressions during the symbolic execution.

Abstract: An approach is provided in which a set of common instructions are each executed by at least two processor cores. Each of the processor cores queues values resulting from at least one of the common instructions (a critical section). The queued values are compared by a queued comparator. An exception is issued in response to the comparison revealing unequal values having been queued by the processor cores.

Abstract: Embodiments include systems and methods for generating an application code binary that exploits new platform-specific capabilities, while maintaining backward compatibility with other older platforms. For example, application code is profiled to determine which code regions are main contributors to the runtime execution of the application. For each hot code region, a determination is made as to whether multiple versions of the hot code region should be produced for different target platform models. Each hot code region can be analyzed to determine if benefits can be achieved by exploiting platform-specific capabilities corresponding to each of N platform models, which can result in between one and N versions of that particular hot code region. Navigation instructions are generated as part of the application code binary to permit a target machine to select appropriate versions of the hot code sections at load time, according to the target machine's capabilities.

Abstract: The present invention provides a method and system for optimization of an intermediate representation in a graphical modeling environment. A first intermediate representation is provided. At least one optimization technique is applied to the first intermediate representation. A second intermediate representation is generated responsive to the application of the at least one optimization technique to the first intermediate representation.

Abstract: More effective compiler optimizations provide improved cache utilization. The compiler optimizations include a structure layout optimization that leaves the physical layout of the structure fields intact and instead changes the access order to these fields. The compiler optimizations apply to arrays using array remappings analogous to structure layout optimizations in which the array is considered as a structure and the physical layout of the array remains intact and instead the access order to the array changes.

Abstract: An illustrative embodiment provides a computer-implemented method for an alternate type system for optimizing the evaluation and use of meta-template instantiations. The computer-implemented method obtains a source code, instantiates an element of the source code to form an instantiated element and identifies a meta-template within the instantiated element to form an identified meta-template. The computer-implemented method creates an entry for the identified meta-template in a first data structure, wherein the entry comprises a set of mapped entries, creates an associated entry in a second data structure linked to the entry comprising the set of mapped entries, wherein the associated entry represents the set of mapped entries, and uses the associated entry of the second data structure in combination with the entry of the first data structure.

Abstract: A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.

Abstract: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

Abstract: A method, computer program product, and system for performing a hybrid dependency analysis is described. According to an embodiment, a method may include computing, by one or more computing devices, one or more dynamic hints based on a finite set of executions of a computer program. The method may further include performing, by the one or more computing devices, a hybrid dependence analysis of one or more statements of the computer program.

Abstract: A method for generating a binary executable of a program so that private symbols in a module are accessible from another module. In one embodiment, the method compiles a source program to an intermediate representation and scans the representation to find the private symbols in the program's modules. It then wraps a function around each private symbol. When called, the function returns an address of the private symbol, so that the other module can access the symbol from outside the module in which the symbol is found. At run time, a call is made to obtain the address of the function, which is then executed to obtain the address of the private symbol so that the symbol can be accessed. In another embodiment, a Just-In-Time compiler executes the wrapper functions and patches the executable program with the direct address of the private symbol to avoid a call to the wrapper function.

Abstract: A method, program, and apparatus for optimizing compiled code using a dynamic compiler. The method includes the steps of: generating intermediate code from a trace, which is an instruction sequence described in machine language; computing an offset between an address value, which is a base point of an indirect branch instruction, and a start address of a memory page, which includes a virtual address referred to by the information processing apparatus immediately after processing a first instruction; determining whether an indirect branch instruction that is subsequent to the first instruction causes processing to jump to another memory page, by using a value obtained from adding the offset to a displacement made by the indirect branch instruction; and optimizing the intermediate code by using the result of the determining step.

Abstract: A method to instrument program code for a virtual machine that comprises, in the course of loading a class to a virtual machine, adding code to the class to declare a field that corresponds to a field declared in a first bootstrap class.

Abstract: A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.

Abstract: A method for distributed static analysis of computer software applications, includes: statically analyzing instructions of a computer software application; identifying at least one entry point in the computer software application; assigning a primary agent to statically analyze the computer software application from the entry point; assigning a secondary agent to statically analyze a call site encountered by the primary agent and produce a static analysis summary of the call site; and presenting results of any of the static analyses via a computer-controlled output device.

Abstract: A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of processors, a plurality of code-blocks, and a marker associated with each code-block. The system may also include a special hardware register (code-block marker hardware register) in each processor for identifying the markers of the code-blocks executed by the processor, without changing any of the plurality of code-blocks.

Abstract: A method, system and computer program product for optimizing memory usage associated with duplicate string objects in a Java virtual machine. The method comprises scanning a heap of the Java virtual machine at the end of the start-up process of the virtual machine to identify duplicate strings associated with the virtual machine, storing the identified strings in a string cache file, and determining whether a new string that needs to be created during start-up already exists in the string cache file. The duplicate strings are added to an interned strings table. A reference to a duplicate string is returned if a string to be created is already in the string cache file.

Abstract: A compiler is provided that determines when the use of software transactional memory (STM) primitives may be optimized with respect to a set of collectively dominating STM primitives. The compiler analysis coordinates the use of variables containing possible shadow copy pointers to allow the analysis to be performed for both direct write and buffered write STM systems. The coordination of the variables containing the possible shadow copy pointers ensures that the results of STM primitives are properly reused. The compiler analysis identifies memory accesses where STM primitives may be eliminated, combined, or substituted for lower overhead STM primitives.

Abstract: To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.

Abstract: A method for providing a service in a user terminal device, in which the user terminal device downloads a service hub program, installs the service hub program, generates an icon container corresponding to the service hub program, displays the icon container, receives an input selecting the icon container, displays an application icon included in the icon container, and deletes a program and data installed in the user terminal device according to a change in status of the user terminal device.

Abstract: The purity of a function may be determined after examining the performance history of a function and analyzing the conditions under which the function behaves as pure. In some cases, a function may be classified as pure when any side effects are de minimis or are otherwise considered trivial. A control flow graph may also be traversed to identify conditions in which a side effect may occur as well as to classify the side effects as trivial or non-trivial. The function purity may be used to identify functions for memoization. In some embodiments, the purity analysis may be performed by a remote server and communicated to a client device, where the client device may memoize the function.

Abstract: One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).

Abstract: A system, method, and computer-readable medium, is described that finds similarities among programming applications based on semantic anchors found within the source code of such applications. The semantic anchors may be API calls, such as Java's package and class calls of the JDK. Latent Semantic Indexing may be used to process the application and semantic anchor data and automatically develop a similarity matrix that contains numbers representing the similarity of one program to another.

Abstract: Delayed insertion of safepoint related code is disclosed. Optimization processing is performed with respect to an intermediate representation of a source code. The optimized intermediate representation is analyzed programmatically to identify a safepoint and insert safepoint related code associated with the safepoint. In some embodiments, analyzing the optimized intermediate representation programmatically comprises determining where to place the safepoint within a program structure of the source code as reflected in the intermediate representation.

Abstract: A function may be memoized when a side effect is a read only side effect. Provided that the read only side effect does not mutate a memory object, the side effect may be considered as an input to a function for purity and memoization analysis. When a read only side effect may be encountered during memoization analysis, the read only side effect may be treated as an input to a function for memoization analysis. In some cases, such side effects may enable an impure function to behave as a pure function for the purposes of memoization.

Abstract: The claimed subject matter provides a method for detecting a data race. The method includes inserting a plurality of breakpoints into a corresponding plurality of program locations. Each of the program locations accesses a plurality of memory locations. Each of the program locations is selected randomly. The method also includes detecting one or more data races for the memory locations in response to one or more of the breakpoints firing. Additionally, the method includes generating a report describing the one or more data races.

Abstract: A method, system, and article of manufacture are disclosed for transforming a definition of a process for delivering a service. This service process definition is comprised of computer readable code. The method comprises the steps of expressing a given set of assumptions in a computer readable code; and transforming said process definition by using a processing unit to apply said assumptions to said process definition to change the configuration of the process definition. The process definition may be transformed by using factors relating to the specific context in or for which the process definition is executed. Also, the process definition may be transformed by identifying, in a flow diagram for the service process definition, flows to which the assumptions apply, and applying program rewriting techniques to those identified flows.

Abstract: Systems and methods for using memory usage to pinpoint sub-optimal code for gaming systems are provided herein. Memory usage characteristics, such as latency, cache misses, load-hit-store, memory address misuse, and wasted cache bandwidth are presented, preferably in a graphical format, to provide the developer with information for optimizing source code. A trace analysis is performed on source code undergoing optimization. Relevant data is extracted from the trace analysis, sorted as necessary, and presented to the user. The user may be presented with multiple results sorting mechanisms as well as ways to change the presentation of the results.

Abstract: A method, system, and program product for removing exception classes that match a pattern is disclosed. Exception classes are searched for those of the exception classes that match that pattern. The parent classes of matched exception classes are refactored to accept an exception type argument. Code that throws the matched exceptions is rewritten by replacing the exception class with the parent class and adding a corresponding exception type. Code that catches the thrown exceptions is rewritten by changing a catch clause to catch a parent exception class and inserting a case statement for the exception type in that catch clause. The matched exception classes are removed.

Abstract: Generating parallelized executable code from input code includes statically analyzing the input code to determine aspects of data flow and control flow of the input code; dynamically analyzing the input code to determine additional aspects of data flow and control flow of the input code; generating an intermediate representation of the input code based at least in part on the aspects of data flow and control flow of the input code identified by the static analysis and the additional aspects of data and control flow of the input code identified by the dynamic analysis; and processing the intermediate representation to determine portions of the intermediate representation that are eligible for parallel execution; and generating parallelized executable code from the processed intermediate representation.

Abstract: Method for communication between a central server and a computerized juke-box which operates in a conference mode, including: sending a header before any transaction, which includes the identity of the destination together, the identity of the emitter, and the size of the packets; responding from the server in the form of a data packet, each packet sent by the server being encoded using the identification code of the juke-box software; and receiving a data packet by the juke-box, which decodes the packet, simultaneously performs a check on the data received by the CRC method and sends an acknowledgement of receipt to the server indicating the accuracy of the information received, to allow it to prepare and send another packet to the juke-box.

Abstract: Embodiments of the present invention provide a method, system and computer program product for heuristically generated suggestions in static code analysis. In an embodiment of the invention, a method for heuristically suggesting an asset transition in a code analysis tool can include receiving from an end user a request to select an asset of a computer program subject to static code analysis by a code analysis tool and selecting in response and contemporaneously to the request, an asset from amongst many assets during static code analysis of a computer program in a code analysis tool. The method further can include determining a set of assets amongst the many assets historically selected by other users of the code analysis tool during static code analysis subsequent to a selection of the contemporaneously selected asset.

Abstract: A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if a compute node has three different types of processors with three different architecture implementations, the compiler may compile the source code and generate three versions of object code where each version is optimized for one of the three different processor types. After compiling the source code, the resultant executable code may contain the necessary information for selecting between the three versions. For example, when a program loader assigns the executable code to the processor, the system determines the processor's type and ensures only the optimized version that corresponds to that type is executed. Thus, the operating system is free to assign the executable code to any processor based on, for example, the current status of the processor (i.e.

Abstract: A partition-based method for diagnosing memory leaks in Java systems, comprising dividing heap memory of a Java virtual machine into a plurality of partitions based on a partition plan, wherein each partition has at least one partition owner; monitoring the status of the respective partitions to determine whether there is a partition in which the memory space is exhausted; and if there is a partition in which the memory space is exhausted, determining that the memory leak may occur in the partition and analyzing the partition to obtain leaked objects and objects related to the leaked objects. The present invention also provides a partition-based apparatus for diagnosing memory leak in Java systems.

Abstract: An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information. The blocks correspond to a program trace and containing a wait instruction. The wait instruction is sunk down the blocks globally to the end of the critical section using the color information and a dependence constraint on the wait instruction.

Abstract: A method, system, and article of manufacture are disclosed for transforming a definition of a process for delivering a service on a specified computing device. This service process definition is comprised of computer readable code. The method comprises the steps of expressing a given set of assumptions in a computer readable code; and transforming the definition by using a processing unit to apply the assumptions to the definition of the process to change the way in which the process operates. The definition of the process may be transformed by using factors relating to the specific context in or for which the definition is executed. Also, the definition may be transformed by identifying, in a flow diagram for the process, flows to which the assumptions apply, and applying program rewriting techniques to those identified flows.

Abstract: Methods, systems and computer program products are provided for creating and compiling source program code using one or more compiler directives a programming environment. The compiler directives may provide information on how to compile the source program code. The compiler directives may apply to the source program code under a given condition. The compiler directive may appear at the second or lower level of the source program code. The present invention may also provide a compiler that can determine the given condition of the source program code and apply the compiler directives based upon the determination of the given condition.

Abstract: Static analysis of a computer software application can be performed by applying a first level of abstraction to model a plurality of run-time objects, thereby producing a set of object abstractions. Static data-flow analysis of the computer software application can be performed using the set of object abstractions, thereby producing a first data-flow propagation graph. A data-flow bottleneck can be identified within the data-flow propagation graph. A second level of abstraction can be applied to model any of the run-time objects having in the set of object abstractions a corresponding object abstraction that is traceable to the data-flow bottleneck. The applying the second level of abstraction can decompose the corresponding object abstraction into a set of object abstractions, thereby modifying the set of object abstractions. Static data-flow analysis of the computer software application can be performed using the modified set of object abstractions.

Abstract: Systems and methods that enhance and balance a late binding and an early binding in a programming language, via supplying an option component to opt-in (or opt-out) late binding, and wherein a late binding is triggered based on a static type for the variable (e.g., object or a type/string.) Additionally, the variable is enabled to have different static types at different regions (e.g., a program fragment) of the programming language.

Abstract: A technique for prefetching data into a cache memory system includes prefetching data based on meta information indicative of data access patterns. A method includes tagging data of a program with meta information indicative of data access patterns. The method includes prefetching the data from main memory at least partially based on the meta information, by a processor executing the program. In at least one embodiment, the method includes generating an executable at least partially based on the meta information. The executable includes at least one instruction to prefetch the data. In at least one embodiment, the method includes inserting one or more instructions for prefetching the data into an intermediate form of program code while translating program source code into the intermediate form of program code.

Abstract: A compiled program has an advanced-load instruction and a load-checking atomic section. The load-checking atomic section follows the advanced-load instruction in the compiled program. The advanced-load instruction, when executed, loads a value from a shared memory address. The load-checking atomic section includes a check instruction for checking the validity of the shared memory address.

Abstract: Disclosed herein is a method of optimizing an executable program to improve instruction cache hit rate when executed on a processor. A method of predicting instruction cache behavior of an executable program is also disclosed. According to further aspects of the present invention, there is provided a software development tool product comprising code which when executed on a computer will perform the method of optimizing an executable program. A linker product and a computer program are also disclosed.

Abstract: A compilation method and mechanism for parallelizing program code. A method for compilation includes analyzing source code and identifying candidate code for parallelization. Having identified one or more suitable candidates, the profitability of parallelizing the candidate code is determined. If the profitability determination meets a predetermined criteria, then the candidate code may be parallelized. If, however, the profitability determination does not meet the predetermined criteria, then the candidate code may not be parallelized. Candidate code may comprises a loop, and determining profitability of parallelization may include computing a probability of transaction failure for the loop. Additionally, a determination of an execution time of a parallelized version of the loop is made. If the determined execution time is less than an execution time of a non-parallelized version of said loop by at least a given amount, then the loop may be parallelized.

Abstract: A lock-clustering compiler is configured to compile program code for a software transactional memory system. The compiler determines that a group of data structures are accessed together within one or more atomic memory transactions defined in the program code. In response to determining that the group is accessed together, the compiler creates an executable version of the program code that includes clustering code, which is executable to associate the data structures of the group with the same software transactional memory lock. The lock is usable by the software transactional memory system to coordinate concurrent transactional access to the group of data structures by multiple concurrent threads.

Abstract: Disclosed herein are methods and systems for using on stack replacement for optimization of software. A source code is compiled into an unoptimized code on a computing device. The unoptimized code is then executed on a computing device. A hot count is incremented. It is then determined whether a function within the unoptimized code is hot. If a function is determined to be hot, an OSR triggering code is inserted at a back edge of each loop within the function. The OSR triggering code is configured to trigger OSR at a loop depth that is less than the hot count.

Abstract: A deadlock detection method and computer system for parallel programs. A determination is made that a lock of the parallel programs is no longer used in a running procedure of the parallel programs. A node corresponding to the lock that is no longer used, and edges relating to the lock that is no longer used, are deleted from a lock graph corresponding to the running procedure of the parallel programs in order to acquire an updated lock graph. The lock graph is constructed according to a lock operation of the parallel programs. Deadlock detection is then performed on the updated lock graph.

Abstract: Memoization may be deployed using a configuration file or database that identifies functions to memorize, and in some cases, includes input and result values for those functions. At compile time, functions defined in the configuration file may be captured and memoized. During compilation or other pre-execution analysis, the executable code may be modified or otherwise decorated to include memoization code. The memoization code may store results from a function during the first execution, then merely look up the results when the function may be called again. The memoized value may be stored in the configuration file or in another data store. In some embodiments, the modified executable code may operate in conjunction with an execution environment, where the execution environment may optionally perform the memoization.

Abstract: A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to externally stored static elements for a document in a document editor and provide a method, system and computer program product for moving static elements for a document between an external file and the document in a document editor. A data processing system for moving static elements for a document between an external file and the document in a document editor can include an automated de-externalization and re-externalization processor coupled to a document editor. The automated de-externalization and re-externalization processor can include program code enabled both to replace static elements in a subject document with static element references while storing replaced static elements in entries in an external file, and also to replace static element references in the subject document with corresponding static elements stored in the entries in the external file.