Abstract: Systems and methods for optimizing code may use transactional memory to optimize one code section by forcing another code section to execute atomically. Application source code may be analyzed to identify instructions in one code section that only need to be executed if there exists the possibility that another code section (e.g., a critical section) could be partially executed or that its results could be affected by interference. In response to identifying such instructions, alternate code may be generated that forces the critical section to be executed as an atomic transaction, e.g., using best-effort hardware transactional memory. This alternate code may replace the original code or may be included in an alternate execution path that can be conditionally selected for execution at runtime. The alternate code may elide the identified instructions (which are rendered unnecessary by the transaction) by removing them, or by including them in the alternate execution path.

Abstract: A system and method are provided for inlining a program call between processes executing under separate ISAs (Instruction Set Architectures) within a system virtual machine. The system virtual machine hosts any number of virtual operating system instances, each of which may execute any number of applications. The system virtual machine interprets or dynamically compiles not only application code executing under virtual operating systems, but also the virtual operating systems. For a program call that crosses ISA boundaries, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the virtual ISA of the code. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions are configured and executed (or emulated) to perform as they would within the virtual ISA.

Abstract: One embodiment of the present invention sets forth a system that allows a software developer to perform shader debugging and performance tuning. The system includes an interception layer between the software application and the application programming interface (API). The interception layer is configured to intercept and store source code versions of the original shaders included in the application. For each object in the frame, the interception layer makes shader source code available to the developer, so that the developer can modify the source code as needed, re-compile only the modified shader source code, and run the application. Consequently, shader debugging and performance tuning may be carried out in a manner that is more efficient and effective relative to prior art approaches.

Abstract: Described is a method and system for optimizing a code layout for execution on a processor including internal and/or external cache memory. The method and system includes executing a program having a first layout, generating at least one memory access parameter for the program, the memory access parameter being based on a cache memory of a computing system on which the program is designed to run and constructing a second layout for the program as a function of the at least one memory access parameter.

Abstract: An error handling operation for checking of an array access in program code is modified during compilation thereof. A sequentially arranged null checking operation and array bounds checking operation for the array access are located. The array bounds checking operation has a corresponding error handling operation operable for setting an array bounds error. The located sequentially arranged null checking operation is removed. The corresponding error handling operation for the located sequentially arranged array bounds checking operation is modified to perform the removed null checking operation during execution of the program code.

Abstract: A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.

Abstract: A method and apparatuses for allowing additional tail call optimizations. The compiler generates both optimized and non-optimized code for tail call candidates. At a later time when there is more information (e.g. regarding program bounds), a decision and a modification to the executable code is made, implementing one of the two earlier codes.

Abstract: Compile-time context information is captured and provided to a runtime binder for dynamic features in programming languages. For example, a C# run-time binder uses the information to perform a run-time bind with semantics matching the compiler's binding behavior. Dynamic programming language features supported relate to compound operations, events, delegates, member accessibility, dynamic-typed objects, structs passed by ref, arguments passed by name rather than position, extension methods, conditionally compiled methods, literal arguments, overflow checking, dynamic indexed properties, dynamic method groups, and static method groups.

Abstract: One embodiment constructs a graph comprising one or more parameter nodes and one or more transformation nodes, wherein: each parameter node represents one or more parameters; and each transformation node represents one or more transformations; and sequentially applies from a lowest level to a highest level of the graph, the one or more parameters represented by each parameter node and the one or more transformations represented by each transformation node to a static resource to determine one or more versions of the static resource.

Abstract: We show that register allocation can be viewed as solving a collection of puzzles. We model the register file as a puzzle board and the program variables as puzzle pieces. We model pre-coloring by letting some of the puzzle pieces be already immovably placed on the puzzle board, and we model register aliasing by letting pieces have a plurality widths. For a wide variety of computer architectures, we can solve the puzzles in polynomial time. Puzzle solving is independent of spilling, that is, puzzle solving can be combined with a wide variety of approaches to spilling.

Abstract: Program converting methods, apparatus and systems including a code analysis unit for performing lexical and syntactic analyses of a source code of an execution program, an optimization unit for transforming this execution program, and an output code generation unit for converting the transformed execution program into a machine language code. In addition, this optimization unit detects a calling procedure and a called procedure in a procedure call of this execution program analyzed by the code analysis unit, guards an evaluation of an argument described in the called procedure under a predetermined evaluation condition, and transforms the execution program so that the evaluation is performed when referring to this argument.

Abstract: In one embodiment, the present invention includes a method for constructing a data dependency graph (DDG) for a loop to be transformed, performing statement shifting to transform the loop into a first transformed loop according to at least one of first and second algorithms, performing unimodular and echelon transformations of a selected one of the first or second transformed loops, partitioning the selected transformed loop to obtain maximum outer level parallelism (MOLP), and partitioning the selected transformed loop into multiple sub-loops. Other embodiments are described and claimed.

Abstract: An information handling system (IHS) employs a compiler methodology that seeks to improve the efficiency of code that executes in a multi-core processor. The compiler receives source code and converts the source code for execution using data parallel select operations that perform well in a single instruction multiple data (SIMD) environment. The compiler of the IHS may apply one or several optimization processes to the code to increase execution efficiency in a parallel processing environment.

Abstract: Systems and methods are provided for generating high-level program code of a rule-based application for interpreting and executing business rules. In one exemplary embodiment, a method is provided that comprises retrieving high-level program code capable of performing the functionality of a business rule called by the rule-based application, wherein the high-level program code includes an annotated set of instructions for the dynamic generation of generated code. The method may also comprise processing the annotated set of instructions with a generator component to create generated code from the high-level program code, mapping the generated code to the called business rule, and utilizing the generated code to execute the functionality of the called business rule.

Abstract: An information handling system (IHS) employs a compiler methodology that seeks to improve the efficiency of code that executes in a multi-core processor. The compiler receives source code and converts the source code for execution using data parallel select operations that perform well in a single instruction multiple data (SIMD) environment. The compiler of the IHS may apply one or several optimization processes to the code to increase execution efficiency in a parallel processing environment.

Abstract: A hardware Java accelerator is provided to implement portions of the Java virtual machine in hardware in order to accelerate the operation of the system on Java bytecodes. The Java hardware accelerator preferably includes Java bytecode translation into native CPU instructions. The combination of the Java hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java programs for use in commercial appliances.

Abstract: A method for modeling and simulating a system comprising first and second interrelated components is disclosed. The method comprises modeling the behavior of said first and second components using first and second specifications. Each of said first and second specifications includes a functional specification and an associated simulation element. The method further comprises simulating the behavior of said first and second components using said first and second specifications. The simulation elements communicate with one another to provide a simulation system.

Abstract: A computer implemented method, computer program product, and data processing system for reducing the number of inner classes in a compiled computer program written in an object-oriented programming language. An outer class of the compiled computer program is received, wherein the outer class contains an inner class, wherein the outer class comprises instructions to create an instance of an inner class. The instance is to be used as one of a callback, a listener command, a set of instructions by which an object instance of the inner class transfers information to the corresponding containing instance of the outer class, and combinations thereof. A transformation of the outer class is performed by moving methods of the inner class, as well as their contained instructions, into the outer class. The behavior of the compiled computer program remains unchanged.

Abstract: A method includes, using a static analysis performed on code, analyzing the code to determine a set of unchanged objects and modifying the code to exercise a singleton-pattern technique for one or more members of the set of unchanged objects. The method also includes outputting the modified code. Apparatus and program products are also disclosed. Another method includes accessing code from a client, and in response to any of the code being source code, compiling the source code into object code until all the code from the client comprises object code. The method further includes, using a static analysis performed on the object code, analyzing the object code to determine a set of unchanged objects and modifying the object code to exercise a singleton-pattern technique for one or more members of the set of unchanged objects. The method additionally includes returning the modified object code to the client.

Abstract: A device generates code with a technical computing environment (TCE) based on a model and information associated with a target processor, registers an algorithm with the TCE, automatically sets optimization parameters applied during generation of the code based on the algorithm, executes the generated code, receives feedback based on execution of the generated code, and uses the feedback to automatically update the optimization parameters and to automatically regenerate the code with the TCE until an optimal code is achieved for the target processor.

Abstract: A method and system of detecting vulnerabilities in source code. Source code is parsed into an intermediate representation. Models (e.g., in the form of lattices) are derived for the variables in the code and for the variables and/or expressions used in conjunction with routine calls. The models are then analyzed in conjunction with pre-specified rules about the routines to determine if the routine call posses one or more of pre-selected vulnerabilities.

Abstract: Systems and methods are described that facilitate validating electronic document conversion chain design in real time, as a designer edits a conversion chain that converts a document collection between formats. Waypoints are inserted into the document conversion chain by associating validation specifications with selected conversion components in the chain. AS the conversion chain is executed on a document collection, the validation specification is executed on all documents in the collection when a selected conversion component is executed. Validation results are returned to indicate to the designer which documents were successfully converted by the component and which were not. The designer can then modify the conversion chain, which is re-executed, and validation results are again presented to the designer for comparison to the pre-modification validation results. The designer can then approve or reject the modification(s) depending on whether document validation is improved thereby.

Abstract: Exemplary embodiments of the present invention comprise an algorithm described herein that utilizes a technique to shrink a set of potentially reachable elements to a close approximation of the actually reachable elements within a software application by closely approximating how the application executes at runtime. The algorithm attempts to identify all of the reachable elements of an object-oriented software application by starting with the entry points into the application and thereafter progressively determining all of the software elements within the application that are reachable. The algorithm instantiates application objects in the same way they would be instantiated at runtime and passes references to these objects from one method and field to the next; emulating as closely as possible object instantiation performed by the application at runtime.

Abstract: A method for optimizing a code section prior to performing register allocation for variables referenced in the plurality of computer instructions. The method includes performing at least one of a full prematerialization or a partial prematerialization for a variable in the plurality of computer instructions. The full prematerialization replaces the variable in every use of the variable in the plurality of computer instructions with one or more variants of the variable and replaces a definition of the variable with a nop instruction. The partial prematerialization replaces some but not all occurrences of the variable in uses of the variable in the plurality of computer instructions with one or more variants of the variable without replacing the definition of the variable with the nop instruction.

Abstract: A method for analyzing a program is provided. The method includes, determining an object type that may exist at an execution point of the program, wherein this enables determination of possible virtual functions that may be called; creating a call graph at a main entry point of the program; and recording an outgoing function call within a main function. The method also includes analyzing possible object types that may occur at any given instruction from any call path for virtual calls, wherein possible object types are determined by tracking object types as they pass through plural constructs; and calling into functions generically for handling specialized native runtime type information.

Abstract: A compiler utility assigns memory locations to alias-free variables within a computer program. The compiler utility allocates memory keys for the alias-free variables, such that access to the memory locations of the alias-free variables is granted to blocks of code that have knowledge of the memory keys. In response to a command by the user, the compiler generates code to detect violations of alias assumptions during execution of the computer program. During the compiling process, the compiler adds the generated code for detecting violations of alias assumptions to the compiled computer program.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: A method and computer readable medium for automatic replacement of object classes in a library with custom classes to improve program efficiency. The method begins with static analysis preformed on a program containing a plurality of objects in order to determine type-correctness constraints and to detect unused functionality in one or more of the objects to be replaced. The plurality of objects is instrumented to detect usage patterns of functionality in one or more objects. Customized classes are generated based upon the static analysis and usage patterns detected. Bytecode is rewritten which is used for generating classes. The present invention provides transparency in the replacement of the objects.

Abstract: A method and computer readable medium for automatic replacement of object classes in a library with custom classes to improve program efficiency. The method begins with static analysis preformed on a program containing a plurality of objects in order to determine type-correctness constraints and to detect unused functionality in one or more of the objects to be replaced. The plurality of objects is instrumented to detect usage patterns of functionality in one or more objects. Customized classes are generated based upon the static analysis and usage patterns detected. Bytecode is rewritten which is used for generating classes. The present invention provides transparency in the replacement of the objects.

Abstract: In a multi-threaded computer system that uses transactional memory, object fields accessed by only one thread are accessed by regular non-transactional read and write operations. When an object may be visible to more than one thread, access by non-transactional code is prevented and all accesses to the fields of that object are performed using transactional code. In one embodiment, the current visibility of an object is stored in the object itself. This stored visibility can be checked at runtime by code that accesses the object fields or code can be generated to check the visibility prior to access during compilation.

Abstract: A system and method for assessing performance of a software application migrated to a grid infrastructure is provided. The system comprises a grid code analyzer for generating a directed acyclic graph (DAG) corresponding to the software application by performing static and dynamic analysis; a grid task generator for reducing the DAG generated by the grid code analyzer; and a grid simulator for simulating performance of the software application on one or more predetermined grid infrastructures. The grid simulator accepts the reduced DAG as input and produces performance data as output.

Abstract: A mechanism for replacing memory pointers with implicit pointers is disclosed. A method of embodiments of the invention includes determining a memory pointer in a source code compiling on a computer system. The memory pointer is associated with a first value in the source code and serves as a referencing link to a second value in memory. The method further includes replacing the memory pointer with an implicit pointer as the memory pointer is optimized away during code optimization of the source code such that the implicit pointer is provided in a compiler-generated debug output to serve as an implicit reference link between the first value and second value. The implicit reference link was once provided as an explicit reference link by the memory pointer before getting optimized away.

Abstract: A method (and system) for performing an emulation of an operation of a target computing system, includes interpreting a target instruction, recognizing an unused capacity of a host system when the host system is interpreting the instruction, and performing a translation of the instruction without increasing a time of interpreting the instruction.

Abstract: A compiler has the capability to selectively compile individual portions of a compilable code module for optimum execution performance or for serviceability. In one aspect, individual portions, such as procedures (being less than the entire module) are selectively optimized. In another aspect, debug activity data is used for determining whether or not to optimize compiled code. It is optionally possible to support one or more levels of partial selective optimization.

Abstract: An improved architecture for a program code conversion apparatus and method for generating intermediate representations for program code conversion. The program code conversion apparatus determines which types of IR nodes to generate in an intermediate representation (IR) of subject code (10) to be translated. Depending upon the particular subject and target computing environments involved in the conversion, the program code conversion apparatus utilizes either base nodes, complex nodes, polymorphic nodes, and architecture specific nodes, or some combination thereof, in generating the intermediate representation.

Abstract: A software transactional memory system is described which utilizes decomposed software transactional memory instructions as well as runtime optimizations to achieve efficient performance. The decomposed instructions allow a compiler with knowledge of the instruction semantics to perform optimizations which would be unavailable on traditional software transactional memory systems. Additionally, high-level software transactional memory optimizations are performed such as code movement around procedure calls, addition of operations to provide strong atomicity, removal of unnecessary read-to-update upgrades, and removal of operations for newly-allocated objects. During execution, multi-use header words for objects are extended to provide for per-object housekeeping, as well as fast snapshots which illustrate changes to objects. Additionally, entries to software transactional memory logs are filtered using an associative table during execution, preventing needless writes to the logs.

Abstract: A method and computer program product for providing an optimization for a most derived object during compile time are provided. The optimization determines whether a most derived class object is present during a compile time. Also, the optimization utilizes the most derived class object to obtain a location of a virtual base for the most derived class object during the compile time, and provides the virtual base of the most derived class object during the compile time. The method is executed for a constructor and/or a destructor. The constructor or destructor contains arguments which require conversion to a base type, and the conversion is performed at compile-time instead of at runtime.

Abstract: A technique is provided for eliminating maximum and minimum expressions within loop bounds are provided. A loop in a code is identified. The loop is determined to meet conditions, which require an upper loop bound and a lower loop bound to contain maximum and minimum expressions, loop-invariant operands, a predetermined size for a code size, and a total number of instructions to be greater than a predetermined constant. A profitability of loop versioning is determined based on a performance gain of a fast version of the loop, a probability of executing the fast version of the loop at runtime, and an overhead for performing loop versioning. A pair of lower loop bound and upper loop bound values resulting in a constant number is identified. A loop iteration value is checked to be a non-zero constant. Branches are identified, and loop versioning is performed to generate a versioned loop.

Abstract: Creating and executing platform portable code. A method includes declaring an object as being a dynamic object in a program. The program is a program compiled using a static language, except that the dynamic object is excluded from static analysis on the object when the program is compiled. The dynamic object includes a dependent call to a platform specific API. The platform specific API is available on one or more platforms to which a compiled version of the program will be deployed, but not available on one or more other platforms to which the compiled version of the program will be deployed.

Abstract: A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted into virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.

Abstract: A web page is generated by applying a partial evaluation technique. In one embodiment, at design time, a page designer enables a dynamic version of a page specification program to be generated, such as by way of a page customization interface. This dynamic version can be executed during the design process, with page customization choices evaluated in a dynamic manner. The parts of the page specification that can be evaluated to static form at design time are identified, and the program is partially evaluated, with the identified parts transformed to static form. The remaining dynamic parts of the page specification program are executed at request time, resulting in a generation of the page to be provided for display over the network. In general, different parts of a page specification program may be selected for evaluation at different times, and there may be more than two phases of evaluation.

Abstract: A computer program product and computer system for implementing a method of compiler optimisation of source code during compilation of the source code in a computer environment. The compiler optimisation of source code includes: recasting two algebraic expressions into a form of one or more token pairs arranged sequentially in a string, each token pair including an operator followed by an operand; reducing the strings in accordance with a set of predetermined simplifying rules; and comparing the reduced strings by matching to detect an equivalence of the two algebraic expressions.

Abstract: One aspect of the invention includes a method of address expression optimization of source-level code. The source-level code describes the functionality of an application to be executed on a digital device. The method comprises first inputting first source-level code that describes the functionality of the application into optimization system. The optimization system then transforms the first source-level into a second source level that has fewer nonlinear operations than the first source-level code.

Abstract: Implementation size of a software package implementation can be determined by determining implementation sizes of modules, determining tasks to be implemented, determining a complexity factor, and calculating the implementation size based on the modules, tasks, and complexity factor. Implementation size of a software package implementation can be determined using a sizing framework. The sizing framework can comprise a repository of modules and functionality provided by the modules, a standard album of tasks, effort information for the tasks, and a repository of complexity values. A sizing tool can determine an implementation size of a software package implementation. The sizing tool can comprise user-interface pages for receiving a selection of modules, for receiving a selection of functionality, for receiving a selection of tasks to be implemented for the software package, and for receiving a selection of complexity values. The sizing tool can calculate the implementation size based on the selections.

Abstract: Mechanisms for aggressively optimizing computer code are provided. With these mechanisms, a compiler determines an optimization to apply to a portion of source code and determines if the optimization as applied to the portion of source code will result in unsafe optimized code that introduces a new source of exceptions being generated by the optimized code. In response to a determination that the optimization is an unsafe optimization, the compiler generates an aggressively compiled code version, in which the unsafe optimization is applied, and a conservatively compiled code version in which the unsafe optimization is not applied. The compiler stores both versions and provides them for execution. Mechanisms are provided for switching between these versions during execution in the event of a failure of the aggressively compiled code version. Moreover, predictive mechanisms are provided for predicting whether such a failure is likely.

Abstract: The present relates to a method for verifying privileged and subject-executed code within a program, the method further comprising the steps of constructing a static model of a program, identifying checkPermission nodes that are comprised within the invocation graph, and performing a fixed-point iteration, wherein each determined permission set is propagated backwards across the nodes of the static model until a privilege-asserting code node is reached. The method further comprises the steps of associating each node of the invocation graph with a set of Permission allocation sites, analyzing each identified privilege-asserting code node and subject-executing code node to determine the Permission allocation site set that is associated with each privilege-asserting code node and subject-executing code node, and determining the cardinality of a Permission allocation-site set that is associated with each privilege-asserting code node and subject-executing code node.

Abstract: Compiler device optimizes a program by changing an order of executing instructions.

Abstract: A system and method for minimizing register spills during compilation. A compiler reallocates spilled variables from stack memory to other available registers. Although a corresponding register file may not have available registers for storage, the compiler identifies available registers in other locations for storage. The compiler identifies available registers in an alternate register file, wherein the alternate register file may be a floating-point register file which is then used for spilled integer variables. Other instruction type combinations between spilled variables and alternate register files are possible. When an available register within the alternate register file is identified, the compiler modifies the program instructions to allocate the corresponding spilled variable to the available register.

Abstract: The present invention provides a method and system for optimization of an intermediate representation in a graphical modeling environment. A first intermediate representation is provided. At least one optimization technique is applied to the first intermediate representation. A second intermediate representation is generated responsive to the application of the at least one optimization technique to the first intermediate representation.

Abstract: A system is disclosed for compiling program code. The system provides a compiler that includes a static verifier and a runtime verifier. The static verifier performs static checks on the program code and produces object code corresponding to the program code. The runtime verifier receives the object code and performs dynamic checks on the object code in a platform dependent environment. The resulting object code can subsequently be executed.