Integrated With Dissimilar Structures On A Common Substrate Patents (Class 977/701)
  • Publication number: 20090038827
    Abstract: This invention provides a better means to achieve affordable solar energy, as well as other technologies. It does so by improving control grids (for addressing and alignment) in solar concentrators and optical equipment in general. Thus troublesome and expensive grid material like Indium Tin Oxide (ITO) can be replaced by more manageable, hardier, and in the long run relatively less expensive nanotubes; or a carbon grid simply laid down by ordinary photocopy (Xerographic) reduction techniques. The instant invention relates to improvements in the control (addressing and alignment) grid for Solar Energy Concentrators; and similar equipment such as Optical Switches [e.g. cf. M. Rabinowitz U.S. Pat. No. 6,976,445]; and Display devices such as Dynamic Reflection, Illumination, and Projection equipment [e.g. cf. M. Rabinowitz U.S. Pat. No. 7,130,102]; as well as display equipment in general.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 12, 2009
    Inventor: Mario Rabinowitz
  • Patent number: 7476787
    Abstract: Systems and methods for addressable field enhancement microscopy are provided. In an embodiment, a nanoscale array of islands may be illuminated with an electromagnetic signal and addressed to differentiate signals from different islands of the nanoscale array. The differentiated signals originating from illuminating the nanoscale array may be applied to microscopy of a specimen.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: January 13, 2009
    Assignee: STC.UNM
    Inventors: James L. Thomas, Wolfgang G. Rudolph
  • Patent number: 7472576
    Abstract: Nanometrology device standards and methods for fabricating and using such devices in conjunction with scanning probe microscopes are described. The fabrication methods comprise: (1) epitaxial growth that produces nanometer sized islands of known morphology, structural, morphological and chemical stability in typical nanometrology environments, and large height-to-width nano-island aspect ratios, and (2) marking suitable crystallographic directions on the device for alignment with a scanning direction.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: January 6, 2009
    Assignee: State of Oregon Acting By and Through The State Board of Higher Education On Behalf of Portland State University
    Inventor: Peter Moeck
  • Patent number: 7413598
    Abstract: The present invention discloses a mold and a method of manufacturing the mold. The mold includes a mold matrix and a number of boron nitride nanotubes sintered together with the mold matrix. Each boron nitride nanotube capsules a number of fullerenes therein respectively. The mold further includes an amount of noble metal powder sintered together with the mold matrix and the boron nitride nanotubes. The fullerenes preferably include C60 molecules. In addition, the method for manufacturing a mold includes the steps of: providing a number of boron nitride nanotubes, each boron nitride nanotube capsuling a number of fullerenes therein respectively; mixing a mold matrix with the boron nitride nanotubes capsuling the fullerenes to form a complex; molding the complex to form a mold preform; and sintering the mold preform, thereby attaining a mold.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: August 19, 2008
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Charles Leu
  • Patent number: 7402829
    Abstract: A silicon/lithium battery can be fabricated from a silicon substrate. This allows the battery to be produced as an integrated unit on a chip. The battery includes a silicon anode formed from sub-micron diameter pillars of silicon fabricated on an n-type silicon wafer. The battery also includes a cathode including lithium.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: July 22, 2008
    Assignee: Nexeon Ltd.
    Inventor: Mino Green
  • Patent number: 7391081
    Abstract: A method of simultaneously fabricating at least two semiconductor devices, at least bone of which is a nanocrystal memory and at least one of which is a non-nanocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions for each of the semiconductor devices being fabricated. The substrate is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: June 24, 2008
    Assignee: Atmel Corporation
    Inventor: Bohumil Lojek
  • Patent number: 7391018
    Abstract: The present invention generally discloses the use of a nanostructured non-silicon thin film (such as an alumina or aluminum thin film) on a supporting substrate which is subsequently coated with an active layer of a material such as silicon or tungsten. The base, underlying non-silicon material generates enhanced surface area while the active layer assists in incorporating and transferring energy to one or more analytes adsorbed on the active layer when irradiated with a laser during laser desorption of the analyte(s). The present invention provides substrate surfaces that can be produced by relatively straightforward and inexpensive manufacturing processes and which can be used for a variety of applications such as mass spectrometry, hydrophobic or hydrophilic coatings, medical device applications, electronics, catalysis, protection, data storage, optics, and sensors.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: June 24, 2008
    Assignee: Nanosys, Inc.
    Inventors: Chunming Niu, Robert Hugh Daniels, Robert S. Dubrow, Jay L. Goldman
  • Patent number: 7390947
    Abstract: A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Amlan Majumdar, Justin K. Brask, Marko Radosavljevic, Suman Datta, Brian S. Doyle, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Robert S. Chau, Uday Shah, James Blackwell
  • Publication number: 20080115831
    Abstract: An electrolyte composition for a dye sensitized solar cell according to one embodiment includes a first polymer or a non-volatile liquid compound having a weight average molecular weight of less than or equal to 500, a second polymer having a weight average molecular weight of more than or equal to 2000, inorganic nano-particles, and a redox derivative.
    Type: Application
    Filed: January 30, 2007
    Publication date: May 22, 2008
    Inventors: Moon-Sung Kang, Ji-Won Lee, Wha-Sup Lee, Kwang-Soon Ahn, Jae-Man Choi, Jae-Kwan Lee, Moon-Seok Kwon, Byong-Cheol Shin, Soo-Jin Moon, Joung-Won Park
  • Publication number: 20080107533
    Abstract: A system for manufacturing an integrally bladed rotor is provided. This system includes a ring component, wherein the ring component further includes at least one metal matrix composite and a continuous radially outwardly facing blade conical surface; an airfoil component, wherein the at least one airfoil component has been created from a single, unitary piece of material and further includes a plurality of individual airfoil blades and a continuous radially inwardly facing blade conical surface; and inertia welding means for frictionally engaging under an axially applied weld load the ring component and the airfoil component to effect an inertia weld therebetween along the conical surfaces.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Charles W. Carrier, Chen-yu J. Chou
  • Publication number: 20080107532
    Abstract: A system for manufacturing an integrally bladed rotor is provided. This system includes a ring component, wherein the ring component further includes at least one metal matrix composite and a continuous radially outwardly facing conical surface; an airfoil component, wherein the airfoil component further includes a plurality of individual airfoil blades, wherein at least a portion of each individual airfoil blade has been reinforced with at least one metal matrix composite, and wherein each of the plurality of airfoil blades further includes a radially inwardly facing blade conical surface; and inertia welding means for frictionally engaging under an axially applied weld load the ring component and the airfoil component to effect an inertia weld therebetween along the conical surfaces.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Charles W. Carrier, Chen-yu J. Chou
  • Publication number: 20080107531
    Abstract: A system for manufacturing an integrally bladed rotor is provided. This system includes a ring component, wherein the ring component further includes at least one metal matrix composite and a plurality of radially outwardly facing blade conical surfaces; an airfoil component, wherein the airfoil component further includes: a plurality of individual airfoil blades, wherein each of the plurality of airfoil blades further includes a radially inwardly facing blade conical surface; and inertia welding means for frictionally engaging under an axially applied weld load the ring component and the airfoil component to effect an inertia weld therebetween along the conical surfaces.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Chen-yu J. Chou, Charles W. Carrier
  • Patent number: 7312095
    Abstract: An electronic system for selectively detecting and identifying a plurality of chemical species, which comprises an array of nanostructure sensing devices, is disclosed. Within the array, there are at least two different selectivities for sensing among the nanostructure sensing devices. Methods for fabricating the electronic system are also disclosed. The methods involve modifying nanostructures within the devices to have different selectivity for sensing chemical species. Modification can involve chemical, electrochemical, and self-limiting point defect reactions. Reactants for these reactions can be supplied using a bath method or a chemical jet method. Methods for using the arrays of nanostructure sensing devices to detect and identify a plurality of chemical species are also provided.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: December 25, 2007
    Assignee: Nanomix, Inc.
    Inventors: Jean-Christophe P. Gabriel, Philip G. Collins, Keith Bradley, George Gruner
  • Patent number: 7258838
    Abstract: A solid state nanopore device including two or more materials and a method for fabricating the same. The device includes a solid state insulating membrane having an exposed surface, a conductive material disposed on at least a portion of the exposed surface of the solid state membrane, and a nanopore penetrating an area of the conductive material and at least a portion of the solid state membrane. During fabrication a conductive material is applied on a portion of a solid state membrane surface, and a nanopore of a first diameter is formed. When the surface is exposed to an ion beam, material from the membrane and conductive material flows to reduce the diameter of the nanopore. A method for evaluating a polymer molecule using the solid state nanopore device is also described. The device is contacted with the polymer molecule and the molecule is passed through the nanopore, allowing each monomer of the polymer molecule to be monitored.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 21, 2007
    Assignee: President and Fellows of Harvard College
    Inventors: Jiali Li, Derek M. Stein, Gregor M. Schurmann, Gavin M. King, Jene Golovchenko, Daniel Branton, Michael Aziz
  • Patent number: 7214611
    Abstract: The present invention first obtains a nano-metal line by an e-beam lithography and an electroless plating, and imprints the line into a material with low-K to obtain a damascene metal line with low cost and high throughput, as a future solution for a metallization process for a general low-K metal damascene structure through CMP.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: May 8, 2007
    Assignee: National Tsing Hua University
    Inventors: Jen Fu Liu, Yung Jen Hsu, Jiann Heng Chen, Fon Shan Huang
  • Patent number: 7183622
    Abstract: An apparatus may include a first substrate, one or more microelectromechanical systems (MEMS) coupled to the first substrate, a second substrate coupled with the first substrate, and one or more passive components coupled to the second substrate. A method may include aligning a first substrate having one or more MEMS coupled thereto and a second substrate having one or more passive components coupled thereto, and coupling the aligned substrates.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: John Heck, Qing Ma, Eyal Bar-Sadeh
  • Patent number: 7183180
    Abstract: A method of simultaneously fabricating at least two semiconductor devices, at least one of which is a nanocrystal memory and at least one of which is a non-nonocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions for each of the semiconductor devices being fabricated. The substrate is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: February 27, 2007
    Assignee: Atmel Corporation
    Inventor: Bohumil Lojek