Abstract: Semiconductor devices may be fabricated using nanowires. In an example embodiment, a conductive gate may be used to control conduction along the nanowires, in which case one of the contacts is a drain and the other a source. The nanowires may be grown in a trench or through-hole in a substrate or in particular in an epitaxial layer on substrate. In another example embodiment, the gate may be provided only at one end of the nanowires. The nanowires can be of the same material along their length; alternatively different materials can be used, especially different materials adjacent to the gate and between the gate and the base of the trench.

Abstract: A mounting method of the present invention includes the steps of: (I) disposing a first liquid in a first region provided on one principal surface of a substrate; (II) bringing a pillar-like member as an anisotropically-shaped member, disposed on one principal surface of a transfer substrate in a predetermined orientation, into contact with the first liquid disposed in the first region, so as to move the pillar-like member to a region of the first liquid; and (III) removing the first liquid from the substrate.

Abstract: A semiconductor integrated circuit (IC) chip includes an IC chip body and a nano-structure-surface passivation film. The IC chip body has at least one surface. The nano-structure-surface passivation film is formed on the at least one surface. The nano-structure-surface passivation film including nano-particles and a carrier resin protects the IC chip body from encountering any external interference. The IC chip body further has a plurality of fingerprint sensing members for sensing a whole fingerprint or a partial fingerprint.

Abstract: The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control gate formed on the memory cell. The memory cell includes a first tunneling oxide layer formed on the substrate; a second tunneling oxide layer formed on the first tunneling oxide layer; and a control oxide layer formed on the second tunneling oxide layer. The control oxide layer includes the nanocrystals. The second tunneling oxide layer, having an aminosilane group the increases electrostatic attraction, may be hydrophilic, enabling the formation of a monolayer of the nanocrystals.

Abstract: To provide a carbon nanotube device capable of efficiently exerting various electrical or physical characteristics of a carbon nanotube, the present invention provides: a carbon nanotube device, in which a carbon nanotube structure layer having a network structure in which plural carbon nanotubes mutually cross-link, is formed in an arbitrary pattern on a surface of a base body; and a method of manufacturing the carbon nanotube device with which the carbon nanotube can be suitably manufactured.

Abstract: A nano-molding process including an imprint process that replicates features sizes less than 7 nanometers. The nano-molding process produces a line edge roughness of the replicated features that is less than 2 nanometers. The nano-molding process including the steps of: a) forming a first substrate having nano-scale features formed thereon, b) casting at least one polymer against the substrate, c) curing the at least one polymer forming a mold, d) removing the mold from the first substrate, e) providing a second substrate having a molding material applied thereon, f) pressing the mold against the second substrate allowing the molding material to conform to a shape of the mold, g) curing the molding material, and h) removing the mold from the second substrate having the cured molding material revealing a replica of the first substrate.

Abstract: Methods of forming a gas dielectric and a related structure are disclosed. In one embodiment, the method includes providing a wiring level including at least one conductive portion within a sacrificial dielectric; forming a nanofiber layer over the wiring level; vaporizing the sacrificial dielectric by heating; evacuating the vaporized sacrificial layer; and sealing pores in the nanofiber layer.

Abstract: A method of fabricating a continuous layer of a defect sensitive material on a silicon substrate includes preparing a silicon substrate; forming a nanostructure array directly on the silicon substrate; depositing a selective growth enhancing layer on the substrate; smoothing the selective growth enhancing layer; and growing a continuous layer of the defect sensitive material on the nanostructure array.

Abstract: A pixel electrode is provided, comprising a nanostructure-film deposited over an active matrix substrate, such that the pixel electrode makes electrical contact with an underlying layer. Similarly, auxiliary data pads and auxiliary gate pads are provided, which also comprise nanostructure-films deposited over an active matrix substrate, such that they make electrical contact with underlying layers.

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract: The present invention comprises a method for fabricating hafnia film comprising the steps of providing a substrate having a surface that allows formation of a self-assembled monolayer thereon via covalent bonding; providing an aqueous solution that provides homogeneous hafnium ionic complexes and hafnium nanoclusters wherein the aqueous solution is capable of undergoing homogeneous precipitation under controlled conditions for a desired period of time at a controlled temperature and controlled solution acidity for desired nanocluster nucleation and growth kinetics, desired nanocluster size, desired growth rate of film thickness and desired film surface characteristics.

Abstract: A solid state device is formed through thin film deposition techniques which results in a self-supporting thin film layer that can have a precisely defined channel bored therethrough. The device is useful in the chacterization of polymer molecules by measuring changes in various electrical characteristics as molecules pass through the channel. To form the device, a thin film layer having various patterns of electrically conductive leads are formed on a silicon substrate. Using standard lithography techniques, a relatively large or micro-scale aperture is bored through the silicon substrate which in turn exposes a portion of the thin film layer. This process does not affect the thin film. Subsequently, a high precision material removal process is used (such as a focused ion beam) to bore a precise nano-scale aperture through the thin film layer that coincides with the removed section of the silicon substrate.

Abstract: The present invention first obtains a nano-metal line by an e-beam lithography and an electroless plating, and imprints the line into a material with low-K to obtain a damascene metal line with low cost and high throughput, as a future solution for a metallization process for a general low-K metal damascene structure through CMP.

Abstract: A semiconductor nanowire is grown laterally. A method of growing the nanowire forms a vertical surface on a substrate, and activates the vertical surface with a nanoparticle catalyst. A method of laterally bridging the nanowire grows the nanowire from the activated vertical surface to connect to an opposite vertical surface on the substrate. A method of connecting electrodes of a semiconductor device grows the nanowire from an activated device electrode to an opposing device electrode. A method of bridging semiconductor nanowires grows nanowires between an electrode pair in opposing lateral directions. A method of self-assembling the nanowire bridges the nanowire between an activated electrode pair. A method of controlling nanowire growth forms a surface irregularity in the vertical surface. An electronic device includes a laterally grown nano-scale interconnection.

Abstract: The invention provides a nanolithographic protosubstrate adapted for nanolithographic formation of nanostructures on the protosubstrate comprising: a substrate having a top surface exposed for nanolithographic formation of nanostructures, wherein the top surface comprises: electrically insulating surface regions; and at least one discreet electrode topology surrounded by the electrically insulating surface regions, wherein the electrode topology is adapted with electrical interconnections for electrically coupling the electrode topology to an external device.

Abstract: A unique, micro-miniature reaction chamber template structure is disclosed for the fabrication of nanoscale molecular systems and devices. The structure is composed of multiple layers of silicon (either doped or intrinsic), Pyrex and various metals. The silicon may or may not be totally or partially covered with silicon dioxide. The Pyrex is chosen to be suitable for field-assisted bonding to silicon and the various metal layers are selected for their adherence to silicon or Pyrex, as well as their conductivity and their chemical reactivity. The basis structure may contain a number of tubes or fluidic pipes of varying cross sections. The structure consists of a layer of silicon bonded to a layer of Pyrex, which is in turn bonded to another layer of silicon and therefore, there is a composite structure which consists of a laminate of silicon glass and silicon.

Abstract: The present invention provides a method for the synthesis of nanowires in a silicon nanoporous template by electrodeposition and a novel technique for the integration of nanowires to transduction surfaces. In accordance with the present invention, a method for the fabrication of nanowire interconnects is provided. The method includes the steps of fabricating substantially vertical nanowires in a selectively passivated nanoporous silicon template, backetching the silicon template to expose the nanowires, eutectically bonding the exposed nanowires to a receiving silicon wafer, and etching the silicon template to produce substantially freestanding nanowire interconnects in contact with the receiving silicon wafer.