Abstract: A method for making silicon nanorods is provided. In accordance with the method, Au nanocrystals are reacted with a silane in a liquid medium to form nanorods, wherein each of said nanorods has an average diameter within the range of about 1.2 nm to about 10 nm and has a length within the range of about 1 nm to about 100 nm.

Abstract: A resistive device includes at least one strain gauge (12, 14) comprising silicon nanowires, a power supply (16) that has at least one current source (22, 24) able to generate a current (Ibias) for biasing the strain gauge; and acquisition means (18) able to deliver a measurement signal which can be used to determine the variation in the electrical resistance of the gauge. The power supply includes a chopper (26) allowing the biasing current generated by each current source to flow through each gauge only during a fraction of an operating cycle of the device.

Abstract: A light-emitting device includes a first conductive semiconductor layer formed on a substrate, a mask layer formed on the first conductive semiconductor layer and having a plurality of holes, a plurality of vertical light-emitting structures vertically grown on the first conductive semiconductor layer through the plurality of holes, a current diffusion layer surrounding the plurality of vertical light-emitting structures on the first conductive semiconductor layer, and a dielectric reflector filling a space between the plurality of vertical light-emitting structures on the current diffusion layer.

Abstract: Provided is a nanostructure including ordered stacked sheets and processes for its preparation and use.

Abstract: A semiconductor device includes a plurality of first conductivity type semiconductor nanowire cores located over a support, and an insulating mask layer located over the support. The nanowire cores include semiconductor nanowires epitaxially extending from portions of a semiconductor surface of the support exposed through openings in the insulating mask layer. The device also includes a plurality of second conductivity type semiconductor shells extending over and around the respective nanowire cores, a first electrode layer that contacts the second conductivity type semiconductor shells and extends into spaces between the semiconductor shells, and an insulating layer located between the insulating mask layer and the first electrode in the spaces between the semiconductor shells.

Abstract: A nanocomposite fluid includes a fluid medium; and a nanoparticle composition comprising nanoparticles which are electrically insulating and thermally conductive. A method of making the nanocomposite fluid includes forming boron nitride nanoparticles; dispersing the boron nitride nanoparticles in a solvent; combining the boron nitride nanoparticles and a fluid medium; and removing the solvent.

Abstract: A method for the synthesis of nano-products, such as atomic titanium oxide wires. The method allows wires of anatase titanium oxide wires to be formed in a range of tunable diameters and aspect ratios in the nanometer and subnanometer size scales. The method also allows the titanium wires to be capped by oleic acid to enhance dispersing and solubility. The method allows the titanium wires to be surface doped with nitrogen species to enhance stability and functionality such as enhanced absorption in the visible wavelength region, which is useful for photodegradation of organic wastes in water by sunlight.

Abstract: A network of nanowires may be used for a sensor. The nanowires are metallic, each nanowire has a thickness of at most 20 nm, and each nanowire has a width of at most 20 nm. The sensor may include nanowires comprising Pd, and the sensor may sense a change in hydrogen concentration from 0 to 100%. A device may include the hydrogen sensor, such as a vehicle, a fuel cell, a hydrogen storage tank, a facility for manufacturing steel, or a facility for refining petroleum products.

Abstract: A method of manufacturing a device based on LEDs includes the growth of semiconducting nanowires on a first electrode produced on an insulating face, and encapsulation thereof in planarizing material; the formation, on the planarizing material, of a second electrode with contact take-up areas. LEDs are formed by releasing a band of the first electrode around each take-up area, including forming a mask defining the bands on the second electrode, chemically etching the planarizing material, stopped so as to preserve planarizing material, chemically etching the portion of nanowires thus released, and then chemically etching the remaining planarizing material. A trench is formed along each of the bands as far as the insulating face and the LEDs are placed in series by connecting the take-up areas and bands of the first electrode.

Abstract: An electronic structure modulation transistor having two gates separated from a channel by corresponding dielectric layers, wherein the channel is formed of a material having an electronic structure that is modified by an electric field across the channel.

Abstract: A method of fabricating metallic Cu nanowires with lengths up to about 25 ?m and diameters in a range 20-100 nm, or greater if desired. Vertically oriented or laterally oriented copper oxide structures (CuO and/or Cu2O) are grown on a Cu substrate. The copper oxide structures are reduced with 99+ percent H or H2, and in this reduction process the lengths decrease (to no more than about 25 ?m), the density of surviving nanostructures on a substrate decreases, and the diameters of the surviving nanostructures have a range, of about 20-100 nm. The resulting nanowires are substantially pure Cu and can be oriented laterally (for local or global interconnects) or can be oriented vertically (for standard vertical interconnects).

Abstract: A method of forming an electrode of a lithium ion secondary battery includes combining a binder and active particles to form a mixture, coating a surface with the mixture to form a coated article, translating the article along a first plane, cutting a first plurality of carbon fibers, each having a first average length, to form a second plurality of carbon fibers, each having a longitudinal axis and a second average length that is shorter than the first average length, inserting the second plurality of fibers into the mixture layer so that the longitudinal axis of each of at least a portion of the second plurality of fibers is not parallel to the first plane to form a preform, wherein the second plurality of fibers forms a truss structure disposed in three dimensions within the mixture layer, and heating the preform to form the electrode. An electrode is also disclosed.

Abstract: A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.

Abstract: A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects.

Abstract: According to one embodiment, metal nanoparticle dispersion includes organic solvent, and metal-containing particles dispersed in the organic solvent. The metal-containing particles include first metal nanoparticles and second metal nanoparticles. Each of the first metal nanoparticles has a high-molecular compound on at least part of a surface thereof. Each of the second metal nanoparticles has a low-molecular compound on at least part of a surface thereof. A total amount of the low-molecular compound on all of the second nanoparticles includes an amount of a primary amine as the low-molecular compound.

Abstract: Another aspect of the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure including the same material as the substrate having a non-nanostructured surface of a dimension suitable for forming an electrical contact, located on the same side of the substrate as the array of silicon nanowires; wherein the contacting structure is doped with a greater impurity concentration than the nanowire array, thereby forming a selective emitter.

Abstract: An embodiment relates to a nanowire-containing LED device with optical feedback comprising a substrate, a nanowire protruding from a first side the substrate, an active region to produce light, a optical sensor and a electronic circuit, wherein the optical sensor is configured to detect at least a first portion of the light produced in the active region, and the electronic circuit is configured to control an electrical parameter that controls a light output of the active region. Yet, another embodiment relates to an image display having the nanowire-containing LED device with optical feedback.

Abstract: The disclosure related to a method for making a nanowire structure. First, a free-standing carbon nanotube structure is suspended. Second, a metal layer is coated on a surface of the carbon nanotube structure. The metal layer is oxidized to grow metal oxide nanowires.

Abstract: An incandescent light source display includes a container and a number of incandescent light sources. The incandescent light sources are located in the container. Each of the incandescent light sources includes a first electrode, a second electrode and an incandescent element. The second electrode is spaced from the first electrode. The incandescent element is electrically connected to the first electrode and the second electrode. The incandescent element includes a carbon nanotube structure.

Abstract: An embodiment of a microcapsule includes a shell surrounding a space, a liquid within the shell, and a light absorbing material within the liquid. An embodiment of a method of making microcapsules includes forming a mixture of a light absorbing material and an organic solution. An emulsion of the mixture and an aqueous solution is then formed. A polymerization agent is added to the emulsion, which causes microcapsules to be formed. Each microcapsule includes a shell surrounding a space, a liquid within the shell, and light absorbing material within the liquid. An embodiment of a method of using microcapsules includes providing phototriggerable microcapsules within a bulk material. Each of the phototriggerable microcapsules includes a shell surrounding a space, a chemically reactive material within the shell, and a light absorbing material within the shell.

Abstract: The device according to the invention comprises a nanostructured LED with a first group of nanowires protruding from a first area of a substrate and a contacting means in a second area of the substrate. Each nanowire of the first group of nanowires comprises a p-i-n-junction and a top portion of each nanowire or at least one selection of nanowires is covered with a light reflecting contact layer. The contacting means of the second area is in electrical contact with the bottom of the nanowires, the light-reflecting contact layer being in electrical contact with the contacting means of the second area via the p-i-n-junction. Thus when a voltage is applied between the contacting means of the second area and the light-reflecting contact layer, light is generated within the nanowire. On top of the light-reflecting contact layer, a first group of contact pads for flip-chip bonding can be provided, distributed and separated to equalize the voltage across the layer to reduce the average serial resistance.

Abstract: Nanowire preparation methods, compositions, and articles are disclosed. Such methods which reduce metal ions to metal nanowires in the presence complexes comprising metal-metal bonds, are capable of producing long, narrow, nanowires useful for electronics and optical applications.

Abstract: A nonvolatile memory electronic device including nanowire channel and nanoparticle-floating gate nodes, in which the nonvolatile memory electronic device, which comprises a semiconductor nanowire used as a charge transport channel and nanoparticles used as a charge trapping layer, is configured by allowing the nanoparticles to be adsorbed on a tunneling layer deposited on a surface of the semiconductor nanowire, whereby charge carriers moving through the nanowire are tunneled to the nanoparticles by a voltage applied to a gate, and then, the charge carriers are tunneled from the nanoparticles to the nanowire by the change of the voltage that has been applied to the gate, whereby the nonvolatile memory electronic device can be operated at a low voltage and increase the operation speed thereof.

Abstract: The present invention provides a hybrid powder of halloysite nanotubes and light-scattering nanoparticles, a method for preparing the same, and a UV-screening cosmetic composition containing the same as an active ingredient. The hybrid powder of halloysite nanotubes and light-scattering nanoparticles according to the present invention, in which the light-scattering nanoparticles are loaded into the halloysite nanotubes, can prevent the light-scattering nanoparticles from penetrating the skin, which minimizes side effects, and has excellent UV-screening effect. Thus, the hybrid powder of halloysite nanotubes and light-scattering nanoparticles according to the present invention can be effectively used as a UV-screening cosmetic composition.

Abstract: Disclosed is a method of screen printing an electrically conductive feature on a substrate, the electrically conductive feature including metallic anisotropic nanostructures, and a coating solution therefore.

Abstract: An optically transparent and electrically conductive film composed of metal nanowires or carbon nanotubes combined with pristine graphene with a metal nanowire-to-graphene or carbon nanotube-to-graphene weight ratio from 1/99 to 99/1, wherein the pristine graphene is single-crystalline and contains no oxygen and no hydrogen, and the film exhibits an optical transparence no less than 80% and sheet resistance no higher than 300 ohm/square. This film can be used as a transparent conductive electrode in an electro-optic device, such as a photovoltaic or solar cell, light-emitting diode, photo-detector, touch screen, electro-wetting display, liquid crystal display, plasma display, LED display, a TV screen, a computer screen, or a mobile phone screen.

Abstract: The invention provides a nanowire light emitting device and a manufacturing method thereof. In the light emitting device, first and second conductivity type clad layers are formed and an active layer is interposed therebetween. At least one of the first and second conductivity type clad layers and the active layer is a semiconductor nanowire layer obtained by preparing a layer of a mixture composed of a semiconductor nanowire and an organic binder and removing the organic binder therefrom.

Abstract: The present disclosure provides a catalyst-free growth mode of defect-free Gallium Arsenide (GaAs)-based nanoneedles on silicon (Si) substrates with a complementary metal-oxide-semiconductor (CMOS)-compatible growth temperature of around 400° C. Each nanoneedle has a sharp 2 to 5 nanometer (nm) tip, a 600 nm wide base and a 4 micrometer (?m) length. Thus, the disclosed nanoneedles are substantially hexagonal needle-like crystal structures that assume a 6° to 9° tapered shape. The 600 nm wide base allows the typical micro-fabrication processes, such as optical lithography, to be applied. Therefore, nanoneedles are an ideal platform for the integration of optoelectronic devices on Si substrates. A nanoneedle avalanche photodiode (APD) grown on silicon is presented in this disclosure as a device application example. The APD attains a high current gain of 265 with only 8V bias.

Abstract: Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.

Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semiconductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: Photonic nanostructures, light absorbing apparatuses, and devices are provided. The photonic nanostructures include a plurality of photonic nanobars configured to collectively absorb light over an excitation wavelength range. At least two of the photonic nanobars of the plurality have lengths that are different from one another. Each photonic nanobar of the plurality has a substantially small width and a substantially small height relative to the different lengths. A method for forming such may comprise forming a plurality of first photonic nanobars comprising a width and a height that are smaller than a length of the plurality of first photonic nanobars, and forming a plurality of second photonic nanobars comprising a width and a height that are smaller than a length of the second photonic nanobar, wherein the lengths of the plurality of first photonic nanobars and the lengths of the plurality of second photonic nanobars are different from one another.

Abstract: A method for culturing neural cells using a culture medium is provided. Each neural cell includes a neural cell body and at least one neurite branched from the neural cell body. The culture medium includes a substrate and a carbon nanotube structure located on the substrate. A surface of the carbon nanotube structure is polarized to form a polar surface. The neural cells are cultured on the polar surface to grow neurites along the carbon nanotube wires. The carbon nanotube structure includes a number of carbon nanotube wires spaced apart from each other. A distance between adjacent carbon nanotube wires is greater than or equal to a diameter of the neural cell body.

Abstract: A lithium-ion battery having an anode including an array of nanowires electrochemically coated with a polymer electrolyte, and surrounded by a cathode matrix, forming thereby interpenetrating electrodes, wherein the diffusion length of the Li+ ions is significantly decreased, leading to faster charging/discharging, greater reversibility, and longer battery lifetime, is described. The battery design is applicable to a variety of battery materials. Methods for directly electrodepositing Cu2Sb from aqueous solutions at room temperature using citric acid as a complexing agent to form an array of nanowires for the anode, are also described. Conformal coating of poly-[Zn(4-vinyl-4?methyl-2,2?-bipyridine)3](PF6)2 by electroreductive polymerization onto films and high-aspect ratio nanowire arrays for a solid-state electrolyte is also described, as is reductive electropolymerization of a variety of vinyl monomers, such as those containing the acrylate functional group.

Abstract: Various embodiments of the present invention are directed to negative refractive index-based holograms that can be electronically controlled and dynamically reconfigured to generate one or more color three-dimensional holographic images. In one aspect, a hologram comprises a phase-control layer having a plurality of phase modulation elements. The phase-modulation elements are configured with a negative effective refractive index and selectively transmit wavelengths associated with one of three primary color wavelength. The hologram also includes an intensity-control layer including a plurality of intensity-control elements. One or more color three-dimensional images can be produced by electronically addressing the phase-modulation elements and intensity-control elements in order to phase shift and control the intensity of light transmitted through the hologram. A method for generating a color holographic image using the hologram is also provided, as is a system for generating a color holographic image.

Abstract: An article is disclosed comprising a network-like pattern of conductive traces formed of at least partially-joined nanoparticles that define randomly-shaped cells that are generally transparent to light and contain a transparent filler material. In a preferred embodiment, the filler material is conductive such as a metal oxide or a conductive polymer. In another preferred embodiment, the filler material is an adhesive that is can be used to transfer the network from one substrate to another. A preferred method of forming the article is also disclosed wherein an emulsion containing the nanoparticles in the solvent phase and the filler material in the water phase is coated onto a substrate. The emulsion is dried and the nanoparticles self-assemble to form the traces and the filler material is deposited in the cells. An electroluminescent device is also disclosed wherein the article of the invention forms a transparent electrode in the device.

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

Abstract: Controlling dimensions of nanowires includes lithographically forming a trench in a layer of a polymer resin with a width less than one micrometer where the polymer resin has a thickness less than one micrometer and is deposited over an electrically conductive substrate, depositing a nanowire material within the trench to form a nanowire, and obtaining the nanowire from the trench with a removal mechanism.

Abstract: A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced.

Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.

Abstract: The disclosure relates generally to toner additives, and in particular, toner additives that provide desired higher and stable toner charge. The toner additives comprise silica nanotubes in combination with or in place of the commonly used silica or titania particulate additives.

Abstract: A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.

Abstract: A temperature stable (color and efficiency) III-nitride based amber (585 nm) light-emitting diode is based on a novel hybrid nanowire-planar structure. The arrays of GaN nanowires enable radial InGaN/GaN quantum well LED structures with high indium content and high material quality. The high efficiency and temperature stable direct yellow and red phosphor-free emitters enable high efficiency white LEDs based on the RGYB color-mixing approach.

Abstract: A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment.

Abstract: Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state.

Abstract: A method of forming a nanowire structure is disclosed. The method comprises applying on a surface of carrier liquid a layer of a liquid composition which comprises a surfactant and a plurality of nanostructures each having a core and a shell, and heating at least one of the carrier liquid and the liquid composition to a temperature selected such that the nanostructures are segregated from the surfactant and assemble into a nanowire structure on the surface.

Abstract: An electrochemical method for producing Si nanopowder, Si nanowires and/or Si nanotubes directly from compound SiX or a mixture containing a silicon compound SiX, the method comprises: providing an electrolysis cell having a cathode, an anode and an electrolyte, using the compound SiX or the mixture containing compound SiX as a cathode and immersing the cathode in an electrolyte comprising a metal compound molten salt, applying a potential between the cathode and the anode in the electrolysis cell, and forming one or more of Si nanopowder, Si nanowires and Si nanotubes on the cathode electrode. The method has advantages of: 1) shorter production processing, 2) inexpensive equipment, 3) convenient operation, 4) reduction of contaminate, 5) easily available feed materials, and 6) easy to achieve continuous production. This is a new field of using electrochemical method for producing one-dimensional Si nano material, and a new method of producing Si nanopowder, Si nanowires and Si nanotubes.

Abstract: A solar cell may include an electrically conducting substrate, a plurality of nanowhiskers extending from the substrate and a transparent electrode extending over free ends of the nanowhiskers and making electrical contact with them. Each nanowhisker may have a column with a diameter of nanometer dimension. The column may include a first p-doped semiconductor lengthwise segment and a second n-doped semiconductor lengthwise segment. The first and second semiconductor segments may have an interface between them, which forms a p-n junction. The nanowhiskers may be encapsulated in a transparent material.