Nanowire Or Quantum Wire (axially Elongated Structure Having Two Dimensions Of 100 Nm Or Less) Patents (Class 977/762)
Cross-Reference Art Collections
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Patent number: 8772755Abstract: A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.Type: GrantFiled: July 17, 2012Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
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Patent number: 8764878Abstract: Claimed methods do not rely on highly reactive reagents, highly corrosive solutions, high temperatures, or long reaction times. Nanowires produced from such methods are free of large attached nanoparticles that have accompanied previously disclosed copper nanowires. Such nanowires are useful for electronics applications.Type: GrantFiled: February 12, 2013Date of Patent: July 1, 2014Inventor: David R. Whitcomb
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Patent number: 8765255Abstract: A garment containing a breathable laminate that is optionally bonded to an outer layer fabric and an optional inner layer fabric. The breathable laminate is constructed from a microporous membrane situated in a face to face relationship with a nanoweb and optionally bonded thereto.Type: GrantFiled: February 29, 2008Date of Patent: July 1, 2014Assignee: E I du Pont de Nemours and CompanyInventors: Jill A. Conley, Robert Anthony Marin
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Patent number: 8766272Abstract: “An imaging device formed as an active pixel array combining a CMOS fabrication process and a nanowire fabrication process. The pixels in the array may include a single or multiple photogates surrounding the nanowire. The photogates control the potential profile in the nanowire, allowing accumulation of photo-generated charges in the nanowire and transfer of the charges for signal readout. Each pixel may include a readout circuit which may include a reset transistor, charge transfer switch transistor, source follower amplifier, and pixel select transistor. A nanowire is generally structured as a vertical rod on the bulk semiconductor substrate to receive light energy impinging onto the tip of the nanowire. The nanowire may be configured to function as either a photodetector or a waveguide configured to guild the light to the substrate. Light of different wavelengths can be detected using the imaging device.Type: GrantFiled: July 6, 2012Date of Patent: July 1, 2014Assignee: Zena Technologies, Inc.Inventors: Young-June Yu, Munib Wober
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Publication number: 20140174155Abstract: The present invention provides a hybrid nanomaterial electrode, comprising a pair of spaced-apart electrodes, at least three pairs of metallic nanowires disposed between the electrodes and respectively connected with the electrodes, and at least a detecting material connecting with the metallic nanowires. The detecting material is formed as a semiconductor nanostructure or a conductor nanostructure. The hybrid nanomaterial electrode of the present invention can be used in a gas detector for detecting volatile organic compounds, and has the advantage of providing high sensitivity, low detection limit, and the ability to operate at room temperature.Type: ApplicationFiled: May 1, 2013Publication date: June 26, 2014Applicant: NATIONAL TSING HUA UNIVERSITYInventors: CHIEN-CHONG HONG, ZI-XIANG LIN, KUO-CHU HWANG
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Publication number: 20140175374Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.Type: ApplicationFiled: March 2, 2014Publication date: June 26, 2014Applicant: Intemational Business Machines CorporationInventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
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Publication number: 20140175375Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer.Type: ApplicationFiled: March 2, 2014Publication date: June 26, 2014Applicant: Intemational Business Machines CorporationInventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
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Patent number: 8759810Abstract: A phase change memory device that utilizes a nanowire structure. Usage of the nanowire structure permits the phase change memory device to release its stress upon amorphization via the minimization of reset resistance and threshold resistance.Type: GrantFiled: September 24, 2010Date of Patent: June 24, 2014Assignee: The Trustees Of The University Of PennsylvaniaInventors: Ritesh Agarwal, Mukut Mitra, Yeonwoong Jung
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Publication number: 20140173786Abstract: Nanowire apparatus and methods of using the same are disclosed. The apparatus include nanowires that are attached to and extend from varying substrates and can be used in the manipulation of cells and/or sensing of cellular and subcellular characteristics. The methods include using the apparatus to sense forces exerted by a single cell or using the apparatus to manipulate one or more cells.Type: ApplicationFiled: February 21, 2014Publication date: June 19, 2014Applicant: Kansas State University Research FoundationInventors: Bret Flanders, Govind Paneru
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Patent number: 8754359Abstract: An embodiment relates to a device comprising a substrate having a front side and a back-side that is exposed to incoming radiation, a nanowire disposed on the substrate and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire.Type: GrantFiled: June 12, 2012Date of Patent: June 17, 2014Assignee: Zena Technologies, Inc.Inventors: Young-June Yu, Munib Wober
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Patent number: 8748799Abstract: An image sensor comprising a substrate and one or more of pixels thereon. The pixels have subpixels therein comprising nanowires sensitive to light of different color. The nanowires are functional to covert light of the colors they are sensitive to into electrical signals.Type: GrantFiled: December 14, 2010Date of Patent: June 10, 2014Assignee: Zena Technologies, Inc.Inventor: Munib Wober
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Publication number: 20140154785Abstract: A method of fabricating polymer single nanowires, comprising the steps of: spin coating a polymethylmethacrylate resist onto a silicon wafer patterned with at least one gold electrode pair; creating a nanochannel using e-beam lithography between each pair of the at least one gold electrode pairs; placing the silicon wafer into an aniline monomer polymerization solution; reacting the polymerization solution to give a coated wafer and a polyaniline film; and cleaning the coated wafer of polymethylmethacrylate resist and polyaniline film to give at least one gold electrode pair with a connecting polymer single nanowire.Type: ApplicationFiled: May 23, 2013Publication date: June 5, 2014Inventors: Minhee Yun, David Schwartzman, Jiyong Huang
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Publication number: 20140151757Abstract: Single crystalline semiconductor fins are formed on a single crystalline buried insulator layer. After formation of a gate electrode straddling the single crystalline semiconductor fins, selective epitaxy can be performed with a semiconductor material that grows on the single crystalline buried insulator layer to form a contiguous semiconductor material portion. The thickness of the deposited semiconductor material in the contiguous semiconductor material portion can be selected such that sidewalls of the deposited semiconductor material portions do not merge, but are conductively connected to one another via horizontal portions of the deposited semiconductor material that grow directly on a horizontal surface of the single crystalline buried insulator layer. Simultaneous reduction in the contact resistance and parasitic capacitance for a fin field effect transistor can be provided through the contiguous semiconductor material portion and cylindrical contact via structures.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anirban Basu, Josephine B. Chang, Michael A. Guillorn, Amlan Majumdar
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Publication number: 20140154621Abstract: The disclosure relates generally to toner additives, and in particular, toner additives that provide desired higher toner charge and low relative humidity (RH) sensitivity. The toner additives comprise titania nanotubes or titania nanosheets in combination with or in place of the commonly used anatase or rutile crystalline titania.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicants: NATIONAL RESEARCH COUNCIL OF CANADA, XEROX CORPORATIONInventors: RICHARD P. VEREGIN, Qingbin Li, Andriy Kovalenko, Sergey Gusarov
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Publication number: 20140154454Abstract: The heat resistant seal member according to one aspect of the present disclosure contains, for 100 parts by weight of a ternary fluoroelastomer, 5 to 15 parts by weight of first carbon nanofibers, 10 to 15 parts by weight of second carbon nanofibers, and 0 to 20 parts by weight of carbon black. The total amount of the first carbon nanofibers and the second carbon nanofibers are 15 to 30 parts by weight, and the total amount of the first carbon nanofibers, the second nanofibers, and the carbon black is 20 to 45 parts by weight. The heat resistant seal member can achieve a compression set of not more than 40% after 70 hours and 25% compressibility in a hydrogen sulfide gas atmosphere at 200° C.Type: ApplicationFiled: December 2, 2013Publication date: June 5, 2014Applicants: Shinshu University, Schlumberger Technology CorporationInventors: Hiroyuki Ueki, Toru Noguchi, Masaei Ito
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Publication number: 20140154564Abstract: Provided are an anode active material including carbon-based particles, silicon nanowires grown on the carbon-based particles, and a carbon coating layer on surfaces of the carbon-based particles and the silicon nanowires, and a method of preparing the anode active material. Since the anode active material of the present invention is used in a lithium secondary battery, physical bonding force between the carbon-based particles and the silicon nanowires may not only be increased but conductivity may also be improved. Thus, lifetime characteristics of the battery may be improved.Type: ApplicationFiled: January 30, 2014Publication date: June 5, 2014Applicant: LG Chem, Ltd.Inventors: Jung Woo Yoo, Won Jong Kwon, Eui Yong Hwang, Kil Sun Lee, Je Young Kim, Yong Ju Lee
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Patent number: 8735797Abstract: An embodiment relates to a device comprising a substrate having a front side and a back-side that is exposed to incoming radiation, a nanowire disposed on the substrate and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire.Type: GrantFiled: December 8, 2009Date of Patent: May 27, 2014Assignee: Zena Technologies, Inc.Inventors: Young-June Yu, Munib Wober
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Patent number: 8736011Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.Type: GrantFiled: December 1, 2011Date of Patent: May 27, 2014Assignee: Alphabet Energy, Inc.Inventors: Mingqiang Yi, Gabriel A. Matus, Matthew L. Scullin, Chii Guang Lee, Sylvain Muckenhirn
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Publication number: 20140138610Abstract: A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Michael C. Gaidis, Alexander J. Gaidis
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Publication number: 20140141555Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: GLO ABInventor: Truls Lowgren
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Publication number: 20140126280Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.Type: ApplicationFiled: November 6, 2012Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Michael C. Gaidis, William Gallagher, Luc Thomas
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Publication number: 20140126281Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.Type: ApplicationFiled: November 30, 2012Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Michael C. Gaidis, William Gallagher, Luc Thomas
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Patent number: 8716695Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.Type: GrantFiled: June 21, 2013Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Guy Cohen, Michael A. Guillorn, Conal E. Murray
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Patent number: 8716072Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.Type: GrantFiled: July 25, 2011Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Josephine B. Chang, Leland Chang, Jeffrey W. Sleight
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Patent number: 8715536Abstract: An electrically conductive material includes a plurality of nanowires and a plurality of nanoconnectors. The ratio by weight of the plurality of nanowires to the plurality of nanoconnectors is in a range of from 1:9 to 9:1. Nanoconnectors can be heated by thermal energy or light energy so that the nanoconnectors can be closely interconnected to each other and to nanowires, resulting in significant increase of the electrical conductivity of the electrically conductive material.Type: GrantFiled: May 27, 2010Date of Patent: May 6, 2014Assignee: Industrial Technology Research InstituteInventors: Yu Ming Wang, Yion Ni Liu, Yeu Kuen Wei, Chen Chih Yeh, Ming Jyh Chang
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Publication number: 20140117308Abstract: The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.Type: ApplicationFiled: October 28, 2013Publication date: May 1, 2014Inventors: Berangere Hyot, Benoit Amstatt, Marie-Francoise Armand
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Publication number: 20140119111Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; a first electrode and a second electrode provided to different locations of the magnetic nanowire; a third electrode including a magnetic layer, the third electrode being provided to a location of the magnetic nanowire between the first electrode and the second electrode; an intermediate layer provided between the magnetic nanowire and the third electrode, the intermediate layer being in contact with the magnetic nanowire and the third electrode; a fourth electrode of a nonmagnetic material provided onto the magnetic nanowire and being on the opposite side of the magnetic wire from the third electrode; and an insulating layer provided between the magnetic nanowire and the fourth electrode, the insulating layer being in contact with the magnetic nanowire and the fourth electrode.Type: ApplicationFiled: October 2, 2013Publication date: May 1, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Shiho Nakamura, Tsuyoshi Kondo, Hirofumi Morise, Takuya Shimada
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Patent number: 8710488Abstract: A first exemplary device has a substrate, a nanowire and a doped epitaxial layer surrounding the nanowire. The nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength. The first exemplary device may further have an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. A second exemplary device has a substrate, a nanowire and one or more photogates surrounding the nanowire. The nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength. The second exemplary device may have an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. The one or more photogates comprise an epitaxial layer.Type: GrantFiled: August 26, 2013Date of Patent: April 29, 2014Assignee: Zena Technologies, Inc.Inventors: Young-June Yu, Munib Wober
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Publication number: 20140110763Abstract: A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode and configured to vibrate in the presence of the magnetic field. The nanowire includes a protruding portion extending in a direction of the gate electrode.Type: ApplicationFiled: October 18, 2013Publication date: April 24, 2014Applicants: Korea University Industrial & Academic Collaboration Foundation, SAMSUNG ELECTRONICS CO., LTD.Inventors: In Sang Song, Ho Soo Park, Duck Hwan Kim, Sang Uk Son, Jae Shik Shin, Jae-Sung Rieh, Byeong Kwon Ju, Dong Hoon Hwang
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Patent number: 8703988Abstract: Nanostructures are formed from alkylated derivatives of aromatic acids of the formula: wherein at least one of R1 to R6 represents a carboxylic acid group, a primary amide group, an ester group, an amidine group, or a salt thereof, at least one other of R1 to R6 is X—Rc, and the remaining of R1 to R6 independently represent H or substituted or unsubstituted organic groups; X represents a linking group; and Rc represents a substituted or unsubstituted alkyl group.Type: GrantFiled: June 22, 2010Date of Patent: April 22, 2014Assignees: Xerox Corporation, National Research Council of CanadaInventors: Darren Andrew Makeiff, Rina Carlini
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Patent number: 8703271Abstract: A thermal interface material (1) comprises a bulk polymer (2) within which is embedded sub-micron (c. 200 to 220 nm) composite material wires (3) having Ag and carbon nanotubes (“CNTs”) 4. The CNTs are embedded in the axial direction and have diameters in the range of 9.5 to 10 nm and have a length of about 0.7 ?m. In general the pore diameter can be in the range of 40 to 1200 nm. The material (1) has particularly good thermal conductivity because the wires (3) give excellent directionality to the nanotubes (4)—providing very low resistance heat transfer paths. The TIM is best suited for use between semiconductor devices (e.g. power semiconductor chip) and any type of thermal management systems for efficient removal of heat from the device.Type: GrantFiled: April 23, 2008Date of Patent: April 22, 2014Assignee: University College Cork—National University of IrelandInventors: Kafil M. Razeeb, Saibal Roy, James Francis Rohan, Lorraine Christine Nagle
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Publication number: 20140106134Abstract: The present invention relates to methods of fabricating transparent conductive films based on nanomaterials, in particular, silver nanowires. The present invention incorporates a single step of annealing and patterning the conductive films by using a high energy flash lamp without post treatment to improve the conductivity and create substantially invisible patterns on the films for use in touch panel or display manufacturing industry.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Applicant: Nano and Advanced Materials Institute LimitedInventors: Li FU, Caiming SUN, Man-Ho SO, Kai LI, Chau-Shek LI, Tak-Hei LAM
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Publication number: 20140104941Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; first insulating layers provided on a first surface of the magnetic nanowire, each of the first insulating layers having a first and second end faces, a thickness of the first insulating layer over the first end face being thicker than a thickness of the first insulating layer over the second end face; first electrodes on surfaces of the first insulating layers opposite to the first surface; second insulating layers on the second surface of the magnetic nanowire, each of the second insulating layers having a third and fourth end faces, a thickness of the second insulating layer over the third surface being thicker than a thickness of the second insulating layer over the fourth end face; and second electrodes on surfaces of the second insulating layers.Type: ApplicationFiled: September 9, 2013Publication date: April 17, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuyoshi KONDO, Hirofumi MORISE, Shiho NAKAMURA, Takuya SHIMADA, Yoshiaki FUKUZUMI, Hideaki AOCHI
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Patent number: 8696947Abstract: Methods of recovering compositions comprising nanowires and the product compositions are disclosed and claimed. The product compositions produced by these methods are able to provide equivalent performance to virgin raw materials in transparent conductive film manufacturing processes.Type: GrantFiled: November 30, 2011Date of Patent: April 15, 2014Assignee: Carestream Health, Inc.Inventors: Richard R. Ollmann, Chaofeng Zou, Gary E. Labelle, Doreen C. Lynch
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Patent number: 8697587Abstract: A nonwoven web of fibers that have a number average diameter of less than 1 micron. The web can have a Poisson Ratio of less than about 0.8, a solidity of at least about 20%, a basis weight of at least about 1 gsm, and a thickness of at least 1 micrometer.Type: GrantFiled: July 1, 2009Date of Patent: April 15, 2014Assignee: E I du Pont de Nemours and CompanyInventors: Pankaj Arora, Guanghui Chen, Simon Frisk, David Keith Graham, Jr., Robert Anthony Marin, Hageun Suh
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Patent number: 8698122Abstract: A silicon nanowire including metal nanoclusters formed on a surface thereof at a high density. The metal nanocluster improves electrical and optical characteristics of the silicon nanowire, and thus can be usefully used in various electrical devices such as a lithium battery, a solar cell, a bio sensor, a memory device, or the like.Type: GrantFiled: October 3, 2012Date of Patent: April 15, 2014Assignees: Samsung Electronics Co., Ltd., Dongguk University Industry-Academic Cooperation FoundationInventors: Gyeong-su Park, In-yong Song, Sung Heo, Dong-wook Kwak, Hoon Young Cho, Han-su Kim, Jae-man Choi, Moon-seok Kwon
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Patent number: 8699206Abstract: Methods and apparatus for storing information or energy. An array of nano vacuum tubes is evacuated to a pressure below 10?6 Torr, where each nano vacuum tube has an anodic electrode, a cathodic electrode spaced apart from the anodic electrode, and an intervening evacuated region. An excess of electrons is stored on the cathodic electrode.Type: GrantFiled: October 20, 2010Date of Patent: April 15, 2014Assignee: The Board of Trustees of the University of IllinoisInventors: Alfred W. Hubler, Onyeama Osuagwu
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Publication number: 20140097502Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.Type: ApplicationFiled: October 8, 2013Publication date: April 10, 2014Applicants: Seoul National University R & DB Foundation, SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Chul SUN, Byung-Gook PARK
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Publication number: 20140090842Abstract: A variety of methods and compositions are disclosed, including, in one embodiment, a method of cementing comprising: providing an aqueous dispersion comprising deagglomerated inorganic nanotubes and water; preparing a cement composition using the aqueous dispersion; introducing the cement composition into a subterranean formation; and allowing the cement composition to set. Another method comprises a method of cementing comprising: providing an ultrasonicated aqueous dispersion comprising deagglomerated nanoparticles, a dispersing agent, and water; preparing a cement composition using the aqueous dispersion; introducing the cement composition into is subterranean formation; and allowing the cement composition to set.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: HALLIBURTON ENERGY SERVICES, INC.Inventors: Rahul Chandrakat Patil, Ramesh Muthusamy, B. Raghava Reddy, Abhimanyu Pramod Deshpande, Sohini Bose
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Patent number: 8685877Abstract: A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1017 atoms/cm3 to be obtained.Type: GrantFiled: December 19, 2007Date of Patent: April 1, 2014Assignee: IMECInventors: Francesca Iacopi, Philippe M. Vereecken
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Patent number: 8685323Abstract: Methods and apparatuses for encapsulating inorganic micro- or nanostructures within polymeric microgels are described. In various embodiments, viruses are encapsulated with microgels during microgel formation. The viruses can provide a template for in situ synthesis of the inorganic structures within the microgel. The inorganic structures can be distributed substantially homogeneously throughout the microgel, or can be distributed non-uniformly within the microgel. The inventive microgel compositions can be used for a variety of applications including electronic devices, biotechnological devices, fuel cells, display devices and optical devices.Type: GrantFiled: September 19, 2008Date of Patent: April 1, 2014Assignees: Massachusetts Institute of Technology, President and Fellows of Harvard CollegeInventors: Yoon Sung Nam, Angela Belcher, Andrew Magyar, Daeyeon Lee, Jin-Woong Kim, David Weitz
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Patent number: 8685844Abstract: A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions. The amorphous alumina portions are removed and the remaining dense alumina portions which have an ordered lattice arrangement are employed as an etch mask. After removing the amorphous alumina portions, each dense alumina portion has a width which is also less than 10 nm.Type: GrantFiled: August 15, 2012Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Christos D. Dimitrakopoulos, Aaron D. Franklin, Joshua T. Smith
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Patent number: 8685348Abstract: The invention concerns a nanowire structural element which is suited for implementation in, for example, a microreactor system or microcatalyzer system. For the production of the nanowire structural element, a template based process is used wherein the electrochemical deposition of the nanowires in nanopores is ideally carried out at least until caps are formed and said caps ideally are at least partially merged together. After reinforcing the two cover layers the structured hollow chamber between the two cover layers is cleared by dissolving the template foil and removing the dissolved template material, wherein the two cover layers remain intact. In this manner, a stable sandwich-like nanostructure is constructed with a two-dimensional hollow chamber-like structure in the plane parallel to the cover layers contained on both sides by the cover layers and permeated in a column-like manner with nanowires.Type: GrantFiled: March 12, 2009Date of Patent: April 1, 2014Assignee: GSI Helmholtzzentrum fur Schwerionenforschung GmbHInventors: Thomas Cornelius, Wolfgang Ensinger, Reinhard Neumann, Markus Rauber
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Patent number: 8679949Abstract: A silicon nanowire includes metal nanoclusters formed on a surface thereof at a high density. The metal nanoclusters improve electrical and optical characteristics of the silicon nanowire, and thus can be usefully used in various electrical devices such as a lithium battery, a solar cell, a bio sensor, a memory device, or the like.Type: GrantFiled: March 31, 2011Date of Patent: March 25, 2014Assignees: Samsung Electronics Co., Ltd., Dongguk University Industry-Academic Cooperation FoundationInventors: Gyeong-su Park, In-yong Song, Sung Heo, Dong-wook Kwak, Hoon Young Cho, Han-su Kim, Jae-man Choi, Moon-seok Kwon
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Patent number: 8680514Abstract: An electric energy generator may include a semiconductor layer and a plurality of nanowires having piezoelectric characteristics. The electric energy generator may convert optical energy into electric energy if external light is applied and may generate piezoelectric energy if external pressure (e.g., sound or vibration) is applied.Type: GrantFiled: October 27, 2010Date of Patent: March 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Young-jun Park, Seung-nam Cha
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Patent number: 8680574Abstract: A hybrid nanostructure array having a substrate and two types of nanostructures, including a set of first nanostructures extending from the substrate and a set of second nanostructures interspersed among the first nanostructures. The first and second nanostructures comprise structures having nanoscale proportions in two dimensions and being elongate in the third dimension. For example, the nanostructures can be nanotubes, nanowires, nanorods, nanocolumns, and/or nanofibers. Also disclosed is a hybrid nanoparticle array using two different types of nanoparticles that have all three dimensions in the nanoscale. The two types of nanostructures or nanoparticles can vary in composition, shape, or size.Type: GrantFiled: July 22, 2009Date of Patent: March 25, 2014Assignee: The Regents of The University of MichiganInventor: Anastasios John Hart
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Publication number: 20140079912Abstract: The present disclosure relates to solution processed nanomaterials, and methods for their manufacture, with activity in the infrared (IR) region for a variety of commercial and defense applications, including conformal large-area IR coatings, devices and pigments that necessitate an absorption band edge in the MWIR or LWIR.Type: ApplicationFiled: September 17, 2012Publication date: March 20, 2014Inventors: Larken E. Euliss, Brett Nosho, Nicole L. Abueg, G. Michael Granger, Peter D. Brewer, Maryam Behroozi
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Publication number: 20140080293Abstract: A solar cell includes a plurality of nanowires arranged such that diameters of the nanowires sequentially increase in a first direction along a path of incident light. In a method of forming nanowires, a catalyst layer is formed on a substrate, a plurality of nanoparticles are formed by thermally processing the catalyst layer, and nanowires are grown from the plurality of nanoparticles. The catalyst layer has a thickness that increases in a first direction, and the plurality of nanoparticles have diameters that increase in the first direction.Type: ApplicationFiled: November 22, 2013Publication date: March 20, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-jun PARK, Chan-wook BAIK
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Patent number: 8673750Abstract: A method can include depositing a thin metal film on a substrate of a sample, establishing a metal island on the substrate by patterning the thin metal film, and annealing the sample to de-wet the metal island and form a metal droplet from the metal island. The method can also include growing a nanowire on the substrate using the metal droplet as a catalyst, depositing a thin film of a semiconductor material on the sample, annealing the sample to allow for lateral crystallization to form a crystal grain, and patterning the crystal grain to establish a crystal island. An electronic device can be fabricated using the crystal island.Type: GrantFiled: December 19, 2011Date of Patent: March 18, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Robert A. Street, Sourobh Raychaudhuri
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Publication number: 20140070251Abstract: The invention provides a reflective phase retarder and a semiconductor light-emitting device including such reflective phase retarder. The reflective phase retarder of the invention converts an incident light beam with a first type polarization into the light with a second type polarization, and reflects the converted light beam with the second type polarization out.Type: ApplicationFiled: May 3, 2013Publication date: March 13, 2014Applicant: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGYInventor: Yi-Jun Jen