Abstract: The present invention relates to an apparatus for providing a data available indication while inhibiting the reading of operand data beyond the last word of an operand data string. The data available indication operates to enable additional cycles to be generated for completing the execution of the instruction. The apparatus includes a memory element, which has a plurality of locations, each of the plurality of locations corresponding to a respective location of a memory device where the operand data string is stored. The memory element stores information which indicates when the corresponding location is the last word of the operand data string. A read address register which contains the read address value of the memory device includes an input strobe terminal which receives an enable signal based on the information stored in the memory element, thereby enabling or inhibiting the updating of the read address value in the read address register.

Abstract: An arbitration circuit comprises a plurality of enabling elements which determines when predetermined conditions exist to transmit a request signal. A first gate combines transmitted request signals to generate a combined request signal. A plurality of first latches, each first latch having a sequential priority order and operatively connected to a corresponding enabling element, and further connected to the output of the first gate, generates an enable and a disable signal. A plurality of second gates is included, each second gate is operatively connected to the first gate to receive the combined request signal, and each second gate operatively connected to the corresponding first latch to receive the enable signal.

Abstract: The present invention relates to a data transmission system, for transmitting information from a first end-user device to a second end-user device, which comprises a plurality of channel elements, each channel element having an input and an output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format. Each channel element also has a plurality of parallel input terminals and a plurality of parallel output terminals adapted to receive and transmit, respectively, parallel digital data. The parallel output terminals of each of the channel elements is operatively connected to the parallel input terminals of a next adjacent channel element thereby connecting the channel elements in a ring configuration.

Abstract: The present invention relates to the operational control of a digital computer system which includes the digital logic circuitry for temporarily storing results internal to an execution unit. An input unit of the execution, which inputs operand words to the execution logic of the execution unit, includes a first stack for holding operand words received from an external memory unit and a second stack for holding the result words of the execution logic. The input unit also includes a switch element for selecting words stored in the first and second stack which are to be utilized as input operand words to the execution logic in response to at least one control signal.

Abstract: A write amplifier for a computer memory unit features a first and a second output terminal. The amplifier may be controlled, in the write mode, to provide output signals, on the two output terminals, of one relative polarity or the other in accordance with an applied data signal. The amplifier may be further controlled, in the read mode, to provide substantially identical signals, called a read reference voltage level, on both output terminals.

Abstract: The present invention relates to a method within a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The method includes loading the temporary storage memory with the first and second operand data strings in a pre-established order such that the subsequent fetching of the operand data words from the temporary storage memory is performed in a sequential order. The loading and fetching steps operate to achieve a desired word order such that the operation between operand data strings can be started while the operand data is being fetched.

Abstract: A plant management system is provided. The system includes one or more digital process control and data acquisition subsystems and a plant control network. Each control subsystem includes a data highway, and process control, and process interface units. The plant control network is a token-passing distributed plant control network in which a plurality of physical modules communicate with one another over a plant control bus. While there are limited number of different types with each type having different functions, all physical modules have common units, one of which is a module central processor unit. Both the number of modules and the number of types of modules of a plant control network have both a maximum and a minimum. Reliability of the plant management system is improved by a provision for redundancy at the physical module level. One type of physical module provides data communication and translation facilities between the plant control network bus and the data highway of a control subsystem.

Abstract: A method of optimizing the operation of a process so that desired products are produced at minimum cost. The process has a plurality of process components, with each component having a run status and an idle status. The process has available more than one input and produces more than one output. The process is controlled by a computer which is provided with a mathematical model of the process, which model includes a model of each of its components. The model for each process component includes a logic variable, which logic variable can have only two values, 0 and 1, and which represent the run or idle status of each process component. The computer, when predetermined conditions arise, solves a mixed integer equation to determine the optimum state of the process at a given time to produce the desired outputs, at desired rates and at minimum cost; and, in doing so, determines the value of the logic variable for each component.

Abstract: An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addressable validity bit arrays, each of which arrays can store a validity bit in each of the addressable locations of each array. A pointer enables only one of the validity bit arrays to receive address signals corresponding to the lower virtual page number (LVPN) of a VPN. The validity bit read out of the memory location corresponding to the LVPN of the enabled array is used in determining if the PPN read out of the corresponding memory location of the associative memory is valid. The bits of the disabled array, immediately after it is disabled, are all reset, or cleared.

Abstract: A driver circuit for applying a first signal having a desired wave form, frequency and peak to peak voltage to a coaxial transmission line which also has applied to it a second signal having a substantially higher frequency. An operational amplifier has the first signal applied to its noninverting input terminal. The output of the operational amplifier is applied across the primary winding of a driver coupling transformer through an inductor which provides high impedance to the second signal. The voltages induced in the secondary winding of the driver transformer are applied to the transmission line. The primary winding of a feedback transformer is connected in parallel with the secondary winding of the driver transformer. The voltage induced in the secondary winding in the feedback transformer are applied by a feedback circuit including an R.C. filter to the inverting input terminal of the operational amplifier. The signal applied to the inverting input terminal includes both an A.C. component and a D.C.

Abstract: The present invention relates to an execution unit of a computing system which executes data manipulation type instructions and arithmetic type instructions on data words having a plurality of decimal character-type data formats. The pipelined execution unit of the present invention includes a first stage element which temporarily stores input data, the input data including operation commands defining said decimal type instructions, and input operand data. A second stage element executes a first predetermined group of the decimal type instructions. A third stage element, operatively coupled to said second stage element, executes a second predetermined group of the decimal type instructions, the second predetermined group including arithmetic type instructions.

Abstract: The present invention relates to an operational control of a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The present invention includes an adder for adding the current read address value to a constant thereby generating a new read address value used to read the operand data on the next cycle. A preselected constant is provided to the adder each cycle, which causes the resultant new read address value to forward or reverse read the operand data.

Abstract: In a data processing system including a central processing unit capable of operation with a plurality of operating systems, a VMSM unit is described for producing a composite decor descriptor from a plurality of possible decor descriptor formats. The VMSM unit includes an input buffer unit and an output buffer unit, a control unit to analyze an incoming DATA and provide appropriate control signals, a reconfiguration unit for reformatting the plurality of descriptor formats into a composite format, a descriptor fetch unit for retrieving a descriptor when the signals applied to the VMSM unit contain a descriptor address, and a descriptor master copy unit which contains a copy of the descriptors stored in the addressing apparatus.

Abstract: A memory refresh control scheme is provided wherein the refresh timing and address signals are independent of memory configuration or the configuration of an interface unit. Since the system relates to a distributed memory arrangement, the refresh control signal and the refresh address signals are simultaneously sent to the corresponding address portions of each of the concerned memory sections and to the interface units. The logic involved in generating the refresh signal includes a first counter, driven by the system clock, which periodically generates the refresh request control signal. A second counter generates a digital address for the portion of the memory units to be refreshed. The second counter is incremented by each successive output control signal from the first counter.

Abstract: Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit of the central processor unit. As instructions are prefetched, the transfer and indirect prediction (TIP) table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s).

Abstract: A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute instructions issued to them in order of issuance by the pipeline and in parallel. As instructions are issued to the execution units, the operation code identifying each instruction is also issued in program order to an instruction execution queue of the collector. The results of the execution of each instruction by an execution unit are stored in a result stack associated with each execution unit. Collector control causes the results of the execution of instructions to program visible registers to be stored in a master safe store register in program order which is determined by the order of instructions stored in the instruction execution stack on a first-in, first-out basis.

Abstract: A peripheral power control sequencer incorporates a microcomputer to control the sequencing of the powering of a plurality of peripheral control units. The terminals of the input/output ports of the microcomputer are time-shared to accommodate the several input and output signals needed to accomplish the sequential powering of the peripheral controller.

Abstract: A pipelined multiplexer is provided for selecting one-of-m input signals, comprising N stages of select elements, each stage of the select elements including 2.sup.n /2 select gates, where n is the stage number. Each select gate has two input terminals and one output terminal for selecting one of two input signals from the input terminals. The selection of an input signal is in response to a corresponding select control signal and the outputting of the respective selected signal is in response to a clocking signal.

Abstract: Apparatus for controlling the colors displayed by a raster graphic system. Information stored at each addressable location of a RAM includes a set of behavior bits and a set of control bits. These bits are read out of memory during each memory read cycle. The control bits are stored in a shift register and the behavior bits are applied to an escape code detector and may be stored in a foreground or a background behavior register if enabled by the detector. One control bit is shifted out of the shift register each pixel clock pulse. This control bit determines the register from which the behavior bits are selected to form a color index. The index includes behavior bits from the selected register and the control bit for the pixel being scanned. This index is applied to a color look-up memory which produces color control signals which are applied to D/A converters, the outputs of which control the color and intensity of each pixel of the raster.

Abstract: A method of synchronizing a digital timer with the frequency of a source of A.C. power to provide long term temporal stability. The timer produces internal, fine resolution, synchronization and real time timing signals from a source of clock signals. The periods of all the timer produced timing signals are integral multiples of the period of its internal timing signal.A.C. reference timing signals which are a function of the frequency of the source of A.C. power are applied to the timer. The quotient of the period of the synchronization timing signals by that of the A.C. reference timing signals is an integer "n". Once n is determined, the number of fine resolution timing signals in each synchronization period for every n.sup.th A.C. timing signal is compared with a reference value. The timing of the fine resolution timing signals is adjusted to maintain the number of fine resolution timing signals in each synchronization period at which the n.sup.th A.C.