Abstract: The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. When the output data word format is different from the input data word format, selected characters in response to a predetermined control signal are temporarily stored so that they may be inputted to the shifters on the next shift cycle in order to achieve the desired shifted character order. An alignment switch then aligns or packs the shifted data from the output of the shifters to the predetermined data format in response to a select control signal.

Abstract: A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock signals to selected serial arrays, a maintenance data processor for providing predetermined signal groups, and addressing apparatus responsive to the predetermined signal groups for loading and unloading register arrays in response to the predetermined signals. The disclosed apparatus permits a predetermined signal group to be entered into the serial register array, a predetermined number of clock cycles (i.e. series of operations performed on the data), and the resulting signals shifted from the serial register array and signals applies to data processing unit for display or analysis.

Abstract: A digital phase locked loop is provided by the present invention which includes a digital controlled oscillator (DCO), whereby the frequency of the output signal of the DCO is a function of the value associated with a digital input word. The frequency of the output signal of the DCO is phase compared to a reference signal by a phase comparator. Depending upon which signal is leading or lagging, the phase comparator outputs an increment signal or a decrement signal. These increment and decrement signals are operatively coupled to an up/down counter which provides the digital input word to the DCO, the value of the digital input word being modified by the increment or decrement signal to cause the frequency of the output signal to track the frequency of the input signal to the phase comparator, i.e., the frequency of the reference signal.

Abstract: The present invention relates to digital logic circuitry for detecting a predetermined character of a data string for operand data stored in a temporary storage memory or while the data is being loaded into the temporary storage memory, wherein the data string length and the starting location of temporary storage memory in which the data string is to be stored is variable. A first comparator element compares a write address pointer to a start address pointer and an adder generates a sign pointer which indicates an address of temporary storage memory of the predetermined character. A second comparator element utilizes the pointers and the resultant outputs of the first comparator and the adder to indicate the end of the data string.

Abstract: A fail-safe digital telephone set of the present invention is operatively connected to a digital PBX which has at least one digital telephone set attached thereto and which further interfaces with telephone lines to a central office. The fail-safe digital phone includes logic for providing digital communication of voice information with the PBX, logic for providing analog communication of voice information with the telephone lines, and a switching element which activates the digital logic and connects the digital logic to the PBX.In the event of failure of the PBX, the switching element activates the analog logic and connects the analog logic to the telephone lines.

Abstract: An improved multiword data register array which features RAM technology to provide a greater memory capacity in a smaller space than a conventional register arrays. Whereas RAM technology does not ordinarily include the capability of simultaneously reading and writing, in accordance with the present invention, data may be written into the register on a first half cycle of a clock signal and read out of memory on the second half cycle of the same clock signal. If the writing and the reading of the data relate to the same address in the register array, the data may be read directly from the input circuit.

Abstract: A power supply for providing a selectable predetermined regulated output voltage. A switching regulator circuit provides the conversion of an input voltage to a DC output voltage and a control circuit, which senses the output voltage, controls the conversion of the switching regulator circuit. In the present invention, an amplifier, having selectable gain values, is interposed in the feedback loop, i.e., between the output terminal of the power supply and the control circuit. Thus a predetermined portion of the output voltage is fed back to the control circuit, thereby selectively determining the output voltage without necessitating changes to the switching regulator circuit or the control circuit.

Abstract: A specialized circuit set is included in a data processing system wherein the circuit set registers can be configured into a serial array. A clock signal distribution system delivers controlled clock signals to selected serial arrays. A maintenance data processor provides predetermined signal groups and addressing apparatus responsive to the predetermined signal groups loads and unloads register arrays in response to the predetermined signals. A predetermined signal group is entered into the serial register array, a predetermined number of clock cycles are applied, and the resulting signals shifted from the serial register array are applied to the maintenance data processor for display or analysis. By comparing the expected result for a given initial state with the actual result of an operation sequence, the accuracy of the operation of the data processing system, or any portion thereof, is thereby determined.

Abstract: In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comprising a step clock generator which generates a gated clock signal. A register element receives a step command signal, an indication from the computer system that the memory unit is to be operated in the step mode, and generates the step mode control signal in response to said step command signal. A shift register receives a strobe command signal from the computer system indicating a request for a memory cycle, and delays the strobe command signal, each stage of the shift register representing a successive step when the computer system is operated in the step mode.

Abstract: In an input/output multiplexer of a data processing unit, a plurality of components, capable of independent activity, provide for the simultaneous execution of a multiplicity of operations involving the exchange of signal groups between a central subsystem and peripheral subsystems. The input/output multiplexer includes apparatus for controlling the receipt from delivery to the central subsystem and peripheral subsystems of signal groups. Apparatus is provided to execute address development normally performed in the central subsystem. Apparatus is also provided to analyze control subsystem signal groups and generate pre-selected command signal groups for delivery to the central subsystem or to the peripheral subsystems. Apparatus in the input/output multiplexer also provides a status of each operation currently in execution.

Abstract: The method by which the right of access to the common communication medium of an initialized local-area network is transferred between modules having access to the medium by the module having such access transmitting a token to a designated existing and properly functioning module. Each such module is assigned a unique address, its MY ADDRESS, and has the data-processing capabilities to determine and store the address of the module to which it last successfully transferred a token, its LAST SUCCESS ADDRESS. Each module also determines the address of a module, if any, between its LAST SUCCESS ADDRESS and its MY ADDRESS, its TRY ADDRESS. The module which has accepted a token will try to pass a token to the module whose address is that of its TRY ADDRESS if its TRY ADDRESS differs from its LAST SUCCESS ADDRESS before attempting to pass a token to the module whose address is that of its LAST SUCCESS ADDRESS.

Abstract: An interface apparatus, which interfaces a communication device to a highway wherein the highway includes a clock line, a data line, and a busy line, comprises a counter element which counts a clock signal transmitted on the clock line to generate a clock value. The counter includes a second input terminal connected to the busy line to disable the counting when a busy signal is present on the busy line. A compare element compares the clock value to a device number value associated with the communication device, each communication device coupled to the highway having a unique device number value, and outputs an enable signal when the clock value and the device number value are equal. A driver element permits data to be transmitted onto the data line in response to the enable signal when the communication device has data to be transmitted.

Abstract: A sense amplifier for a computer memory includes a plural stage differential amplifier. The first stage of the differential amplifier includes an input emitter follower connected to the input of the first stage differential pair. A negative feedback loop is connected around the first stage. The negative feedback loop enhances the response characteristic of the amplifier. Circuit means are also provided which enables the selective steering of energizing current through or away from the second stage of the differential amplifier to provide for the selective blocking of the output of the sense amplifier.

Abstract: In a data processing system having a plurality of CPUs, each CPU is operatively connected to other portions of the data processing system through a system interface unit. The CPU includes a cache memory, an execution unit, and a control unit. Further, each CPU includes an apparatus for verifying the operability of the CPU independent from the operation of the data processing system, which comprises a switch element, interposed between a first port of the CPU and the system interface unit, for decoupling the CPU from said system interface unit in response to a decoupling control signal. A detecting element, detects whether the CPU and the system interface unit are operatively connected to generate a configuration signal indicating the status of the operative connection. A maintenance panel is connected to the switch element and to the detecting element via a second CPU port.

Abstract: The method by which a token-passing local-area network having from two to 2.sup.n modules is initialized, where n is an integer greater than zero. When connected into the network and energized, each module determines if the network is initialized and, if not, which module is to do so. Each module has a unique n bit network address. The module with the smallest network address energized before the network is initialized is identified and begins the process of initialization by transmitting tokens addressed sequentially to network addresses beginning with the next higher address than its own until a token so transmitted is accepted by an addressed module or until a token has been addressed to all network addresses other than that of the initiating module. If after tokens are transmitted to all possible network addresses other than that of the initiating module, the initiating module generates a fault signal to indicate its status.

Abstract: A cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the cache are equal in capacity. The two parts of the cache, designated I-Cache and O-Cache, are semi-independent in their operation and include arrangements for effecting synchronized searches, they can accommodate up to three separate operations substantially simultaneously. Each cache unit has a directory and a data array with the directory and data array being separately addressable. Each cache unit may be subjected to a primary and to one or more secondary concurrent uses with the secondary uses prioritized.

Abstract: The present invention relates to an apparatus for verifying a data path through a digital switch between a transmitting port and a receiving port. The apparatus comprises a transmitter which transmits a test data block in a first predetermined time slot which corresponds to the time slot associated with the transmitting port. A receiver receives the test data block in a second predetermined time slot, which corresponds to the time slot associated with the receiving port. Test logic examines the received test data block to determine that the test data block has been transmitted error-free through the digital switch thereby verifying the data path.

Abstract: A decoder for Manchester encoded data signals in which the encoded data signals are applied to a first circuit which produces a primary pulse at each voltage transition of the applied signals. The primary pulse enables a delay line oscillator which after a predetermined period of delay produces a decode clock signal of a given frequency. The inverted primary pulse, the decode clock signal, and a constant voltage data input signal are applied to a decoder shift register. The primary pulse and selected outputs of the decoder shift register are applied to a logic circuit which produces a receive clock signal having desired low-to-high voltage transitions occurring substantially in the center of each half-bit cell of a Manchester bit cell. The receive clock signal can be applied to a receive data shift register to which the encoded data signals are also applied so that the binary value of each half-bit cell of a Manchester bit cell can be stored in the data shift register.

Abstract: Method and apparatus for calculating the residue of a signed binary number of "n" bits with respect to a given check base m where m=2.sup.b -1. The bits of the binary number excluding the sign bit are partitioned into number segments, each of b bits starting with the least significant bit. If (n-1) is not an even multiple of b, higher order bit positions of the number segment containing the next most significant bit of the binary number are filled with logical zeros. A sign segment of b bits is formed. Both number and sign segments have boundaries. The bit position in the sign segment relative to a sign segment boundary which corresponds to the bit position of the sign bit "s" relative to the nearest boundary of a number segment is filled with a logical zero. All other bit positions of the sign segment are filled with the sign bit. The number and sign segments are applied to carry save adders to reduce the number segments and sign segment to a single sum segment and a single rotated carry segment.

Abstract: Method and apparatus for calculating the residue of a binary number of "n" bits with respect to a given check base m where m=2.sup.b -1. The binary number is partitioned into segments, each of b bits starting with the least significant bit. If n is not an even multiple of b, higher order bit positions of the segment containing the most significant bit of the number are filled with logical zeros. The segments are applied to levels of carry save adders to reduce the segments of the binary number to a single sum segment of b bits and a single rotated carry segment of b bits where a rotated carry segment is a carry segment produced by a carry save adder, the most significant bit of which is rotated so that it becomes the least significant bit of the rotated carry segment. Carry segments produced by carry save adders of one level are converted to rotated carry segments before being applied to a carry save adder of a lower level carry save adder.