Abstract: Diagonally disposed line-selection artifacts appear in the video signal from a CCD imager using a line-transfer register, owing to differential delay in a side-loaded CCD shift register used for transferring charge packets from the image sensing array to the charge sensing output stage. The extent of these line-selection artifacts is shortened in the direction of line scan by spatial multiplexing, so they occur entirely within line retrace intervals. The line-selection artifacts are then suppressed by normal line retrace blanking.

Abstract: A CCD imager of frame-storage type has a frame storage register operable as a recirculating serial memory. The output ends of the parallel charge transfer channels in the image register are separated from respective ones of the input ends of the parallel charge transfer channels in the frame storage register by respective ones of the successive charge transfer stages of a line register. After the frame storage register charge packet contents are converted to serial format and sensed during selected field scan intervals, corresponding charge packets are clocked serially into the line register, then parallelly entered into the frame storage register.

Abstract: In an FM receiver including a plurality of cascaded amplifier stages for successively amplifying an IF signal to form a pulse signal which is demodulated to derive an audio signal, an auxiliary amplifier section beside the cascade is provided to amplify a signal developed at an intermediate point in the cascade to form a signal from which a control signal for controlling the gain of an RF amplifier. The auxiliary amplifier section includes a first linear amplifier including degenerative signal feedback followed in cascade by a second linear amplifier including a gain control arrangement. The latter is responsive to a logarithmic gain control signal generated by a logarithmic amplifier in response to the output signal of a peak detector following the auxiliary amplifier. The control signal has a relatively wide control range, e.g., 10 to 500 microvolts of RF input signal, suitable for controlling the gain of an RF stage.

Abstract: In a television receiver, two tunable traps are incorporated between the RF input and the tuner to attenuate undesired signals symmetrically located in frequency below and above respective desired RF carriers. In one embodiment, the tunable traps are responsive to a tuning voltage for controlling the tuned circuits of the tuner so that the attenuation frequencies of the traps track the frequencies of the RF carriers associated with selected channels. In another embodiment the attenuation frequencies of the traps are moved with respect to the respective frequencies of desired RF carriers to optimize interference reduction.

Abstract: The input offset potential of a transistor amplifier exhibited by a grounded-emitter bipolar transistor or a grounded source enhancement-mode field effect transistor can be too large for certain applications. A preceding differential-input amplifier overcomes this problem.

Abstract: An integrated circuit for processing the IF signal of a radio receiver to produce an audio signal also includes a muting circuit for muting the audio signal, detector circuits for generating a stop signal which, e.g., may be used to stop the operation of a scanning tuner when the IF signal has a predetermined condition, an inhibiting circuit for inhibiting the generation of the stop signal and a signal strength for generating positive-going and negative-going signals representing the amplitudes of an RF input signal.

Abstract: In an integrated circuit structure including IF amplifier stages coupled in cascade by d-c blocking capacitors to restrict the noise bandwidth of an FM receiver in which it is employed and receiving power from a common power supply line, separate operating voltage generating circuits are provided for each amplifier stage to inhibit undesired oscillations. Each voltage generating circuit is decoupled from the power supply line by a respective lateral transistor configuration cooperative with a current mirror amplifier arrangement to supply a reference current to the voltage generating circuit.

Abstract: The circuitry comprises a source of input signal current, a common-base transistor amplifier or its equivalent supplying a first load means from its output connection, a first resistive means connected at its first end to the source of input signal current and at its second end to the input connection of the common-base transistor amplifier or its equivalent, a voltage follower with input connection from the first end of the first resistive means, a current mirror amplifier supplying a second load means from its output connection, and a second resistive means connected at its first end to the output connection of said voltage follower and connected at its second end to the input connection of the current mirror amplifier.

Abstract: A digital phase comparator for essentially eliminating the dead zone in the phase correction means of a phase locked loop. The digital phase comparator is arranged to provide respective up and down output pulses to operate respective charge pumps. The up and down output pulses at all times are greater than a predetermined time duration no matter how small the phase difference between comparator input signals. A delay means is provided in the phase comparator logic, which delay means substantially determines such predetermined time duration. The minimum pulse duration of the up and down signals is selected to be at least of a duration sufficient to operate its respective charge pump, thereby overcoming the finite turn on time of the respective charge pump, no matter how small the phase error.

Abstract: A logic level converter for translating an input signal that swings between first and second voltage levels to an output signal that swings between third and fourth voltage levels. The input signal and its complement are first translated to the desired output levels in a pair of conventional CMOS inverters to produce complementary logic signals. The faster edge of each translated logic signal is used by logic means to control the output signal. Specifically, the leading edge of one logic signal and the trailing edge of the other logic signal are used to control the output signal. The resulting logic level shift circuit provides both fast rise and fall times, and substantially equal propagation delays for both high-to-low and low-to-high signal transitions.

Abstract: An integrated circuit having circuitry for clamping input terminals that remain unconnected after assembly into a system. A transistor is connected to clamp the input terminal to reference potential and provide regenerative feedback to a NAND circuit forming a latch which maintains the transistor on when the input terminal would otherwise be left floating. Alternatively, when the terminal is connected to supply potential, the transistor is maintained "off", precluding loss of power.

Abstract: Within a single pack tape cartridge, a bearing szrface is integrated on the cartridge case to preclude segments of the tape pack from telescoping into clearance space and thereby a retaining ring is eliminated from the tape cartridge assembly.

Abstract: A complementary symmetry inverter comprising two field effect transistors and a current mirror amplifier. A constant bias current is supplied to the master path of the current mirror amplifier. The slave path of the current mirror amplifier and one of said field effect transistors are connected to form a switched current source in series with the other of said transistors. The switched current source limits the peak value of the switching current pulse in the inverter in fixed relation to the current in the master path of the current mirror amplifier when the inverter switches between logic states. The switched current source also limits the current between the inverter output and an external device.

Abstract: A defect compensation circuit of the type that substitutes a portion of delayed signal information for a real-time signal defect including circuitry for correcting chrominance phase reversal. The delayed signal is sampled at 1/2 the period of the chrominance before and after a 1H delay. The signal samples are summed and proportioned to provide a substitution signal having its chrominance signal in phase with the real time signal, and an average luminance signal exhibiting non-observable distortion.

Abstract: A temperature-independent reference voltage is developed as the difference between the offset potentials across first and second diode means, the second nested within the first to conduct the same forward bias current.

Abstract: A gain control circuit includes a first transistor with direct-coupled collector-to-base feedback converting current, applied to its collector, to logarithmically related voltage appearing between its emitter and base. This logarithmically related voltage is incremented or decremented by a voltage .DELTA.V.sub.1 proportional to T and applied to the emitter-base junction of a second transistor used as a logarithm of voltage to current converter, T being an absolute temperature close to that at which the first and second transistors are operated. .DELTA.V.sub.1 is developed as the potential drop across a resistive element R1, responsive to the output current of a current-to-logarithm-of-current converter circuit, making the conversion with a scaling factor proportional to T divided by the resistance R.sub.1 of resistive element R1. Accordingly, the gain setting of the gain control circuit is unaffected by change in T.

Abstract: A current driver circuit using a two-level current source for switching PIN diodes. The driver is responsive to a binary signal control voltage for providing a respective forward-bias current or reverse-bias voltage. The two-level current source, responsive to output voltage, is included in the driver circuit to supply one of two current levels when the driver is conditioned to forward-bias the diode. When the output voltage is below a predetermined threshold value, a first level of current is supplied; when the output voltage is above the predetermined value, a second level of current, generally larger than the first current, is provided. The disclosed technique reduces peak instantaneous power dissipation in the driver by avoiding the simultaneous condition of high voltage and high current.

Abstract: A defect compensation circuit which substitutes a portion of delayed signal information for a real-time signal defect. A capacitor passes the a-c component of the delayed signal and stores the d-c component of the real-time signal to preclude the occurrence of d-c shifts upon effecting the substitution of signal.

Abstract: An input signal to a buffer circuit is applied via the emitter-to-base junction of a transistor to a circuit which includes at least one additional semiconductor junction and a current source. The collector of the transistor connects to a second current source and to the buffer circuit output terminal. When the input signal exceeds a threshold value, determined by the number of semiconductor junctions in the circuit including the emitter-to-base junction, the transistor turns on and its collector current, which exceeds the capacity of the second current source, flows via the buffer circuit output terminal to the load circuit.

Abstract: The transistors of a differential amplifier are coupled at their common emitter electrode connection to a low voltage power supply terminal and at their collector electrodes through respective current sinks to a point of reference potential. The collector electrodes are maintained at a voltage level above the reference potential to permit input signal swings at the base electrodes of the transistors a comparable amount below the reference voltage level. Current sources are provided for satisfying that portion of the current demand of these sinks not furnished by the transistors. When the amplifier is connected to operate as a voltage follower, additional transistors may be provided to prevent an undesirable change in the polarity of the output signal, when the input signal swings substantially below the reference voltage level.