Abstract: In a television system including a source of an intermediate frequency (IF) signal, which signal includes an IF picture carrier amplitude modulated with video information, synchronous demodulator means responds to the IF signal, for providing an in-phase first output video signal that has both luminance and chrominance components, and for providing a quadrature-phase second output video signal that has a chrominance component but substantially no luminance component. Chroma circuitry is responsive to the quadrature-phase second output video signal for generating first and second color-difference signals.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: A method is disclosed for operating electronic apparatus for generating a weighted summation of digital input signals as manifested in electric signal form, each sample of which digital input signals has a plurality B in number of bits identified by respective ones of consecutive ordinal numbers first through B.sup.th assigned in order of decreasing significance. Successive samples of each of the digital input signals is supplied in a respective stream, such that the respective streams of samples are parallel in time with each other. Each B-bit sample of said digital input signals is recoded into a plurality D in number of binary-coded digits, as manifested in electric signal form and as identified by consecutive ordinal numbers frist through D.sup.th assigned in order of decreasing significance of the respective weighting assigned each of the D binary-coded digits, B and D begin respectively a relatively larger positive integer and a relatively smaller positive integer.

Abstract: In an oversampling interpolative analog-to-digital converter having a sigma-delta modulator followed in cascade by a decimation filter, the decimation filter supplies digital output signals for the oversampling analog-to-digital converter at an output rate that is a submultiple 1/R of an oversampling rate at which digital samples of an input signal for said decimation filter are supplied. The chopping rate of the chopper-stabilized amplifier is a multiple of the output sample rate of the decimation filter to place the fundamental and the harmonics of the chopping at the frequencies corresponding to the zeroes in the decimation filter response, better to keep remnants of the chopper stabilization from appearing in the output samples from the decimation filter.

Abstract: Plural-bit digital input signals to be subjected to weighted summation in a neural net layer are bit-sliced; and a number N of respective first through N.sup.th weighted summations of the bits of the digital input signals in each bit slice are performed, resulting in a respective set of first through N.sup.th partial weighted summation results. Weighted summations of the partial weighted summation results of similar ordinal number are then performed to generate first through N.sup.th final weighted summation results. Each weighted summation of a bit slice of the digital input signals is performed using a capacitive network that generates partial weighted summation results in the analog regime. In this capacitive network each weight is determined by the difference in the capacitances of a respective pair of capacitive elements.

Abstract: An oversampling converter of a type using a plural-order, plural-stage sigma-delta modulator, the output signal to the decimating filter of which modulator has the quantization noise contribution of a number of its plurality of stages suppressed therein, uses single-bit quantization in those stages to help avoid problems of nonlinearity. Each other sigma-delta converter stage, the quantization noise of which appears in substantial amount in the converter output signal to the decimating filter, uses quantization having multiple-bit resolution to help increase the resolution of the oversampling converter overall.

Abstract: Linear combining apparatus for digit-serial data performs addition, subtraction and comparison functions on a systolic basis. Signals are afforded the apparatus indicating the occurence of the most significant digits of the digit-serial signals being linearly combined.

Abstract: An oversampling converter of a type using a plural-order, plural-stage sigma-delta modulator, the output signal to the decimating filter of which modulator has the quantization noise contribution of a number of its plurality of stages suppressed therein, uses single-bit quantization in those stages, and the modulator uses single-bit quantization in those stages. Those stages each employ digital-to-analog converters with single-bit resolution in their feedback connections to avoid non-linearity problems. Another sigma-delta converter stage, the quantization noise of which appears in substantial amount in the converter output signal to the decimating filter, uses quantization having multiple-bit resolution to help increase the resolution of the oversampling converter overall.

Abstract: A laser device includes a substrate of semiconductor material having a major surface and a pair of opposed side surfaces. A plurality of laser elements are on the major surface of the substrate and are arranged in a plurality of spaced rows. Each laser element has an active region in which radiation is generated and which extends substantially parallel to the major surface of the substrate and between the side surfaces. Each row can contain either a single laser element or a plurality of laser elements which are optically coupled along the row. A waveguide extends from each end of each row of laser elements toward an adjacent side surface of the substrate. The waveguides are optically coupled to optically couple the laser elements in the rows in series so as to injection lock in phase the laser elements. Means are provided for emitting the radiation from one of the surfaces of the substrate.

Abstract: Respective processors for pairs of photodetecting elements are included in an imager used for sensing hologram fringe patterns in an optical interferometer. These processors remove the direct-current pedestal from in-phase and quadrature-phase field images, then perform partial correlations of the resulting field images on a pixel-by-pixel basis, and then sum the partial correlations to complete the image correlation process and to provide imager output signal or the basis therefor. This localized processing greatly reduces the number of samples that have to be brought out of the imager each frame when the imager is used in an optical interferometer to detect phase modulation in an optical signal, allowing for increased frame rates in accordance with a further aspect of the invention. Image correlation is done according to a novel algorithm that avoids actually having to multiply together correspondingly located pixels in each pair of successive fields forming a successive non-overlapping frame.

Abstract: Parallel accumulation of the density functions of image picture elements is done for a number of elements located at the same radial distance from the axis of rotation for the fan-beam scanner. This allows the computation of weighting factor to be done in common for these elements, as well as the computation of interpolation coefficients for ray sums not registering exactly with x-ray detectors.

Abstract: The capacitances of a pair of capacitors associated with a neural net is carried out in a complementary way, so the sum of the capacitances remains equal to a constant, C.sub.k. Each of a set of component capacitors with capacitances related in accordance with powers of two is selected to be a component of one or the other of the pair of capacitors, the selecting being done by field effect transistors (FETs) operated as transmission gates. The gate signals for the FETs are respective ones of the bits in a binary number stored in a word storage element of a semiconductor memory.

Abstract: The input signals to the weighted summation circuitry are weighted by respective weighting factors on a digit-sliced basis. Each of the weighting factors is expressed as a respective plurality of portions of different weighting significance, the portions being R in number. The portions of the weighting factors expressed as digits that have the same weighting significance constitute a rank of values. These ranks of values are normalized by dividing each of them by its respective weighting significance. R ranks of capacitors are connected in R respective networks that sum the input signals, as weighted respectively by each of the ranks of normalized values, to get normalized respective partial summation results. To generate a final weighted summation result, means are provided to sum the respective partial summation results provided from the R respective networks, after the respective partial summation results have been weighted by their corresponding weighting significances to remove normalization.

Abstract: One type of transversal filter using digit-serial signals in its operation comprises a to-digit-serial converter for converting a succession of input data words received at its input port each to a respective succession of m-bit-wide digits supplied from its output port in order of progressively greater significance, m being a positive plural integer; a clocked delay line having an input tap connected for responding to the m-bit-wide digits supplied from the output port of the to-digit-serial converter and having at least one further tap for supplying a respective tap signal; and means for performing a weighted summation of the input signal to the clocked delay line and each tap signal from the clocked delay line, to generate a filter response in digit-serial format.

Abstract: A recursive digital filter for digit-serial signals comprises a digit-serial adder having an augend input port to which successions of m-bit-wide digits of a digital-serial filter input signal are supplied in order of progressively greater significance, having at least a first addend input port, and having a sum output port; digit-serial multiplier apparatus having a multiplicand input port connected from the sum output port of said digit-serial adder and having a product output port for supplying a weighted response to signal received at its multiplicand input port; and means for applying the weighted response to the first addend input port of the digit-serial adder so as to be in word alignment with the digit-serial input signal to the augend input port of the digit-serial adder.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: Digital electronic apparatus for performing chain-serial matrix multiplications using a single pipeline multiplier supplies elements of the multiplicand and multiplier matrices to the digital memory from first and second memories. Each product matrix is temporarily stored in a third memory until such time as it is used to write the first memory for the next matrix multiplication in the series. This procedure avoids overwriting the first memory when its data are still required for application to the pipeline multiplier.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: Linear combining apparatus for digit-serial data performs addition, subtraction and comparison functions. The capability of performing addition or subtraction as the result of comparison permits non-restoring division to be done using a plurality of the linear combining apparatuses.

Abstract: An inertial transformation matrix generator generates a succession of Euler transformation matrices in inertial coordinates, and is useful for converting to inertial coordinates the responses of a sensor hard mounted on the hull of a craft (e.g., an aircraft). First, second and third rate-sensing gyros located proximately to said sensor are strapped down to the craft hull, and are oriented to sense the motion of the craft hull in three mutually orthogonal directions, for providing respective output signals indicative of components of craft hull motion in each of those three mutually orthogonal directions. The output signals of the gyros are digitized, and based on these digital signals successive incremental Euler transformation matrices are generated.