Abstract: The plural-phase clocking signal used in a subsampling time-domain digital filter is partially blanked to generate a sparse clocking signal for a clocked data latch that decimates the output signal from the digital filter, to supply it at a subsampling rate as compared to the sampling rate of input signal to the filter. The blanking signal is generated from a counter that counts occurrences of pulses in the plural-phase clocking signal, which counter comprises a ripple-carry adder and another clocked data latch arranged to accumulate successive unit values. This procedure guarantees correct timing of clocking signal for the output latch vis-a-vis the plural-phase clocking signal used in the preceding time-domain digital filter despite the time taken for carry ripplethrough in the counter adder. Digital hardware is conserved by blanking only one phase of the plural-phase clocking signals.

Abstract: A crossbar switch is constructed in monolithic integrated circuit form together with respective memory cells controlling each of the component crosspoint switches in the crossbar switch. The memory cells permit control signals for the crosspoint switches to be supplied serially to the monolithic integrated circuit and thus permit those control signals to be supplied in coded form as orthogonal cross addressing for the memory cells. This reduces the number of bits which must be provided in parallel to the integrated circuit for controlling the crosspoint switches. In preferred embodiments of the crossbar switch, provision is made for operation as a corner-turn array for rotating bit matrices and for faster operation as a barrel shifter.

Abstract: The discrete Fourier transform is continuously calculated at input signal sample rate using recursive filtering, rather than transversal filtering. This reduces the number of complex digital multiplications per computational cycle to N, the number of spectral components in the discrete Fourier transform, where rectangular truncation window or a new exponential window is used. Where a triangular truncation window is used the number of complex digital multiplications per computational cycle is reduced to 2N.

Abstract: A method for performing oversampled analog-to-digital conversion of an input signal to generate a conversion result signal essentially free of systematic errors in accordance with the invention includes the steps of: performing oversampled analog-to-digital conversion of the input signal to generate a preliminary conversion result signal accompanied by systematic error, performing oversampled analog-to-digital conversion of a zero-valued signal to generate a correction signal essentially consisting of a corresponding systematic error, and differentially combining the correction signal and the preliminary conversion result signal to generate the conversion result essentially free of systematic errors. In a structural embodiment of the invention the systematic error in an oversampled analog-to-digital converter is suppressed by subtracting from the conversion response the response of a similar oversampled analog-to-digital converter to the reference voltage as its analog input signal.

Abstract: A design methodology for digit serial architecture, especially for use in digital signal processing circuitry, includes a cell stack configuration incorporating a variable number of individual operation cells in conjunction with cap and control cells to provide power, control and timing signals. The arrangement employed permits the construction of cell libraries for silicon compilers from a small number of individual components and permits such compilers to generate chip fabrication masks for a plurality of fixed, but initially arbitrary digit size circuit designs.

Abstract: Instantaneous trip capability is provided to an electronic circuit breaker, which is of the type that generates trip signals by accumulating squares of power line current samples and thresholds the accumulation results. Samples of power line current are taken directly from the current transformer and analog-to-digital converter cascade generating them. The analog-to-digital converter is of an oversampling type, using a delta-sigma modulator. The samples are threshold detected against a prescribed threshold value without previous squaring, integration and detection. The threshold detector result is checked for two consecutive overcurrent indications before an instantaneous trip signal is generated.

Abstract: A switched-capacitance amplifier has a common terminal and an input signal terminal for receiving an input signal voltage therebetween, and it has an inverted output signal terminal for supplying, during each of a second series of separated time intervals interleaved without overlap with a first series of separated time intervals, an output voltage that is the negative of its input signal voltage. The switched-capacitance amplifier includes first and second capacitors. The switched-capacitance amplifier also includes a differential-input amplifier, having an output connection to the inverted output signal terminal, having a non-inverting input connection to the common terminal, having an inverting input connection, and having an input port between its non-inverting and inverting input connections.

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Abstract: A cell module which is particularly employable in bit-serial silicon compilation methods permits the fabrication and layout of bit-serial multipliers having variable word sizes. In particular, the cell module permits the fabrication of a bit-serial multiplier which is capable of a number of different functions including the production of high-order (major) and low-order (minor) output product bit streams which may be selected from so as to provide output results in a variety of different formats associated with binary fractional multiplication.

Abstract: Current mirror amplifiers are disclosed, each having first and second ports that can be interchanged as to which is input port and which is output port in response to an electric control signal. A chopper-stabilized differential amplifier that uses such a switchable current mirror amplifier as a balanced-to-single-ended signal converter for output signals is disclosed, which chopper-stabilized differential amplifier is particularly suited for the integrating amplifier in a delta-sigma analog-to-digital converter.

Abstract: A digital multiplier for multiplying together W-bit digit-serial multiplier and multiplicand signals includes a combinational array of multiplier cells arranged in N rows and W columns. A digit-serial-in/parallel-out register supplies respective bits of each successive multiplicand signal to the W columns of the array, the N rows of which receive respective bits of each successive digit of the multiplier signal. After each earlier digit of the multiplier is processed, the carry and sum bits are forwarded without column shift and with one column shift, respectively, from the final row to the first row of multiplier cells. This scrolls the operation of the W-column-by-N-row multiplier cell array, allowing it to be used M times for each word of the multiplier signal, one for each of the M digits in a W-bit word of the multiplier signal.

Abstract: A data shifter is constructed in monolithic integrated-circuit form essentially from three basic cells, namely: a first or A type of bit-slice cell with a multiplexer for selecting one of two inputs to a clocked output latch, a second or B type of bit-slice cell with a multiplexer for selecting one of two inputs to a cascaded pair of clocked latches, and a control cell for controlling the selection process in bit-slice cells arranged in a stack therewith. In addition where the order of the bits in each successive digit of the shifter output needs to be rotated, this can be accomplished using combinations of two further types of basic cells, namely: a braid-slice cell, and a braid-cap cell. These cells are rectangular and tile in a close-packed mosaic. The disclosure describes how to make a same set of basic cells that is adaptable for use both in left shifters and in right shifters.

Abstract: A barrel-shift data shifter structure is modified to segregate switches in a switching matrix included therein into those switches as participate in a simple shift as well as in a barrel shift and those switches used only in a barrel shift. The former set of switches is controlled by shift control signals alone, and the latter set of switches responds to shift control signals and to the presence or absence of a rotation enable signal. The number of switches required is substantially smaller than required in a barrel shifter followed in cascade by a simple data shifter. Preferably provision is made for sticky bit generation. The sticky bit is the LOGIC OR response to all bits shifted to less significance than output data.

Abstract: A differential delta-sigma modulator of switched-capacitance type is operated with a three-phase cycle, rather than the two-phase cycle of the prior art. In the first phase of operation the switched capacitors are charged in accordance with the previous single-bit output of the modulator. Structural modifications permit the switching capacitors to be connected in series to receive the modulator input voltage during the second phase of operation so that voltage need not be balanced with regard to any specified common-mode potential. In the third phase of operation the switched capacitors discharge from first plates thereof to the differential-input integrator while the second plates thereof are driven in accordance with the previous single-bit output of the modulator.

Abstract: Before subsampling them for transmission, telemetry data are bandwidth-limited by IIR filtering at the sending station of a telemetry system. The transmitted filtered telemetry data have attendant phase distortion that is compensated for by FIR filtering at the receiving station of the system, so as to obtain overall linear phase response through the system.

Abstract: Sine and cosine waves are simultaneously accumulated in accordance with the following equations in apparatus embodying the invention.M sin .theta.=[M sin (.theta.-.delta..theta.)] cos .delta..theta.+[M cos (.theta.-.delta..theta.)] sin .delta..theta.M cos .theta.=[M cos (.theta.-.delta..theta.)] cos .delta..theta.-]M sin (.theta.-.delta..theta.)] sin .delta..theta.Here .delta..theta. is an incremental angle between successive steps of accumulation.

Abstract: A detector for a first continuous-wave-modulation signal is supplied an unmodulated carrier signal in addition to the first continuous-wave-modulation signal. Means are provided for modulating the unmodulated carrier signal responsive to output signal from the detector to generate a second continuous-wave-modulation signal encoding a previous value of output signal, as delayed to provide a predicted input signal, in the same way the first continuous-wave-modulation signal encodes the input signal. The first and second continuous-wave-modulation signals are linearly combined so as to cancel the correlated portions of them and to develop a third continuous-wave-modulation signal with suppressed carrier, which is detected to recover an error signal. This error signal is combined with the predicted input signal obtained by delaying a previous value of said output signal, thereby to generate the current output signal of the detector.

Abstract: A double precision, low-latency two's complement bit-serial multiplier operates on the fact that after both inputs have been fully read into the multiplier, the calculation has proceeded to such a stage that it may be completed with a single counter. The multiplier comprises a plurality of bit slices and an endcell connected in series. The serial bit streams of the operands are sampled by latches in each of the bit slices, and the sampled bit values are accumulated using (5,3) counters to generate partial sum output signals. The partial sum output signal for the last bit slice is the least significant word of the double precision product. The endcell comprises another (5,3) counter which accumulates propagated sum and carry output signals of the bit slices and generates the most significant word of the double precision product.

Abstract: A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.

Abstract: Computer main memory is used for storing relatively densely sampled luminance detail information concerning a television display and for storing relatively sparsely sampled narrowband color-component information concerning the same television display. The relatively densely sampled luminance detail information is read out in substantially real-time from computer main memory during line trace intervals in the television display. The relatively sparsely sampled narrowband color-component information is read out of computer main memory in advanced and compressed time during selected line retrace intervals in the television display.