Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).

Abstract: An amplifier circuit contains a first and second current branch, each branch comprising an input transistor and a cascode transistor. Inputs of the amplifier are coupled to control electrodes of the input transistors in respective ones of the current branches. The control electrodes of the cascode transistors are coupled to each other. A high frequency coupling is provided between the control electrodes of the cascode transistors and a node of the common current source, to copy substantially common mode voltage changes of terminals of the main current channels of the input transistors to voltage changes at the control electrodes of the cascode transistors.

Abstract: An arrangement for determining the position of a motion sensor element influencing the formation of a magnetic field, impressed on the arrangement, periodically along its motion co-ordinate, includes a sensor arrangement which is sensitive along a measuring direction aligned at least substantially parallel to the motion co-ordinate of the motion sensor element to at least the polarity of the magnetic field impressed on the arrangement and is adapted to supply a measuring signal in dependence upon a field component of the magnetic field impressed on the arrangement. The motion sensor element, arranged in a strip-shaped zone of a main surface extending along the motion co-ordinate of the motion sensor element includes periodically recurrent areas alternatively influencing the measuring field which is being formed parallel to the main surface and is at least substantially parallel to the motion co-ordinate of the motion sensor element.

Abstract: What is described is a configuration for determining the position of a body along a movement direction, wherein the body is in the form of a magnetized encoder with two magnetic tracks extending, on one surface of the body, along the movement direction, at least essentially in parallel with one another, wherein, at specified intervals along the movement direction, a first of the magnetic tracks exhibits magnetized sections in which the magnetic north poles are aligned so as to be at least largely coincident in a magnetization direction that is essentially at right-angles to the surface of the body, and wherein, at intervals specified to coincide with the above-mentioned intervals along the movement coordinate, the second of the magnetic tracks exhibits magnetized sections in which the magnetic south poles are aligned so as to be at least largely coincident in the said magnetization direction, and wherein, in each case, a magnetized section of one of the magnetic tracks is located at least largely centrally in

Abstract: A method of correcting a real-time clock of an electronic apparatus, notably a mobile telephone, in which the real-time clock operates with a first clock generator which generates a real-time clock while the electronic apparatus operates with a second clock generator which generates a system clock, which method includes the following steps: determining the actual frequency of the real-time clock, determining the ratio Vclock/standard of the actual frequency of the real-time clock to the reference frequency of a standard clock, determining the deviation time of the real-time clock per second from the difference (1?Vclock/standard), determining, on the basis of the deviation time per second, a time difference dt within which the real-time clock is to be corrected by a correction time difference ?t, correcting the real time by ?t after expiration of dt.

Abstract: A radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter (108,110,112,114) for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter (516) for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter (516) is terminated, the other (I) is digitised by a non-complex ADC (520), then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter (516) are digitised and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs (120,1620) is possible, thereby avoiding duplication of circuitry and providing significant power savings.

Abstract: A RF amplifier device (22) including an amplifier element (24) compensated by a compensating circuit (26, 28) with respect to its output capacitance and frequency decoupled from its power supply (26), wherein the decoupling circuit is directly connected to the compensating circuit (26, 28) and a RF amplifier device including an amplifier element (56, 80) and a compensating circuit comprising an internal shunt inductor having a compensating inductance (58, 60, 62) and a compensating capacitance (64, 92) and arranged in parallel to a terminal of the amplifier element (56, 80) to compensate a terminal capacitance of the amplifier element (56, 80), and a decoupling and power supply lead (76, 98) which is connected to the compensating capacitance (64, 92) and/or a decoupling circuit (100) and/or a combination of the compensating capacitance and the decoupling circuit (130) and a module thereof and a method for decoupling the mentioned RF amplifier device.

Abstract: An output circuit for a semiconductor amplifier element having an output capacitance (20, 42) that is to be cancelled by a first LC circuit having a first inductance (22, 44) and a first capacitance (24, 46), said output circuit comprising an additional inductance circuit with an additional inductance (30, 52) and an additional capacitance (32, 54), said first inductance circuit and said additional inductance circuit compensating for the output capacitance (20, 42) of the semiconductor amplifier element, while the first inductance (22, 44) and the first capacitance (24, 46) cancel out the second harmonics within the output signal of the semiconductor amplifier element.

Abstract: The invention relates to a filter device equipped with at least one bulk acoustic wave resonator, which comprises a resonator unit and a reflection element (2) comprising several layers (6, 7, 8). The layers (6, 7, 8) each comprise a mixture of at least two materials. Within each layer (6, 7, 8), the composition of the mixture varies continuously and periodically relative to the layer thickness.

Abstract: A semiconductor package is proposed. The semiconductor package includes a discrete semiconductor chip on a die pad, a plurality of bond pads situated next to the chip and formed with a plurality of connecting mechanisms and an encapsulant for encapsulating the chip and the pads. In a preferred embodiment the die pad and/or the bond pads comprise means for vertically and laterally interlocking the pads to the encapsulant. The interlocking means of the bond pads and the die pad significantly enhance the bonding strength between the pads and the encapsulant for preventing delamination or cracking, so that quality and reliability of the quad flat non-leaded semiconductor package comprising a discrete can be assured.

Abstract: A voltage comparator with comparing means that are energized upon the occurrence of a clock-edge and that are de-energized when the comparison operation is completed. The comparing means are preceded by a voltage divider (D) for dividing the voltage to be compared and a switch (S8) in series with the voltage divider for preventing current flow through the voltage divider when the comparing means are de-energized.

Abstract: A radio receiver configurable to operate in either a low-IF or a zero-IF mode comprises a quadrature down-converter (108,110,112,114) for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter (202) for performing image rejection filtering. One of the outputs (Q) of the filter (202) is terminated, the other (I) is passed to a non-complex ADC (206). The output from the ADC is processed digitally then a quadrature signal generator (212,214) generates quadrature-related IF signals which are passed to a down-converter (216,218) for conversion to baseband signals. By enabling analogue-to-digital conversion and channel filtering to be performed at IF on non-complex signals, significant power savings are possible. Further, the flexibility of the receiver is enhanced, enabling it to operate efficiently in both low-IF and zero-IF modes.

Abstract: A magnetoresitive sensor comprising at least one sensor element for measuring a magnetic field, and a magnet assigned to the sensor element is disclosed. The magnet (14) has structures (18) which lead to a perpendicular guidance of magnetic flux lines (25) from the supporting magnet (14) in the sensing direction (y direction) at least in the sensitive area (26) of the sensor (100). The inventive sensor has a simple structure and does not require subsequent trimming for compensating an offset as in the prior art.

Abstract: The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10), wherein a semiconductor element (1) provided with a number of connection regions (2) is fitted between a first, electroconductive plate (3) and a second plate (4), wherein two connection conductors (3A, 3B) are formed, from the first plate (3), for the two connection regions (2A, 2B) of the element (1), wherein a passivating encapsulation (5) is provided between the plates (3, 4) and around the element (1), and wherein the device (10) is formed by applying a mechanical separating technique in two mutually perpendicular directions (L, M). In a method according to the invention, the connection conductors (3A, 3B) are formed by providing a mask (6) on the first conducting plate (3) in such a manner that a part (3C) of the plate (3) situated between the connection regions (2A, 2B) remains exposed, which part is subsequently removed by etching.

Abstract: A high power Doherty amplifier circuit having at least one input terminal and at least one output terminal comprising at least one carrier transistor (30) forming a main amplifier stage; at least one peak transistor (32) forming a peak amplifier stage; a first input line (27) connecting the input terminal (28) to an input (29) of the carrier transistor (30); a second input line (31) connecting the input terminal (28) to an input (63) of the peak transistor (32); a first output line (33) connecting the output terminal (56) to an output (49) of the carrier transistor (30); and a second output line (35) connecting the output terminal (56) to an output (75) of the peak transistor (32).

Abstract: An amplifier circuit comprises an input transistor Q1 with a first control electrode coupled to the input In and a first main current channel coupled to the internal node 10. An output transistor Q4 has a second control electrode coupled to the internal node 10 and a second main current channel coupled to the output Out of the amplifier. An internal transistor Q2 has a third main current channel coupled to the internal node 10. The internal transistor Q2 serves to modify the impedance at the internal node 10, but a main low-frequency gain path from the first main channel Q1 to the second control electrode does not pass through the third main current channel Q2. The internal node 10 is coupled to ground via the third main current channel Q2 and a resistive element R1 successively. The resistance value of the resistive element R1 causes poles of a transfer function of the amplifier circuit to develop an imaginary frequency (resonant) component.

Abstract: Circuit comprising a noise suppressing circuitry (40) having an input (42) for a first voltage (VDD) and an output (43) for providing a supply voltage (VDDfiltered). The circuit further comprises a MOSFET-based switch (41) with a MOSFET (MP) being situated in a well, whereby a supply voltage (VDDfiltered) is applied to the well (67). The first voltage (VDD) is a global voltage used elsewhere in the same circuit, and the supply voltage (VDDfiltered) is less-noisy than the first voltage (VDD).

Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7c) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.

Abstract: A method of despreading a plurality of GPS spread spectrum signals received by a GPS receiver (24) is disclosed together with a GPS receiver (24) and a mobile communications device (MS1) (especially a mobile cellular telephone) for the same. The method comprises the steps of acquiring a first GPS signal from the stored samples; obtaining frequency information relating to variations in the frequency of the first acquired signal as measured by the GPS receiver; and using the frequency information to acquire a second GPS signal. The frequency information may be used to acquire the second GPS signal in the course of a single dwell and may also, for a digital GPS receiver, relate to variations in the frequency of the first acquired signal present in stored samples.