Abstract: Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between different layers of a multiple layer device. In a preferred embodiment, the variations are such that the field strength is substantially constant along any horizontal or vertical cross section of the termination region.

Abstract: A phase interpolation receiver for receiving angle modulated radio frequency signals. The receiver comprises mixers for down-converting the received angle modulated signal to lower frequency signals, limiters, interpolation filters, and a demodulator. The mixers down-convert the received RF signal to a low IF intermediate frequency signal. The low IF intermediate frequency signal is limited. After further down-conversion to zero IF, using quadrature mixers, the limited signal is phase interpolated. The intermediate frequency is chosen such that the limited signal comprises an unwanted signal at twice the intermediate frequency that acts as a noise spreading signal for spectrally spreading of quantization noise generated by the limiters, and the cut-off frequency of the interpolation filters is chosen such that the unwanted signal and the spread quantization noise are suppressed.

Abstract: In a multi-chip module semiconductor device (1), at least one first semiconductor die (20) is mounted on the base portion (11) of a lead-frame (10). A flip chip IC die (30) is mounted by first bump electrodes (31) to electrode contacts (G, S?) on the at least one first die (20) and by second bump electrodes (32) to terminal pins (14) of the lead frame. The integrated circuit of the flip chip (30) does not require any lead-frame base-portion area for mounting, and low impedance circuit connections are provided by the bump electrodes (31, 32). The first die (20) may be a MOSFET power switching transistor, with a gate driver circuit in the flip chip (30). The circuit impedance for the switching transistor may be further reduced by having distributed parallel gate connections (G), which may alternate with distributed parallel source connections (S?), and furthermore by having distributed and alternating power supply connections (VCC, GND).

Abstract: The invention relates to an antenna diversity comprising a first and a second antenna element one of which is operated in an active mode whereas the other one of which is operated in a parasitic mode. It is the object of the present invention to further minimize the amount of mismatch by still being able to maximize a predetermined signal quality criterion for the electromagnetic signal on the active path between the active antenna and the transceiver. This object is solved by a switching unit 120 for either operating the first antenna element in the parasitic mode and simultaneously operating the second antenna element in the active mode or vice versa and by providing a pre-selection unit 130 as well as a selection unit 140 for selecting an optimal configuration for the antenna diversity ensuring that the amount of said mismatch is below a predetermined threshold value and that simultaneously a predetermined quality criterion for the transceived electromagnetic signal is fulfilled best.

Abstract: A circuit comprises a frequency synthesizing circuit with a voltage-controlled oscillator whose frequency is preset to a preset value. The voltage-controlled oscillator generates an oscillating signal in response to an input voltage. The frequency synthesizing circuit is configured to operate in a locked loop mode under control of an error signal representative of a phase frequency differential between the divided oscillating signal and a reference signal. A digital processing unit can disable the frequency synthesizing circuit to operate in phase locked loop mode. Once the synthesizing circuit is disabled, the digital processing unit determines a first and a second frequency of the oscillating signal in response to respective first and second loop filter input voltage values. The unit further generates a control value from the two frequencies, the frequency divider dividing ratio and the reference signal.

Abstract: The invention relates to a controllable delay circuit for delaying an electrical input signal wherein the controllable delay circuit is arranged for receiving an input signal and at least one control signal, wherein, in use, the delay circuit delays the input signal by a delay for generating an output signal, wherein the delay is a function of the at least one control signal, wherein the delay circuit comprises a first module for generating a base signal and at least one support signal on the basis of the input signal and the at least one control signal, wherein, in use, the phase and/or the amplitude of the at least one support signal is controllable with respect to the phase and/or the amplitude of the base-signal by means of the at least one control signal, wherein the delay circuit also comprises a second module connected to the first module, which second module comprises a signal-conductor and at least one support conductor, wherein the signal conductor and the at least one support conductor extend, at l

Abstract: The invention relates to a supporting device for supporting substrates in a component placement machine including a housing (1), a piston rod (5) arranged in the housing so as to be movable in its longitudinal direction in the housing (1) by pressurized fluid and having one end extending outside the housing (1) and a locking mechanism (7 to 9) by which displacement of the piston rod (5) in its longitudinal direction can be prevented. The locking mechanism (7 to 9) includes clamp (8) movable by an adjuster (7) in a direction transverse to the longitudinal direction of the piston rod (5) between an active position for blocking the piston rod (5) and an idle position in which the piston rod (5) is movable in its longitudinal direction. The clamp (8) have been arranged in the housing (1) so that in the active position said clamping means (8) directly engage the piston rod (5).

Abstract: An amplifier (AMP) is provided with a pair of choppers (CHPi,CHPo) in order to reduce the DC-offset and the noise produced by the amplifier (AMP). To obtain an optimal noise reduction the pair of choppers (CHPi,CHPo) operate on a high frequency. As a result the DC-offset cancellation is not optimal because a so-called charge injection of the switches in the pair of choppers (CHPi,CHPo) produces a DC-offset. To overcome this problem the amplifier (AMP) is further provided with further offset cancellation means which are for example formed by a further pair of choppers (CHPfi,CHPfo). This further pair of choppers (CHPfi,CHPfo) operates on a relatively low frequency. The combination of the pair of choppers (CHPi,CHPo) and the further pair of choppers (CHPfi,CHPfo) guarantees an optimal DC-offset cancellation as well as an optimal noise cancellation.

Abstract: A socket (1) for accommodating and testing a component (2) having several electrical connectors (3) is disclosed, which socket comprises a substantially rectangular frame (4) surrounding a space (5), which frame (4) includes a first row (6) and a second row (7) of electric conductors (8) which are arranged opposite one another, which conductors (8) have first section (9) with a terminal (10) extending into space (5) for contacting an electric connector (3) of the component (2), and a second section (11) projecting from the frame (4). The spacing (12) between the terminals (10) in each row (6, 7) is adjustable. In the method of testing a component (2) in the socket (1), the spacing (12) between the terminals (10) in each row (6, 7) is adjusted to establish electrical contact between the electrical connectors (3) of the component (2) and its corresponding terminal (10) by placing the component (2) in the socket (1).

Abstract: A quadrature device 1 for a communication device, receiver, transmitter, transceiver, telephone, mixer, modulator or demodulator comprises I and Q signal paths and corresponding signal paths components 2I, 2Q; 4I, 4Q; 9I, 9Q showing a mismatch. The device 1 comprises switching circuitry 3, 3?, 6, 3?, 3?? for data dependently exchanging the I and Q signals in the I and Q paths in order to improve adverse effects, such as reduction of leakage of quantisation noise from the image band to the signal band in a quadrature modulator. Even mismatch effects between digital to analog converters (DAC's) in a feedback path of a sigma delta (??) modulator are compensated.

Abstract: A turbo decoder employing the sliding window algorithm is computational intensive. Computational requirements are reduced in iterative decoders, at the expense of increased memory usage, by storing the stakes between iterations. The stakes used in this improved sliding windows algorithm can be compressed, resulting in a decoder with minimal additional memory requirements, while retaining the advantages in computational requirements obtained from storing the stakes between iterations.

Abstract: A device for the inspection of surfaces, notably for the inspection of a surface of a semiconductor (14), which device comprises at least one laser light source (1) and a detector for detecting the light (13) that is reflected from the surface (10) to be inspected; the device also includes at least one mode filter (15; 15.1) for filtering the reflected light.

Abstract: A method of, and a receiver for, detecting the presence of digitally modulated data signals in which the receiver is periodically energised to detect the presence of the signals. The received signals/noise are converted using a quadrature frequency translation stage (16, 17, 18) into a complex signal which after differential decoding (28) contain n samples for each transmitted bit. A running sum of successive groups of m samples, where m<n, is obtained and an absolute value (Xi) of each group is derived. A weighting value (Wi) is selected by comparing each absolute value with predetermined statistics of expected values and the weighting value selected is multiplied by the associated absolute value to produce a product (S). The product is compared in a comparator (56) with a further threshold level (58) to derive an indication of the presence of data in the received signals. If the indication is negative the receiver is powered down to save power.

Abstract: The invention relates to a transmitter and a method of generating a transmission signal, which transmitter includes a modulation device for generating two uncompensated transmission signals Y, Z by respective modulation of at least one baseband signal I, Q with an oscillation signal XLOQ, XLOI, the two uncompensated transmission signals Y, Z containing at least one respective interference component, which interference components are phase shifted by a given amount relative to one another. These interference components are eliminated by a compensation circuit that includes an all-pass. The all-pass rotates the phase of the interference component to be eliminated in one of the uncompensated transmission signals to overall a phase difference of 180° relative to the phase of the corresponding interference component in the other uncompensated transmission signal.

Abstract: Improvement is afforded in the recognition of wide-band data transmitted in the form of a data sequence to a network element of an analog, cellular network, notably a mobile radio set or a base station. The sequence includes a starting synchronization (DOT1), a word synchronization (WS), a data word (REP1) and number of repeats of a synchronization (DOT), a word synchronization (WS) and the data word (REP 1-REP 11). The network element recognizes, from received sequences, that a transmission of a sequence occurs when a starting synchronization (DOT 1) has been recognized, or alternatively when one of the further synchronizations (DOT) that is succeeded by a correct word synchronization (WS) has been recognized, and evaluates the data words (REP 1-REP 11) received each time subsequent to a recognized starting synchronization (DOT 1) that is succeeded by a word synchronization (WS), or received subsequent to a recognized further synchronization (DOT) that is succeeded by a correct word synchronization (WS).

Abstract: A resolved component of a multi-path signal is assigned to a rake finger of a spread spectrum rake receiver. The resolved component is variably delayed. On the variably delayed resolved component, an early-late detection is performed so as to determine whether the resolved component arrived early or late with respect to an optimum arrival time. A first pulse is generated if the early-late detection determines that said resolved component arrived early. A second pulse is generated if the early-late detection determines that the resolved component arrived late. The first and second pulses are counted. The first pulse causes counting in a first direction and the second pulse causes counting in a second direction. From the counting, a fractional-chip delay timing adjustment signal is derived, and fed back to adjust the variably delaying of the resolved component. Also from the counting a chip delay phase adjustment signal is derived, and fed back to control a phase of a pseudo-noise generator.

Abstract: A bit rate detector for detecting the speed of transmission of a data signal having one of at least two alternative bit rates, comprises a differential decoder (28) for differentially decoding received digitally modulated signals into oversampled complex signals, a summing stage (38, 40 and 42) for forming a running sum of successive groups of samples, and a bit rate detector (58). The bit rate detector (58) having a stage (62, 66 (FIG. 5)) for determining if the running sum represents a signal as opposed to interference, and if the running sum represents a signal, determining the sign of the running sum, a stage (74 (FIG. 5)) for assigning one of two binary values dependent on whether the sign is positive or negative, a shift register (82 (FIG. 5)) for storing successive binary values, a comparator (88 (FIG.

Abstract: A transistor substrate for a liquid crystal display comprises an array of insulated-gate staggered TFTs and a capacitor (36) associated with each transistor. The gate insulator (400,420) comprises a first inorganic layer (400) and a second, polymer or spin-on glass layer (420), of which layers only the polymer or spin-on glass layer (420) extends to the capacitor (36) to define the capacitor dielectric.

Abstract: A method of despreading GPS spread spectrum signals containing pseudorandom noise (PRN) code sequences and received by a GPS receiver (24) is disclosed together with a GPS receiver (24) and a mobile communications device (MS1) (especially a mobile cellular telephone) for the same. The method comprises the steps of providing Doppler information relating to an estimate of the variation in Doppler shift as observed on the target signal by the GPS receiver and which is attributable to the motion of the GPS satellite; and correlating the target signal with a reference signal containing corresponding PRN code sequences, wherein, in the course of a single dwell, the correlation is modified as a function of the Doppler information.

Abstract: The invention provides a tool to select reliable organic LED devices, where the risk for failure before the end of its lifetime is low. This tool comprises the steps of: i) subjecting the device to a high electric field over the electroluminescent layer. This leads to a division of the devices into two, clearly separated, populations, namely one population with a low leakage current (current through the electroluminescent layer in reverse voltage operation) and one population with a high leakage current. In this step, the first population is selected in accordance with a current criterion. ii) detecting instabilities in the leakage current, referred to as noise. It has been established that these instabilities arise in particular at reverse driving voltages between 1 and 10 Volts. These instabilities are a measure of the occurrence of early failures during operation. In this step, the devices are selected in accordance with a noise criterion.